2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
10 RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0');
11 ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (others => '0')
18 stall_in : in std_ulogic;
19 flush_in : in std_ulogic;
20 stop_in : in std_ulogic;
21 alt_reset_in : in std_ulogic;
23 -- redirect from execution unit
24 e_in : in Execute1ToFetch1Type;
27 i_out : out Fetch1ToIcacheType
31 architecture behaviour of fetch1 is
32 type stop_state_t is (RUNNING, STOPPED, RESTARTING);
33 type reg_internal_t is record
34 stop_state: stop_state_t;
36 signal r, r_next : Fetch1ToIcacheType;
37 signal r_int, r_next_int : reg_internal_t;
42 if rising_edge(clk) then
44 report "fetch1 rst:" & std_ulogic'image(rst) &
45 " IR:" & std_ulogic'image(e_in.virt_mode) &
46 " P:" & std_ulogic'image(e_in.priv_mode) &
47 " R:" & std_ulogic'image(e_in.redirect) &
48 " S:" & std_ulogic'image(stall_in) &
49 " T:" & std_ulogic'image(stop_in) &
50 " nia:" & to_hstring(r_next.nia) &
51 " SM:" & std_ulogic'image(r_next.stop_mark);
59 variable v : Fetch1ToIcacheType;
60 variable v_int : reg_internal_t;
61 variable increment : boolean;
67 if alt_reset_in = '1' then
68 v.nia := ALT_RESET_ADDRESS;
70 v.nia := RESET_ADDRESS;
74 v_int.stop_state := RUNNING;
75 elsif e_in.redirect = '1' then
76 v.nia := e_in.redirect_nia;
77 v.virt_mode := e_in.virt_mode;
78 v.priv_mode := e_in.priv_mode;
79 elsif stall_in = '0' then
81 -- For debug stop/step to work properly we need a little bit of
82 -- trickery here. If we just stop incrementing and send stop marks
83 -- when stop_in is set, then we'll increment on the cycle it clears
84 -- and end up never executing the instruction we were stopped on.
86 -- Avoid this along with the opposite issue when stepping (stop is
87 -- cleared for only one cycle) is handled by the state machine below
89 -- By default, increment addresses
91 case v_int.stop_state is
93 -- If we are running and stop_in is set, then stop incrementing,
94 -- we are now stopped.
97 v_int.stop_state := STOPPED;
100 -- When stopped, never increment. If stop is cleared, go to state
101 -- "restarting" but still don't increment that cycle. stop_in is
102 -- now 0 so we'll send the NIA down without a stop mark.
104 if stop_in = '0' then
105 v_int.stop_state := RESTARTING;
108 -- We have just sent the NIA down, we can start incrementing again.
109 -- If stop_in is still not set, go back to running normally.
110 -- If stop_in is set again (that was a one-cycle "step"), go
111 -- back to "stopped" state which means we'll stop incrementing
112 -- on the next cycle. This ensures we increment the PC once after
113 -- sending one instruction without a stop mark. Since stop_in is
114 -- now set, the new PC will be sent with a stop mark and thus not
116 if stop_in = '0' then
117 v_int.stop_state := RUNNING;
119 v_int.stop_state := STOPPED;
124 v.nia := std_logic_vector(unsigned(v.nia) + 4);
129 v.stop_mark := stop_in;
134 -- Update outputs to the icache
139 end architecture behaviour;