2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
7 use work.wishbone_types.all;
14 stall_in : in std_ulogic;
15 flush_in : in std_ulogic;
17 -- Results from icache
18 i_in : in IcacheToFetch2Type;
21 f_out : out Fetch2ToDecode1Type
25 architecture behaviour of fetch2 is
27 -- The icache cannot stall, so we need to stash a cycle
28 -- of output from it when we stall.
29 type reg_internal_type is record
30 stash : IcacheToFetch2Type;
31 stash_valid : std_ulogic;
35 signal r_int, rin_int : reg_internal_type;
36 signal r, rin : Fetch2ToDecode1Type;
41 if rising_edge(clk) then
44 report "fetch2 rst:" & std_ulogic'image(rst) &
45 " S:" & std_ulogic'image(stall_in) &
46 " F:" & std_ulogic'image(flush_in) &
47 " T:" & std_ulogic'image(rin.stop_mark) &
48 " V:" & std_ulogic'image(rin.valid) &
49 " nia:" & to_hstring(rin.nia);
52 -- Output state remains unchanged on stall, unless we are flushing
53 if rst = '1' or flush_in = '1' or stall_in = '0' then
57 -- Internal state is updated on every clock
63 variable v : Fetch2ToDecode1Type;
64 variable v_int : reg_internal_type;
65 variable v_i_in : IcacheToFetch2Type;
70 -- If stalling, stash away the current input from the icache
71 if stall_in = '1' and v_int.stash_valid = '0' then
73 v_int.stash_valid := '1';
76 -- If unstalling, source input from the stash and invalidate it,
77 -- otherwise source normally from the icache.
80 if v_int.stash_valid = '1' and stall_in = '0' then
81 v_i_in := v_int.stash;
82 v_int.stash_valid := '0';
85 v.valid := v_i_in.valid;
86 v.stop_mark := v_i_in.stop_mark;
88 v.insn := v_i_in.insn;
90 -- Clear stash internal valid bit on flush. We still mark
91 -- the stash itself as valid since we still want to override
92 -- whatever comes form icache when unstalling, but we'll
93 -- override it with something invalid.
95 if flush_in = '1' then
96 v_int.stash.valid := '0';
99 -- If we are flushing or the instruction comes with a stop mark
100 -- we tag it as invalid so it doesn't get decoded and executed
101 if flush_in = '1' or v.stop_mark = '1' then
105 -- Clear stash on reset
107 v_int.stash_valid := '0';
118 end architecture behaviour;