fetch2.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.common.all;
   7 use work.wishbone_types.all;
   8
   9 entity fetch2 is
  10         port(
  11                 clk          : in std_ulogic;
  12                 rst          : in std_ulogic;
  13
  14                 stall_in     : in std_ulogic;
  15                 stall_out    : out std_ulogic;
  16
  17                 flush_in     : in std_ulogic;
  18
  19                 i_in         : in IcacheToFetch2Type;
  20                 i_out        : out Fetch2ToIcacheType;
  21
  22                 f_in         : in Fetch1ToFetch2Type;
  23
  24                 f_out        : out Fetch2ToDecode1Type
  25         );
  26 end entity fetch2;
  27
  28 architecture behaviour of fetch2 is
  29         signal r, rin : Fetch2ToDecode1Type;
  30 begin
  31         regs : process(clk)
  32         begin
  33                 if rising_edge(clk) then
  34                         -- Output state remains unchanged on stall, unless we are flushing
  35                         if rst = '1' or flush_in = '1' or stall_in = '0' then
  36                                 r <= rin;
  37                         end if;
  38                 end if;
  39         end process;
  40
  41         comb : process(all)
  42                 variable v : Fetch2ToDecode1Type;
  43         begin
  44                 v := r;
  45
  46                 -- asynchronous icache lookup
  47                 i_out.req <= '1';
  48                 i_out.addr <= f_in.nia;
  49                 v.valid := i_in.ack;
  50                 v.nia := f_in.nia;
  51                 v.insn := i_in.insn;
  52                 stall_out <= not i_in.ack;
  53
  54
  55                 if flush_in = '1' then
  56                         v.valid := '0';
  57                 end if;
  58
  59                 -- Update registers
  60                 rin <= v;
  61
  62                 -- Update outputs
  63                 f_out <= r;
  64         end process;
  65 end architecture behaviour;