fpga/arty_a7.xdc

   1 ################################################################################
   2 # clkin, reset, uart pins...
   3 ################################################################################
   4
   5 set_property -dict { PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
   6
   7 set_property -dict { PACKAGE_PIN C2  IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
   8
   9 set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
  10 set_property -dict { PACKAGE_PIN A9  IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
  11
  12 ################################################################################
  13 # Pmod Header JC: UART (bottom)
  14 ################################################################################
  15
  16 #set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
  17 #set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
  18 #set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
  19 #set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
  20
  21 ################################################################################
  22 # RGB LEDs
  23 ################################################################################
  24
  25 set_property -dict { PACKAGE_PIN E1  IOSTANDARD LVCMOS33 } [get_ports { led0_b }];
  26 set_property -dict { PACKAGE_PIN F6  IOSTANDARD LVCMOS33 } [get_ports { led0_g }];
  27 set_property -dict { PACKAGE_PIN G6  IOSTANDARD LVCMOS33 } [get_ports { led0_r }];
  28
  29 ################################################################################
  30 # SPI Flash
  31 ################################################################################
  32
  33 set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
  34 set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_clk }];
  35 set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
  36 set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
  37 set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
  38 set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
  39
  40 # Put registers into IOBs to improve timing
  41 set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/*sck_1*}]
  42 set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_delay_1.dat_i_l*}]
  43
  44
  45 ################################################################################
  46 # DRAM (generated by LiteX)
  47 ################################################################################
  48
  49 # ddram:0.a
  50 set_property LOC R2 [get_ports {ddram_a[0]}]
  51 set_property SLEW FAST [get_ports {ddram_a[0]}]
  52 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
  53
  54 # ddram:0.a
  55 set_property LOC M6 [get_ports {ddram_a[1]}]
  56 set_property SLEW FAST [get_ports {ddram_a[1]}]
  57 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
  58
  59 # ddram:0.a
  60 set_property LOC N4 [get_ports {ddram_a[2]}]
  61 set_property SLEW FAST [get_ports {ddram_a[2]}]
  62 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
  63
  64 # ddram:0.a
  65 set_property LOC T1 [get_ports {ddram_a[3]}]
  66 set_property SLEW FAST [get_ports {ddram_a[3]}]
  67 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
  68
  69 # ddram:0.a
  70 set_property LOC N6 [get_ports {ddram_a[4]}]
  71 set_property SLEW FAST [get_ports {ddram_a[4]}]
  72 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
  73
  74 # ddram:0.a
  75 set_property LOC R7 [get_ports {ddram_a[5]}]
  76 set_property SLEW FAST [get_ports {ddram_a[5]}]
  77 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
  78
  79 # ddram:0.a
  80 set_property LOC V6 [get_ports {ddram_a[6]}]
  81 set_property SLEW FAST [get_ports {ddram_a[6]}]
  82 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
  83
  84 # ddram:0.a
  85 set_property LOC U7 [get_ports {ddram_a[7]}]
  86 set_property SLEW FAST [get_ports {ddram_a[7]}]
  87 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
  88
  89 # ddram:0.a
  90 set_property LOC R8 [get_ports {ddram_a[8]}]
  91 set_property SLEW FAST [get_ports {ddram_a[8]}]
  92 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
  93
  94 # ddram:0.a
  95 set_property LOC V7 [get_ports {ddram_a[9]}]
  96 set_property SLEW FAST [get_ports {ddram_a[9]}]
  97 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
  98
  99 # ddram:0.a
 100 set_property LOC R6 [get_ports {ddram_a[10]}]
 101 set_property SLEW FAST [get_ports {ddram_a[10]}]
 102 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
 103
 104 # ddram:0.a
 105 set_property LOC U6 [get_ports {ddram_a[11]}]
 106 set_property SLEW FAST [get_ports {ddram_a[11]}]
 107 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
 108
 109 # ddram:0.a
 110 set_property LOC T6 [get_ports {ddram_a[12]}]
 111 set_property SLEW FAST [get_ports {ddram_a[12]}]
 112 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
 113
 114 # ddram:0.a
 115 set_property LOC T8 [get_ports {ddram_a[13]}]
 116 set_property SLEW FAST [get_ports {ddram_a[13]}]
 117 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
 118
 119 # ddram:0.ba
 120 set_property LOC R1 [get_ports {ddram_ba[0]}]
 121 set_property SLEW FAST [get_ports {ddram_ba[0]}]
 122 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
 123
 124 # ddram:0.ba
 125 set_property LOC P4 [get_ports {ddram_ba[1]}]
 126 set_property SLEW FAST [get_ports {ddram_ba[1]}]
 127 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
 128
 129 # ddram:0.ba
 130 set_property LOC P2 [get_ports {ddram_ba[2]}]
 131 set_property SLEW FAST [get_ports {ddram_ba[2]}]
 132 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
 133
 134 # ddram:0.ras_n
 135 set_property LOC P3 [get_ports {ddram_ras_n}]
 136 set_property SLEW FAST [get_ports {ddram_ras_n}]
 137 set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
 138
 139 # ddram:0.cas_n
 140 set_property LOC M4 [get_ports {ddram_cas_n}]
 141 set_property SLEW FAST [get_ports {ddram_cas_n}]
 142 set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
 143
 144 # ddram:0.we_n
 145 set_property LOC P5 [get_ports {ddram_we_n}]
 146 set_property SLEW FAST [get_ports {ddram_we_n}]
 147 set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
 148
 149 # ddram:0.cs_n
 150 set_property LOC U8 [get_ports {ddram_cs_n}]
 151 set_property SLEW FAST [get_ports {ddram_cs_n}]
 152 set_property IOSTANDARD SSTL135 [get_ports {ddram_cs_n}]
 153
 154 # ddram:0.dm
 155 set_property LOC L1 [get_ports {ddram_dm[0]}]
 156 set_property SLEW FAST [get_ports {ddram_dm[0]}]
 157 set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
 158
 159 # ddram:0.dm
 160 set_property LOC U1 [get_ports {ddram_dm[1]}]
 161 set_property SLEW FAST [get_ports {ddram_dm[1]}]
 162 set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
 163
 164 # ddram:0.dq
 165 set_property LOC K5 [get_ports {ddram_dq[0]}]
 166 set_property SLEW FAST [get_ports {ddram_dq[0]}]
 167 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
 168 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
 169
 170 # ddram:0.dq
 171 set_property LOC L3 [get_ports {ddram_dq[1]}]
 172 set_property SLEW FAST [get_ports {ddram_dq[1]}]
 173 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
 174 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
 175
 176 # ddram:0.dq
 177 set_property LOC K3 [get_ports {ddram_dq[2]}]
 178 set_property SLEW FAST [get_ports {ddram_dq[2]}]
 179 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
 180 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
 181
 182 # ddram:0.dq
 183 set_property LOC L6 [get_ports {ddram_dq[3]}]
 184 set_property SLEW FAST [get_ports {ddram_dq[3]}]
 185 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
 186 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
 187
 188 # ddram:0.dq
 189 set_property LOC M3 [get_ports {ddram_dq[4]}]
 190 set_property SLEW FAST [get_ports {ddram_dq[4]}]
 191 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
 192 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
 193
 194 # ddram:0.dq
 195 set_property LOC M1 [get_ports {ddram_dq[5]}]
 196 set_property SLEW FAST [get_ports {ddram_dq[5]}]
 197 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
 198 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
 199
 200 # ddram:0.dq
 201 set_property LOC L4 [get_ports {ddram_dq[6]}]
 202 set_property SLEW FAST [get_ports {ddram_dq[6]}]
 203 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
 204 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
 205
 206 # ddram:0.dq
 207 set_property LOC M2 [get_ports {ddram_dq[7]}]
 208 set_property SLEW FAST [get_ports {ddram_dq[7]}]
 209 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
 210 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
 211
 212 # ddram:0.dq
 213 set_property LOC V4 [get_ports {ddram_dq[8]}]
 214 set_property SLEW FAST [get_ports {ddram_dq[8]}]
 215 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
 216 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
 217
 218 # ddram:0.dq
 219 set_property LOC T5 [get_ports {ddram_dq[9]}]
 220 set_property SLEW FAST [get_ports {ddram_dq[9]}]
 221 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
 222 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
 223
 224 # ddram:0.dq
 225 set_property LOC U4 [get_ports {ddram_dq[10]}]
 226 set_property SLEW FAST [get_ports {ddram_dq[10]}]
 227 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
 228 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
 229
 230 # ddram:0.dq
 231 set_property LOC V5 [get_ports {ddram_dq[11]}]
 232 set_property SLEW FAST [get_ports {ddram_dq[11]}]
 233 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
 234 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
 235
 236 # ddram:0.dq
 237 set_property LOC V1 [get_ports {ddram_dq[12]}]
 238 set_property SLEW FAST [get_ports {ddram_dq[12]}]
 239 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
 240 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
 241
 242 # ddram:0.dq
 243 set_property LOC T3 [get_ports {ddram_dq[13]}]
 244 set_property SLEW FAST [get_ports {ddram_dq[13]}]
 245 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
 246 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
 247
 248 # ddram:0.dq
 249 set_property LOC U3 [get_ports {ddram_dq[14]}]
 250 set_property SLEW FAST [get_ports {ddram_dq[14]}]
 251 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
 252 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
 253
 254 # ddram:0.dq
 255 set_property LOC R3 [get_ports {ddram_dq[15]}]
 256 set_property SLEW FAST [get_ports {ddram_dq[15]}]
 257 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
 258 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
 259
 260 # ddram:0.dqs_p
 261 set_property LOC N2 [get_ports {ddram_dqs_p[0]}]
 262 set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
 263 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
 264 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
 265
 266 # ddram:0.dqs_p
 267 set_property LOC U2 [get_ports {ddram_dqs_p[1]}]
 268 set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
 269 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
 270 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
 271
 272 # ddram:0.dqs_n
 273 set_property LOC N1 [get_ports {ddram_dqs_n[0]}]
 274 set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
 275 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
 276 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
 277
 278 # ddram:0.dqs_n
 279 set_property LOC V2 [get_ports {ddram_dqs_n[1]}]
 280 set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
 281 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
 282 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
 283
 284 # ddram:0.clk_p
 285 set_property LOC U9 [get_ports {ddram_clk_p}]
 286 set_property SLEW FAST [get_ports {ddram_clk_p}]
 287 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
 288
 289 # ddram:0.clk_n
 290 set_property LOC V9 [get_ports {ddram_clk_n}]
 291 set_property SLEW FAST [get_ports {ddram_clk_n}]
 292 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
 293
 294 # ddram:0.cke
 295 set_property LOC N5 [get_ports {ddram_cke}]
 296 set_property SLEW FAST [get_ports {ddram_cke}]
 297 set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
 298
 299 # ddram:0.odt
 300 set_property LOC R5 [get_ports {ddram_odt}]
 301 set_property SLEW FAST [get_ports {ddram_odt}]
 302 set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
 303
 304 # ddram:0.reset_n
 305 set_property LOC K6 [get_ports {ddram_reset_n}]
 306 set_property SLEW FAST [get_ports {ddram_reset_n}]
 307 set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
 308
 309 ################################################################################
 310 # Design constraints and bitsteam attributes
 311 ################################################################################
 312
 313 #Internal VREF
 314 set_property INTERNAL_VREF 0.675 [get_iobanks 34]
 315
 316 set_property CONFIG_VOLTAGE 3.3 [current_design]
 317 set_property CFGBVS VCCO [current_design]
 318
 319 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 320 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
 321 set_property CONFIG_MODE SPIx4 [current_design]
 322
 323 ################################################################################
 324 # Clock constraints
 325 ################################################################################
 326
 327 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
 328
 329 ################################################################################
 330 # False path constraints (from LiteX as they relate to LiteDRAM)
 331 ################################################################################
 332
 333 set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
 334
 335 set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]