fpga/arty_a7.xdc

   1 ################################################################################
   2 # clkin, reset, uart pins...
   3 ################################################################################
   4
   5 set_property -dict { PACKAGE_PIN E3  IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
   6
   7 set_property -dict { PACKAGE_PIN C2  IOSTANDARD LVCMOS33 } [get_ports { ext_rst_n }];
   8
   9 set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }];
  10 set_property -dict { PACKAGE_PIN A9  IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }];
  11
  12 ################################################################################
  13 # Pmod Header JC: UART (bottom)
  14 ################################################################################
  15
  16 set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
  17 set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
  18 set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
  19 set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
  20
  21 ################################################################################
  22 # RGB LEDs
  23 ################################################################################
  24
  25 set_property -dict { PACKAGE_PIN E1  IOSTANDARD LVCMOS33 } [get_ports { led0_b }];
  26 set_property -dict { PACKAGE_PIN F6  IOSTANDARD LVCMOS33 } [get_ports { led0_g }];
  27 set_property -dict { PACKAGE_PIN G6  IOSTANDARD LVCMOS33 } [get_ports { led0_r }];
  28 #set_property -dict { PACKAGE_PIN G4  IOSTANDARD LVCMOS33 } [get_ports { led1_b }];
  29 #set_property -dict { PACKAGE_PIN J4  IOSTANDARD LVCMOS33 } [get_ports { led1_g }];
  30 #set_property -dict { PACKAGE_PIN G3  IOSTANDARD LVCMOS33 } [get_ports { led1_r }];
  31 #set_property -dict { PACKAGE_PIN H4  IOSTANDARD LVCMOS33 } [get_ports { led2_b }];
  32 #set_property -dict { PACKAGE_PIN J2  IOSTANDARD LVCMOS33 } [get_ports { led2_g }];
  33 #set_property -dict { PACKAGE_PIN J3  IOSTANDARD LVCMOS33 } [get_ports { led2_r }];
  34 #set_property -dict { PACKAGE_PIN K2  IOSTANDARD LVCMOS33 } [get_ports { led3_b }];
  35 #set_property -dict { PACKAGE_PIN H6  IOSTANDARD LVCMOS33 } [get_ports { led3_g }];
  36 #set_property -dict { PACKAGE_PIN K1  IOSTANDARD LVCMOS33 } [get_ports { led3_r }];
  37
  38 ################################################################################
  39 # Normal LEDs
  40 ################################################################################
  41
  42 set_property -dict { PACKAGE_PIN H5  IOSTANDARD LVCMOS33 } [get_ports { led4 }];
  43 set_property -dict { PACKAGE_PIN J5  IOSTANDARD LVCMOS33 } [get_ports { led5 }];
  44 set_property -dict { PACKAGE_PIN T9  IOSTANDARD LVCMOS33 } [get_ports { led6 }];
  45 set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led7 }];
  46
  47 ################################################################################
  48 # SPI Flash
  49 ################################################################################
  50
  51 set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n }];
  52 set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_clk }];
  53 set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi }];
  54 set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso }];
  55 set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n }];
  56 set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }];
  57
  58 # Put registers into IOBs to improve timing
  59 set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/*sck_1*}]
  60 set_property IOB true [get_cells -hierarchical -filter {NAME =~*/spi_rxtx/input_delay_1.dat_i_l*}]
  61
  62 ################################################################################
  63 # PMOD header JA (standard, 200 ohm protection resisters)
  64 ################################################################################
  65
  66 #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_1 }];
  67 #set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_2 }];
  68 #set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_3 }];
  69 #set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_4 }];
  70 #set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_7 }];
  71 #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_8 }];
  72 #set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_9 }];
  73 #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { pmod_ja_10 }];
  74
  75 ################################################################################
  76 # PMOD header JB (high-speed, no protection resisters)
  77 ################################################################################
  78
  79 #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_1 }];
  80 #set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_2 }];
  81 #set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_3 }];
  82 #set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_4 }];
  83 #set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_7 }];
  84 #set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_8 }];
  85 #set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_9 }];
  86 #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { pmod_jb_10 }];
  87
  88 ################################################################################
  89 # PMOD header JC (high-speed, no protection resisters)
  90 ################################################################################
  91
  92 #set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_1 }];
  93 #set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_2 }];
  94 #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_3 }];
  95 #set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_4 }];
  96 #set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_7 }];
  97 #set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_8 }];
  98 #set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_9 }];
  99 #set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { pmod_jc_10 }];
 100
 101 ################################################################################
 102 # PMOD header JD (standard, 200 ohm protection resisters)
 103 ################################################################################
 104
 105 #set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_1 }];
 106 #set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_2 }];
 107 #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_3 }];
 108 #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_4 }];
 109 #set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_7 }];
 110 #set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_8 }];
 111 #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_9 }];
 112 #set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { pmod_jd_10 }];
 113
 114 ################################################################################
 115 # Arduino/chipKIT shield connector
 116 ################################################################################
 117
 118 #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { shield_io0 }];
 119 #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { shield_io1 }];
 120 #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { shield_io2 }];
 121 #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { shield_io3 }];
 122 #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { shield_io4 }];
 123 #set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { shield_io5 }];
 124 #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { shield_io6 }];
 125 #set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { shield_io7 }];
 126 #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { shield_io8 }];
 127 #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { shield_io9 }];
 128 #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { shield_io10 }];
 129 #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { shield_io11 }];
 130 #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { shield_io12 }];
 131 #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { shield_io13 }];
 132 #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { shield_io26 }];
 133 #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { shield_io27 }];
 134 #set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { shield_io28 }];
 135 #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { shield_io29 }];
 136 #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { shield_io30 }];
 137 #set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { shield_io31 }];
 138 #set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { shield_io32 }];
 139 #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { shield_io33 }];
 140 #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { shield_io34 }];
 141 #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { shield_io35 }];
 142 #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { shield_io36 }];
 143 #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { shield_io37 }];
 144 #set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { shield_io38 }];
 145 #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { shield_io39 }];
 146 #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { shield_io40 }];
 147 #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { shield_io41 }];
 148 #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { shield_ioa }];
 149 #set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { shield_scl }];
 150 #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { shield_sda }];
 151 #set_property -dict { PACKAGE_PIN C2  IOSTANDARD LVCMOS33 } [get_ports { shield_rst }];
 152
 153 #set_property -dict { PACKAGE_PIN C1  IOSTANDARD LVCMOS33 } [get_ports { spi_hdr_ss }];
 154 #set_property -dict { PACKAGE_PIN F1  IOSTANDARD LVCMOS33 } [get_ports { spi_hdr_clk }];
 155 #set_property -dict { PACKAGE_PIN H1  IOSTANDARD LVCMOS33 } [get_ports { spi_hdr_mosi }];
 156 #set_property -dict { PACKAGE_PIN G1  IOSTANDARD LVCMOS33 } [get_ports { spi_hdr_miso }];
 157
 158 ################################################################################
 159 # Ethernet (generated by LiteX)
 160 ################################################################################
 161
 162 # eth_ref_clk:0
 163 set_property LOC G18 [get_ports {eth_ref_clk}]
 164 set_property IOSTANDARD LVCMOS33 [get_ports {eth_ref_clk}]
 165
 166 # eth_clocks:0.tx
 167 set_property LOC H16 [get_ports {eth_clocks_tx}]
 168 set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]
 169
 170 # eth_clocks:0.rx
 171 set_property LOC F15 [get_ports {eth_clocks_rx}]
 172 set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]
 173
 174 # eth:0.rst_n
 175 set_property LOC C16 [get_ports {eth_rst_n}]
 176 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]
 177
 178 # eth:0.mdio
 179 set_property LOC K13 [get_ports {eth_mdio}]
 180 set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]
 181
 182 # eth:0.mdc
 183 set_property LOC F16 [get_ports {eth_mdc}]
 184 set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]
 185
 186 # eth:0.rx_dv
 187 set_property LOC G16 [get_ports {eth_rx_dv}]
 188 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_dv}]
 189
 190 # eth:0.rx_er
 191 set_property LOC C17 [get_ports {eth_rx_er}]
 192 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_er}]
 193
 194 # eth:0.rx_data
 195 set_property LOC D18 [get_ports {eth_rx_data[0]}]
 196 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]
 197
 198 # eth:0.rx_data
 199 set_property LOC E17 [get_ports {eth_rx_data[1]}]
 200 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]
 201
 202 # eth:0.rx_data
 203 set_property LOC E18 [get_ports {eth_rx_data[2]}]
 204 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]
 205
 206 # eth:0.rx_data
 207 set_property LOC G17 [get_ports {eth_rx_data[3]}]
 208 set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]
 209
 210 # eth:0.tx_en
 211 set_property LOC H15 [get_ports {eth_tx_en}]
 212 set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_en}]
 213
 214 # eth:0.tx_data
 215 set_property LOC H14 [get_ports {eth_tx_data[0]}]
 216 set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]
 217
 218 # eth:0.tx_data
 219 set_property LOC J14 [get_ports {eth_tx_data[1]}]
 220 set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]
 221
 222 # eth:0.tx_data
 223 set_property LOC J13 [get_ports {eth_tx_data[2]}]
 224 set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]
 225
 226 # eth:0.tx_data
 227 set_property LOC H17 [get_ports {eth_tx_data[3]}]
 228 set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]
 229
 230 # eth:0.col
 231 set_property LOC D17 [get_ports {eth_col}]
 232 set_property IOSTANDARD LVCMOS33 [get_ports {eth_col}]
 233
 234 # eth:0.crs
 235 set_property LOC G14 [get_ports {eth_crs}]
 236 set_property IOSTANDARD LVCMOS33 [get_ports {eth_crs}]
 237
 238 ################################################################################
 239 # DRAM (generated by LiteX)
 240 ################################################################################
 241
 242 # ddram:0.a
 243 set_property LOC R2 [get_ports {ddram_a[0]}]
 244 set_property SLEW FAST [get_ports {ddram_a[0]}]
 245 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
 246
 247 # ddram:0.a
 248 set_property LOC M6 [get_ports {ddram_a[1]}]
 249 set_property SLEW FAST [get_ports {ddram_a[1]}]
 250 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
 251
 252 # ddram:0.a
 253 set_property LOC N4 [get_ports {ddram_a[2]}]
 254 set_property SLEW FAST [get_ports {ddram_a[2]}]
 255 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
 256
 257 # ddram:0.a
 258 set_property LOC T1 [get_ports {ddram_a[3]}]
 259 set_property SLEW FAST [get_ports {ddram_a[3]}]
 260 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
 261
 262 # ddram:0.a
 263 set_property LOC N6 [get_ports {ddram_a[4]}]
 264 set_property SLEW FAST [get_ports {ddram_a[4]}]
 265 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
 266
 267 # ddram:0.a
 268 set_property LOC R7 [get_ports {ddram_a[5]}]
 269 set_property SLEW FAST [get_ports {ddram_a[5]}]
 270 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
 271
 272 # ddram:0.a
 273 set_property LOC V6 [get_ports {ddram_a[6]}]
 274 set_property SLEW FAST [get_ports {ddram_a[6]}]
 275 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
 276
 277 # ddram:0.a
 278 set_property LOC U7 [get_ports {ddram_a[7]}]
 279 set_property SLEW FAST [get_ports {ddram_a[7]}]
 280 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
 281
 282 # ddram:0.a
 283 set_property LOC R8 [get_ports {ddram_a[8]}]
 284 set_property SLEW FAST [get_ports {ddram_a[8]}]
 285 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
 286
 287 # ddram:0.a
 288 set_property LOC V7 [get_ports {ddram_a[9]}]
 289 set_property SLEW FAST [get_ports {ddram_a[9]}]
 290 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
 291
 292 # ddram:0.a
 293 set_property LOC R6 [get_ports {ddram_a[10]}]
 294 set_property SLEW FAST [get_ports {ddram_a[10]}]
 295 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
 296
 297 # ddram:0.a
 298 set_property LOC U6 [get_ports {ddram_a[11]}]
 299 set_property SLEW FAST [get_ports {ddram_a[11]}]
 300 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
 301
 302 # ddram:0.a
 303 set_property LOC T6 [get_ports {ddram_a[12]}]
 304 set_property SLEW FAST [get_ports {ddram_a[12]}]
 305 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
 306
 307 # ddram:0.a
 308 set_property LOC T8 [get_ports {ddram_a[13]}]
 309 set_property SLEW FAST [get_ports {ddram_a[13]}]
 310 set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
 311
 312 # ddram:0.ba
 313 set_property LOC R1 [get_ports {ddram_ba[0]}]
 314 set_property SLEW FAST [get_ports {ddram_ba[0]}]
 315 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
 316
 317 # ddram:0.ba
 318 set_property LOC P4 [get_ports {ddram_ba[1]}]
 319 set_property SLEW FAST [get_ports {ddram_ba[1]}]
 320 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
 321
 322 # ddram:0.ba
 323 set_property LOC P2 [get_ports {ddram_ba[2]}]
 324 set_property SLEW FAST [get_ports {ddram_ba[2]}]
 325 set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
 326
 327 # ddram:0.ras_n
 328 set_property LOC P3 [get_ports {ddram_ras_n}]
 329 set_property SLEW FAST [get_ports {ddram_ras_n}]
 330 set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
 331
 332 # ddram:0.cas_n
 333 set_property LOC M4 [get_ports {ddram_cas_n}]
 334 set_property SLEW FAST [get_ports {ddram_cas_n}]
 335 set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
 336
 337 # ddram:0.we_n
 338 set_property LOC P5 [get_ports {ddram_we_n}]
 339 set_property SLEW FAST [get_ports {ddram_we_n}]
 340 set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
 341
 342 # ddram:0.cs_n
 343 set_property LOC U8 [get_ports {ddram_cs_n}]
 344 set_property SLEW FAST [get_ports {ddram_cs_n}]
 345 set_property IOSTANDARD SSTL135 [get_ports {ddram_cs_n}]
 346
 347 # ddram:0.dm
 348 set_property LOC L1 [get_ports {ddram_dm[0]}]
 349 set_property SLEW FAST [get_ports {ddram_dm[0]}]
 350 set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
 351
 352 # ddram:0.dm
 353 set_property LOC U1 [get_ports {ddram_dm[1]}]
 354 set_property SLEW FAST [get_ports {ddram_dm[1]}]
 355 set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
 356
 357 # ddram:0.dq
 358 set_property LOC K5 [get_ports {ddram_dq[0]}]
 359 set_property SLEW FAST [get_ports {ddram_dq[0]}]
 360 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
 361 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
 362
 363 # ddram:0.dq
 364 set_property LOC L3 [get_ports {ddram_dq[1]}]
 365 set_property SLEW FAST [get_ports {ddram_dq[1]}]
 366 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
 367 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
 368
 369 # ddram:0.dq
 370 set_property LOC K3 [get_ports {ddram_dq[2]}]
 371 set_property SLEW FAST [get_ports {ddram_dq[2]}]
 372 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
 373 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
 374
 375 # ddram:0.dq
 376 set_property LOC L6 [get_ports {ddram_dq[3]}]
 377 set_property SLEW FAST [get_ports {ddram_dq[3]}]
 378 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
 379 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
 380
 381 # ddram:0.dq
 382 set_property LOC M3 [get_ports {ddram_dq[4]}]
 383 set_property SLEW FAST [get_ports {ddram_dq[4]}]
 384 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
 385 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
 386
 387 # ddram:0.dq
 388 set_property LOC M1 [get_ports {ddram_dq[5]}]
 389 set_property SLEW FAST [get_ports {ddram_dq[5]}]
 390 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
 391 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
 392
 393 # ddram:0.dq
 394 set_property LOC L4 [get_ports {ddram_dq[6]}]
 395 set_property SLEW FAST [get_ports {ddram_dq[6]}]
 396 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
 397 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
 398
 399 # ddram:0.dq
 400 set_property LOC M2 [get_ports {ddram_dq[7]}]
 401 set_property SLEW FAST [get_ports {ddram_dq[7]}]
 402 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
 403 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
 404
 405 # ddram:0.dq
 406 set_property LOC V4 [get_ports {ddram_dq[8]}]
 407 set_property SLEW FAST [get_ports {ddram_dq[8]}]
 408 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
 409 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
 410
 411 # ddram:0.dq
 412 set_property LOC T5 [get_ports {ddram_dq[9]}]
 413 set_property SLEW FAST [get_ports {ddram_dq[9]}]
 414 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
 415 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
 416
 417 # ddram:0.dq
 418 set_property LOC U4 [get_ports {ddram_dq[10]}]
 419 set_property SLEW FAST [get_ports {ddram_dq[10]}]
 420 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
 421 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
 422
 423 # ddram:0.dq
 424 set_property LOC V5 [get_ports {ddram_dq[11]}]
 425 set_property SLEW FAST [get_ports {ddram_dq[11]}]
 426 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
 427 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
 428
 429 # ddram:0.dq
 430 set_property LOC V1 [get_ports {ddram_dq[12]}]
 431 set_property SLEW FAST [get_ports {ddram_dq[12]}]
 432 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
 433 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
 434
 435 # ddram:0.dq
 436 set_property LOC T3 [get_ports {ddram_dq[13]}]
 437 set_property SLEW FAST [get_ports {ddram_dq[13]}]
 438 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
 439 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
 440
 441 # ddram:0.dq
 442 set_property LOC U3 [get_ports {ddram_dq[14]}]
 443 set_property SLEW FAST [get_ports {ddram_dq[14]}]
 444 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
 445 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
 446
 447 # ddram:0.dq
 448 set_property LOC R3 [get_ports {ddram_dq[15]}]
 449 set_property SLEW FAST [get_ports {ddram_dq[15]}]
 450 set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
 451 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
 452
 453 # ddram:0.dqs_p
 454 set_property LOC N2 [get_ports {ddram_dqs_p[0]}]
 455 set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
 456 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
 457 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
 458
 459 # ddram:0.dqs_p
 460 set_property LOC U2 [get_ports {ddram_dqs_p[1]}]
 461 set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
 462 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
 463 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
 464
 465 # ddram:0.dqs_n
 466 set_property LOC N1 [get_ports {ddram_dqs_n[0]}]
 467 set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
 468 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
 469 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
 470
 471 # ddram:0.dqs_n
 472 set_property LOC V2 [get_ports {ddram_dqs_n[1]}]
 473 set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
 474 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
 475 set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
 476
 477 # ddram:0.clk_p
 478 set_property LOC U9 [get_ports {ddram_clk_p}]
 479 set_property SLEW FAST [get_ports {ddram_clk_p}]
 480 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
 481
 482 # ddram:0.clk_n
 483 set_property LOC V9 [get_ports {ddram_clk_n}]
 484 set_property SLEW FAST [get_ports {ddram_clk_n}]
 485 set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
 486
 487 # ddram:0.cke
 488 set_property LOC N5 [get_ports {ddram_cke}]
 489 set_property SLEW FAST [get_ports {ddram_cke}]
 490 set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
 491
 492 # ddram:0.odt
 493 set_property LOC R5 [get_ports {ddram_odt}]
 494 set_property SLEW FAST [get_ports {ddram_odt}]
 495 set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
 496
 497 # ddram:0.reset_n
 498 set_property LOC K6 [get_ports {ddram_reset_n}]
 499 set_property SLEW FAST [get_ports {ddram_reset_n}]
 500 set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
 501
 502 ################################################################################
 503 # Design constraints and bitsteam attributes
 504 ################################################################################
 505
 506 #Internal VREF
 507 set_property INTERNAL_VREF 0.675 [get_iobanks 34]
 508
 509 set_property CONFIG_VOLTAGE 3.3 [current_design]
 510 set_property CFGBVS VCCO [current_design]
 511
 512 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 513 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
 514 set_property CONFIG_MODE SPIx4 [current_design]
 515
 516 ################################################################################
 517 # Clock constraints
 518 ################################################################################
 519
 520 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { ext_clk }];
 521
 522 create_clock -name eth_rx_clk -period 40.0 [get_ports { eth_clocks_rx }]
 523
 524 create_clock -name eth_tx_clk -period 40.0 [get_ports { eth_clocks_tx }]
 525
 526 set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -asynchronous
 527
 528 set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets system_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous
 529
 530 set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_rx]] -group [get_clocks -include_generated_clocks -of [get_nets eth_clocks_tx]] -asynchronous
 531
 532 ################################################################################
 533 # False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
 534 ################################################################################
 535
 536 set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
 537
 538 set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
 539
 540 set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]