2 use ieee.std_logic_1164.all;
5 use UNISIM.vcomponents.all;
7 entity clock_generator is
9 CLK_INPUT_HZ : positive := 12000000;
10 CLK_OUTPUT_HZ : positive := 50000000
13 ext_clk : in std_logic;
14 pll_rst_in : in std_logic;
15 pll_clk_out : out std_logic;
16 pll_locked_out : out std_logic);
17 end entity clock_generator;
19 architecture rtl of clock_generator is
20 signal clkfb : std_ulogic;
22 type pll_settings_t is record
23 clkin_period : real range 10.000 to 800.0;
24 clkfbout_mult : real range 2.0 to 64.0;
25 clkout_divide : real range 1.0 to 128.0;
26 divclk_divide : integer range 1 to 106;
27 force_rst : std_ulogic;
30 function gen_pll_settings (
31 constant input_hz : positive;
32 constant output_hz : positive)
33 return pll_settings_t is
35 constant bad_settings : pll_settings_t :=
46 return (clkin_period => 10.0,
47 clkfbout_mult => 16.0,
48 clkout_divide => 16.0,
52 return (clkin_period => 10.0,
53 clkfbout_mult => 16.0,
54 clkout_divide => 32.0,
58 report "Unsupported output frequency" severity failure;
64 return (clkin_period => 83.33,
65 clkfbout_mult => 50.0,
70 return (clkin_period => 83.33,
71 clkfbout_mult => 50.0,
72 clkout_divide => 12.0,
76 report "Unsupported output frequency" severity failure;
80 report "Unsupported input frequency" severity failure;
83 end function gen_pll_settings;
85 constant pll_settings : pll_settings_t := gen_pll_settings(clk_input_hz,
90 BANDWIDTH => "OPTIMIZED",
91 CLKFBOUT_MULT_F => pll_settings.clkfbout_mult,
92 CLKIN1_PERIOD => pll_settings.clkin_period,
93 CLKOUT0_DIVIDE_F => pll_settings.clkout_divide,
94 DIVCLK_DIVIDE => pll_settings.divclk_divide,
95 STARTUP_WAIT => FALSE)
99 CLKOUT0 => pll_clk_out,
110 LOCKED => pll_locked_out,
114 RST => pll_rst_in or pll_settings.force_rst
116 end architecture rtl;