fpga/clk_gen_plle2.vhd

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 Library UNISIM;
   5 use UNISIM.vcomponents.all;
   6
   7 entity clock_generator is
   8   generic (
   9     clk_period_hz : positive := 100000000);
  10   port (
  11     ext_clk        : in  std_logic;
  12     pll_rst_in   : in  std_logic;
  13     pll_clk_out    : out std_logic;
  14     pll_locked_out : out std_logic);
  15 end entity clock_generator;
  16
  17 architecture rtl of clock_generator is
  18
  19   signal clkfb : std_ulogic;
  20
  21   type pll_settings_t is record
  22     clkin_period  : real    range 0.000 to 52.631;
  23     clkfbout_mult : integer range 2 to 64;
  24     clkout_divide : integer range 1 to 128;
  25     divclk_divide : integer range 1 to 56;
  26   end record;
  27
  28   function gen_pll_settings (
  29     constant freq_hz : positive)
  30     return pll_settings_t is
  31   begin
  32     if freq_hz = 100000000 then
  33       return (clkin_period  => 10.0,
  34               clkfbout_mult => 16,
  35               clkout_divide => 32,
  36               divclk_divide => 1);
  37     else
  38       report "Unsupported input frequency" severity failure;
  39 --      return (clkin_period  => 0.0,
  40 --              clkfbout_mult => 0,
  41 --              clkout_divide => 0,
  42 --              divclk_divide => 0);
  43     end if;
  44   end function gen_pll_settings;
  45
  46   constant pll_settings : pll_settings_t := gen_pll_settings(clk_period_hz);
  47 begin
  48
  49   pll : PLLE2_BASE
  50     generic map (
  51       BANDWIDTH          => "OPTIMIZED",
  52       CLKFBOUT_MULT      => pll_settings.clkfbout_mult,
  53       CLKIN1_PERIOD      => pll_settings.clkin_period,
  54       CLKOUT0_DIVIDE     => pll_settings.clkout_divide,
  55       DIVCLK_DIVIDE      => pll_settings.divclk_divide,
  56       STARTUP_WAIT       => "FALSE")
  57     port map (
  58       CLKOUT0  => pll_clk_out,
  59       CLKOUT1  => open,
  60       CLKOUT2  => open,
  61       CLKOUT3  => open,
  62       CLKOUT4  => open,
  63       CLKOUT5  => open,
  64       CLKFBOUT => clkfb,
  65       LOCKED   => pll_locked_out,
  66       CLKIN1   => ext_clk,
  67       PWRDWN   => '0',
  68       RST      => pll_rst_in,
  69       CLKFBIN  => clkfb);
  70
  71 end architecture rtl;