fpga/nexys-video.xdc

   1 set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports ext_clk]
   2 create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk]
   3
   4 set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS15} [get_ports ext_rst]
   5
   6 set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports uart_main_tx]
   7 set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports uart_main_rx]
   8
   9 ##Pmod Header JA: UART (bottom)
  10
  11 set_property -dict { PACKAGE_PIN Y21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_cts_n }];
  12 set_property -dict { PACKAGE_PIN AA21 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_tx }];
  13 set_property -dict { PACKAGE_PIN AA20 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rx }];
  14 set_property -dict { PACKAGE_PIN AA18 IOSTANDARD LVCMOS33 } [get_ports { uart_pmod_rts_n }];
  15
  16 # LEDs (no colors, just normal LEDs here)
  17 set_property -dict { PACKAGE_PIN T14  IOSTANDARD LVCMOS33 } [get_ports { led0 }];
  18 set_property -dict { PACKAGE_PIN T15  IOSTANDARD LVCMOS33 } [get_ports { led1 }];
  19
  20 # DRAM (generated by LiteX)
  21  ## ddram:0.a
  22 set_property LOC M2 [get_ports ddram_a[0]]
  23 set_property SLEW FAST [get_ports ddram_a[0]]
  24 set_property IOSTANDARD SSTL15 [get_ports ddram_a[0]]
  25  ## ddram:0.a
  26 set_property LOC M5 [get_ports ddram_a[1]]
  27 set_property SLEW FAST [get_ports ddram_a[1]]
  28 set_property IOSTANDARD SSTL15 [get_ports ddram_a[1]]
  29  ## ddram:0.a
  30 set_property LOC M3 [get_ports ddram_a[2]]
  31 set_property SLEW FAST [get_ports ddram_a[2]]
  32 set_property IOSTANDARD SSTL15 [get_ports ddram_a[2]]
  33  ## ddram:0.a
  34 set_property LOC M1 [get_ports ddram_a[3]]
  35 set_property SLEW FAST [get_ports ddram_a[3]]
  36 set_property IOSTANDARD SSTL15 [get_ports ddram_a[3]]
  37  ## ddram:0.a
  38 set_property LOC L6 [get_ports ddram_a[4]]
  39 set_property SLEW FAST [get_ports ddram_a[4]]
  40 set_property IOSTANDARD SSTL15 [get_ports ddram_a[4]]
  41  ## ddram:0.a
  42 set_property LOC P1 [get_ports ddram_a[5]]
  43 set_property SLEW FAST [get_ports ddram_a[5]]
  44 set_property IOSTANDARD SSTL15 [get_ports ddram_a[5]]
  45  ## ddram:0.a
  46 set_property LOC N3 [get_ports ddram_a[6]]
  47 set_property SLEW FAST [get_ports ddram_a[6]]
  48 set_property IOSTANDARD SSTL15 [get_ports ddram_a[6]]
  49  ## ddram:0.a
  50 set_property LOC N2 [get_ports ddram_a[7]]
  51 set_property SLEW FAST [get_ports ddram_a[7]]
  52 set_property IOSTANDARD SSTL15 [get_ports ddram_a[7]]
  53  ## ddram:0.a
  54 set_property LOC M6 [get_ports ddram_a[8]]
  55 set_property SLEW FAST [get_ports ddram_a[8]]
  56 set_property IOSTANDARD SSTL15 [get_ports ddram_a[8]]
  57  ## ddram:0.a
  58 set_property LOC R1 [get_ports ddram_a[9]]
  59 set_property SLEW FAST [get_ports ddram_a[9]]
  60 set_property IOSTANDARD SSTL15 [get_ports ddram_a[9]]
  61  ## ddram:0.a
  62 set_property LOC L5 [get_ports ddram_a[10]]
  63 set_property SLEW FAST [get_ports ddram_a[10]]
  64 set_property IOSTANDARD SSTL15 [get_ports ddram_a[10]]
  65  ## ddram:0.a
  66 set_property LOC N5 [get_ports ddram_a[11]]
  67 set_property SLEW FAST [get_ports ddram_a[11]]
  68 set_property IOSTANDARD SSTL15 [get_ports ddram_a[11]]
  69  ## ddram:0.a
  70 set_property LOC N4 [get_ports ddram_a[12]]
  71 set_property SLEW FAST [get_ports ddram_a[12]]
  72 set_property IOSTANDARD SSTL15 [get_ports ddram_a[12]]
  73  ## ddram:0.a
  74 set_property LOC P2 [get_ports ddram_a[13]]
  75 set_property SLEW FAST [get_ports ddram_a[13]]
  76 set_property IOSTANDARD SSTL15 [get_ports ddram_a[13]]
  77  ## ddram:0.a
  78 set_property LOC P6 [get_ports ddram_a[14]]
  79 set_property SLEW FAST [get_ports ddram_a[14]]
  80 set_property IOSTANDARD SSTL15 [get_ports ddram_a[14]]
  81  ## ddram:0.ba
  82 set_property LOC L3 [get_ports ddram_ba[0]]
  83 set_property SLEW FAST [get_ports ddram_ba[0]]
  84 set_property IOSTANDARD SSTL15 [get_ports ddram_ba[0]]
  85  ## ddram:0.ba
  86 set_property LOC K6 [get_ports ddram_ba[1]]
  87 set_property SLEW FAST [get_ports ddram_ba[1]]
  88 set_property IOSTANDARD SSTL15 [get_ports ddram_ba[1]]
  89  ## ddram:0.ba
  90 set_property LOC L4 [get_ports ddram_ba[2]]
  91 set_property SLEW FAST [get_ports ddram_ba[2]]
  92 set_property IOSTANDARD SSTL15 [get_ports ddram_ba[2]]
  93  ## ddram:0.ras_n
  94 set_property LOC J4 [get_ports ddram_ras_n]
  95 set_property SLEW FAST [get_ports ddram_ras_n]
  96 set_property IOSTANDARD SSTL15 [get_ports ddram_ras_n]
  97  ## ddram:0.cas_n
  98 set_property LOC K3 [get_ports ddram_cas_n]
  99 set_property SLEW FAST [get_ports ddram_cas_n]
 100 set_property IOSTANDARD SSTL15 [get_ports ddram_cas_n]
 101  ## ddram:0.we_n
 102 set_property LOC L1 [get_ports ddram_we_n]
 103 set_property SLEW FAST [get_ports ddram_we_n]
 104 set_property IOSTANDARD SSTL15 [get_ports ddram_we_n]
 105  ## ddram:0.dm
 106 set_property LOC G3 [get_ports ddram_dm[0]]
 107 set_property SLEW FAST [get_ports ddram_dm[0]]
 108 set_property IOSTANDARD SSTL15 [get_ports ddram_dm[0]]
 109  ## ddram:0.dm
 110 set_property LOC F1 [get_ports ddram_dm[1]]
 111 set_property SLEW FAST [get_ports ddram_dm[1]]
 112 set_property IOSTANDARD SSTL15 [get_ports ddram_dm[1]]
 113  ## ddram:0.dq
 114 set_property LOC G2 [get_ports ddram_dq[0]]
 115 set_property SLEW FAST [get_ports ddram_dq[0]]
 116 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[0]]
 117 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[0]]
 118  ## ddram:0.dq
 119 set_property LOC H4 [get_ports ddram_dq[1]]
 120 set_property SLEW FAST [get_ports ddram_dq[1]]
 121 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[1]]
 122 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[1]]
 123  ## ddram:0.dq
 124 set_property LOC H5 [get_ports ddram_dq[2]]
 125 set_property SLEW FAST [get_ports ddram_dq[2]]
 126 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[2]]
 127 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[2]]
 128  ## ddram:0.dq
 129 set_property LOC J1 [get_ports ddram_dq[3]]
 130 set_property SLEW FAST [get_ports ddram_dq[3]]
 131 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[3]]
 132 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[3]]
 133  ## ddram:0.dq
 134 set_property LOC K1 [get_ports ddram_dq[4]]
 135 set_property SLEW FAST [get_ports ddram_dq[4]]
 136 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[4]]
 137 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[4]]
 138  ## ddram:0.dq
 139 set_property LOC H3 [get_ports ddram_dq[5]]
 140 set_property SLEW FAST [get_ports ddram_dq[5]]
 141 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[5]]
 142 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[5]]
 143  ## ddram:0.dq
 144 set_property LOC H2 [get_ports ddram_dq[6]]
 145 set_property SLEW FAST [get_ports ddram_dq[6]]
 146 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[6]]
 147 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[6]]
 148  ## ddram:0.dq
 149 set_property LOC J5 [get_ports ddram_dq[7]]
 150 set_property SLEW FAST [get_ports ddram_dq[7]]
 151 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[7]]
 152 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[7]]
 153  ## ddram:0.dq
 154 set_property LOC E3 [get_ports ddram_dq[8]]
 155 set_property SLEW FAST [get_ports ddram_dq[8]]
 156 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[8]]
 157 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[8]]
 158  ## ddram:0.dq
 159 set_property LOC B2 [get_ports ddram_dq[9]]
 160 set_property SLEW FAST [get_ports ddram_dq[9]]
 161 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[9]]
 162 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[9]]
 163  ## ddram:0.dq
 164 set_property LOC F3 [get_ports ddram_dq[10]]
 165 set_property SLEW FAST [get_ports ddram_dq[10]]
 166 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[10]]
 167 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[10]]
 168  ## ddram:0.dq
 169 set_property LOC D2 [get_ports ddram_dq[11]]
 170 set_property SLEW FAST [get_ports ddram_dq[11]]
 171 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[11]]
 172 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[11]]
 173  ## ddram:0.dq
 174 set_property LOC C2 [get_ports ddram_dq[12]]
 175 set_property SLEW FAST [get_ports ddram_dq[12]]
 176 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[12]]
 177 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[12]]
 178  ## ddram:0.dq
 179 set_property LOC A1 [get_ports ddram_dq[13]]
 180 set_property SLEW FAST [get_ports ddram_dq[13]]
 181 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[13]]
 182 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[13]]
 183  ## ddram:0.dq
 184 set_property LOC E2 [get_ports ddram_dq[14]]
 185 set_property SLEW FAST [get_ports ddram_dq[14]]
 186 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[14]]
 187 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[14]]
 188  ## ddram:0.dq
 189 set_property LOC B1 [get_ports ddram_dq[15]]
 190 set_property SLEW FAST [get_ports ddram_dq[15]]
 191 set_property IOSTANDARD SSTL15 [get_ports ddram_dq[15]]
 192 set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddram_dq[15]]
 193  ## ddram:0.dqs_p
 194 set_property LOC K2 [get_ports ddram_dqs_p[0]]
 195 set_property SLEW FAST [get_ports ddram_dqs_p[0]]
 196 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[0]]
 197  ## ddram:0.dqs_p
 198 set_property LOC E1 [get_ports ddram_dqs_p[1]]
 199 set_property SLEW FAST [get_ports ddram_dqs_p[1]]
 200 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_p[1]]
 201  ## ddram:0.dqs_n
 202 set_property LOC J2 [get_ports ddram_dqs_n[0]]
 203 set_property SLEW FAST [get_ports ddram_dqs_n[0]]
 204 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[0]]
 205  ## ddram:0.dqs_n
 206 set_property LOC D1 [get_ports ddram_dqs_n[1]]
 207 set_property SLEW FAST [get_ports ddram_dqs_n[1]]
 208 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_dqs_n[1]]
 209  ## ddram:0.clk_p
 210 set_property LOC P5 [get_ports ddram_clk_p]
 211 set_property SLEW FAST [get_ports ddram_clk_p]
 212 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_p]
 213  ## ddram:0.clk_n
 214 set_property LOC P4 [get_ports ddram_clk_n]
 215 set_property SLEW FAST [get_ports ddram_clk_n]
 216 set_property IOSTANDARD DIFF_SSTL15 [get_ports ddram_clk_n]
 217  ## ddram:0.cke
 218 set_property LOC J6 [get_ports ddram_cke]
 219 set_property SLEW FAST [get_ports ddram_cke]
 220 set_property IOSTANDARD SSTL15 [get_ports ddram_cke]
 221  ## ddram:0.odt
 222 set_property LOC K4 [get_ports ddram_odt]
 223 set_property SLEW FAST [get_ports ddram_odt]
 224 set_property IOSTANDARD SSTL15 [get_ports ddram_odt]
 225  ## ddram:0.reset_n
 226 set_property LOC G1 [get_ports ddram_reset_n]
 227 set_property SLEW FAST [get_ports ddram_reset_n]
 228 set_property IOSTANDARD SSTL15 [get_ports ddram_reset_n]
 229
 230 #Internal VREF
 231 set_property INTERNAL_VREF 0.750 [get_iobanks 35]
 232
 233 set_property CONFIG_VOLTAGE 3.3 [current_design]
 234 set_property CFGBVS VCCO [current_design]
 235
 236 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 237 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
 238 set_property CONFIG_MODE SPIx4 [current_design]