fpga/nexys_a7.xdc

   1 set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports ext_clk]
   2 create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports ext_clk]
   3
   4 set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports ext_rst]
   5
   6 set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS33} [get_ports uart0_txd]
   7 set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS33} [get_ports uart0_rxd]
   8
   9 set_property CONFIG_VOLTAGE 3.3 [current_design]
  10 set_property CFGBVS VCCO [current_design]
  11
  12 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
  13 set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
  14 set_property CONFIG_MODE SPIx4 [current_design]