1 -- The Potato Processor - A simple processor for FPGAs
2 -- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
5 use ieee.std_logic_1164.all;
7 --! @brief A generic FIFO module.
8 --! Adopted from the FIFO module in <https://github.com/skordal/smallthings>.
11 DEPTH : natural := 64;
21 empty : out std_logic;
24 data_in : in std_logic_vector(WIDTH - 1 downto 0);
25 data_out : out std_logic_vector(WIDTH - 1 downto 0);
26 push, pop : in std_logic
30 architecture behaviour of pp_fifo is
32 type memory_array is array(0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
33 signal memory : memory_array := (others => (others => '0'));
35 subtype index_type is integer range 0 to DEPTH - 1;
36 signal top, bottom : index_type;
38 type fifo_op is (FIFO_POP, FIFO_PUSH);
39 signal prev_op : fifo_op := FIFO_POP;
43 empty <= '1' when top = bottom and prev_op = FIFO_POP else '0';
44 full <= '1' when top = bottom and prev_op = FIFO_PUSH else '0';
48 if rising_edge(clk) then
53 data_out <= memory(bottom);
54 bottom <= (bottom + 1) mod DEPTH;
62 if rising_edge(clk) then
67 memory(top) <= data_in;
68 top <= (top + 1) mod DEPTH;
74 set_prev_op: process(clk)
76 if rising_edge(clk) then
80 if push = '1' and pop = '1' then
81 -- Keep the same value for prev_op
89 end process set_prev_op;
91 end architecture behaviour;