fpga/pp_soc_memory.vhd

   1 -- The Potato Processor - A simple processor for FPGAs
   2 -- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7 use std.textio.all;
   8
   9 use work.pp_utilities.all;
  10
  11 --! @brief Simple memory module for use in Wishbone-based systems.
  12 entity pp_soc_memory is
  13         generic(
  14                 MEMORY_SIZE   : natural := 4096; --! Memory size in bytes.
  15                 RAM_INIT_FILE : string
  16         );
  17         port(
  18                 clk : in std_logic;
  19                 reset : in std_logic;
  20
  21                 -- Wishbone interface:
  22                 wb_adr_in  : in  std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
  23                 wb_dat_in  : in  std_logic_vector(63 downto 0);
  24                 wb_dat_out : out std_logic_vector(63 downto 0);
  25                 wb_cyc_in  : in  std_logic;
  26                 wb_stb_in  : in  std_logic;
  27                 wb_sel_in  : in  std_logic_vector( 7 downto 0);
  28                 wb_we_in   : in  std_logic;
  29                 wb_ack_out : out std_logic
  30         );
  31 end entity pp_soc_memory;
  32
  33 architecture behaviour of pp_soc_memory is
  34         type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
  35
  36     impure function init_ram(name : STRING) return ram_t is
  37         file ram_file : text open read_mode is name;
  38         variable ram_line : line;
  39         variable temp_word : std_logic_vector(63 downto 0);
  40         variable temp_ram : ram_t := (others => (others => '0'));
  41     begin
  42         for i in 0 to (MEMORY_SIZE/8)-1 loop
  43             exit when endfile(ram_file);
  44             readline(ram_file, ram_line);
  45             hread(ram_line, temp_word);
  46             temp_ram(i) := temp_word;
  47         end loop;
  48
  49         return temp_ram;
  50     end function;
  51
  52     signal memory : ram_t := init_ram(RAM_INIT_FILE);
  53
  54         attribute ram_style : string;
  55         attribute ram_style of memory : signal is "block";
  56
  57         attribute ram_decomp : string;
  58         attribute ram_decomp of memory : signal is "power";
  59
  60         type state_type is (IDLE, ACK);
  61         signal state : state_type;
  62
  63         signal read_ack : std_logic;
  64
  65 begin
  66
  67         wb_ack_out <= read_ack and wb_stb_in;
  68
  69         process(clk)
  70         begin
  71                 if rising_edge(clk) then
  72                         if reset = '1' then
  73                                 read_ack <= '0';
  74                                 state <= IDLE;
  75                         else
  76                                 if wb_cyc_in = '1' then
  77                                         case state is
  78                                                 when IDLE =>
  79                                                         if wb_stb_in = '1' and wb_we_in = '1' then
  80                                                                  for i in 0 to 7 loop
  81                                                                         if wb_sel_in(i) = '1' then
  82                                                                                 memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))))(((i + 1) * 8) - 1 downto i * 8)
  83                                                                                         <= wb_dat_in(((i + 1) * 8) - 1 downto i * 8);
  84                                                                         end if;
  85                                                                  end loop;
  86                                                                  read_ack <= '1';
  87                                                                  state <= ACK;
  88                                                         elsif wb_stb_in = '1' then
  89                                                                 wb_dat_out <= memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))));
  90                                                                 read_ack <= '1';
  91                                                                 state <= ACK;
  92                                                         end if;
  93                                                 when ACK =>
  94                                                         if wb_stb_in = '0' then
  95                                                                 read_ack <= '0';
  96                                                                 state <= IDLE;
  97                                                         end if;
  98                                         end case;
  99                                 else
 100                                         state <= IDLE;
 101                                         read_ack <= '0';
 102                                 end if;
 103                         end if;
 104                 end if;
 105         end process clk;
 106
 107 end architecture behaviour;