fpga/pp_soc_memory.vhd

   1 -- The Potato Processor - A simple processor for FPGAs
   2 -- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7 use std.textio.all;
   8
   9 use work.pp_utilities.all;
  10
  11 --! @brief Simple memory module for use in Wishbone-based systems.
  12 entity pp_soc_memory is
  13         generic(
  14                 MEMORY_SIZE : natural := 4096 --! Memory size in bytes.
  15         );
  16         port(
  17                 clk : in std_logic;
  18                 reset : in std_logic;
  19
  20                 -- Wishbone interface:
  21                 wb_adr_in  : in  std_logic_vector(log2(MEMORY_SIZE) - 1 downto 0);
  22                 wb_dat_in  : in  std_logic_vector(63 downto 0);
  23                 wb_dat_out : out std_logic_vector(63 downto 0);
  24                 wb_cyc_in  : in  std_logic;
  25                 wb_stb_in  : in  std_logic;
  26                 wb_sel_in  : in  std_logic_vector( 7 downto 0);
  27                 wb_we_in   : in  std_logic;
  28                 wb_ack_out : out std_logic
  29         );
  30 end entity pp_soc_memory;
  31
  32 architecture behaviour of pp_soc_memory is
  33         type ram_t is array(0 to (MEMORY_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
  34
  35     impure function init_ram(name : STRING) return ram_t is
  36         file ram_file : text open read_mode is name;
  37         variable ram_line : line;
  38         variable temp_word : std_logic_vector(63 downto 0);
  39         variable temp_ram : ram_t := (others => (others => '0'));
  40     begin
  41         for i in 0 to (MEMORY_SIZE/8)-1 loop
  42             exit when endfile(ram_file);
  43             readline(ram_file, ram_line);
  44             hread(ram_line, temp_word);
  45             temp_ram(i) := temp_word;
  46         end loop;
  47
  48         return temp_ram;
  49     end function;
  50
  51     signal memory : ram_t := init_ram("firmware.hex");
  52
  53         attribute ram_style : string;
  54         attribute ram_style of memory : signal is "block";
  55
  56         attribute ram_decomp : string;
  57         attribute ram_decomp of memory : signal is "power";
  58
  59         type state_type is (IDLE, ACK);
  60         signal state : state_type;
  61
  62         signal read_ack : std_logic;
  63
  64 begin
  65
  66         wb_ack_out <= read_ack and wb_stb_in;
  67
  68         process(clk)
  69         begin
  70                 if rising_edge(clk) then
  71                         if reset = '1' then
  72                                 read_ack <= '0';
  73                                 state <= IDLE;
  74                         else
  75                                 if wb_cyc_in = '1' then
  76                                         case state is
  77                                                 when IDLE =>
  78                                                         if wb_stb_in = '1' and wb_we_in = '1' then
  79                                                                  for i in 0 to 7 loop
  80                                                                         if wb_sel_in(i) = '1' then
  81                                                                                 memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))))(((i + 1) * 8) - 1 downto i * 8)
  82                                                                                         <= wb_dat_in(((i + 1) * 8) - 1 downto i * 8);
  83                                                                         end if;
  84                                                                  end loop;
  85                                                                  read_ack <= '1';
  86                                                                  state <= ACK;
  87                                                         elsif wb_stb_in = '1' then
  88                                                                 wb_dat_out <= memory(to_integer(unsigned(wb_adr_in(wb_adr_in'left downto 3))));
  89                                                                 read_ack <= '1';
  90                                                                 state <= ACK;
  91                                                         end if;
  92                                                 when ACK =>
  93                                                         if wb_stb_in = '0' then
  94                                                                 read_ack <= '0';
  95                                                                 state <= IDLE;
  96                                                         end if;
  97                                         end case;
  98                                 else
  99                                         state <= IDLE;
 100                                         read_ack <= '0';
 101                                 end if;
 102                         end if;
 103                 end if;
 104         end process clk;
 105
 106 end architecture behaviour;