fpga/pp_soc_reset.vhd

   1 -- The Potato Processor - A simple processor for FPGAs
   2 -- (c) Kristian Klomsten Skordal 2018 <kristian.skordal@wafflemail.net>
   3
   4 library ieee;
   5 use ieee.std_logic_1164.all;
   6 use work.pp_utilities.all;
   7
   8 --! @brief System reset unit.
   9 --! Because most resets in the processor core are synchronous, at least one
  10 --! clock pulse has to be given to the processor while the reset signal is
  11 --! asserted. However, if the clock generator is being reset at the same time,
  12 --! the system clock might not run during reset, preventing the processor from
  13 --! properly resetting.
  14 entity pp_soc_reset is
  15         generic(
  16                 RESET_CYCLE_COUNT : natural := 20000000
  17         );
  18         port(
  19                 clk : in std_logic;
  20
  21                 reset_n   : in  std_logic;
  22                 reset_out : out std_logic;
  23
  24                 system_clk        : in std_logic;
  25                 system_clk_locked : in std_logic
  26         );
  27 end entity pp_soc_reset;
  28
  29 architecture behaviour of pp_soc_reset is
  30
  31         subtype counter_type is natural range 0 to RESET_CYCLE_COUNT;
  32         signal counter : counter_type;
  33
  34         signal fast_reset : std_logic := '0';
  35         signal slow_reset : std_logic := '1';
  36 begin
  37
  38         reset_out <= slow_reset;
  39
  40 --      process(clk)
  41 --      begin
  42 --              if rising_edge(clk) then
  43 --                      if reset_n = '0' then
  44 --                              fast_reset <= '1';
  45 --                      elsif system_clk_locked = '1' then
  46 --                              if fast_reset = '1' and slow_reset = '1' then
  47 --                                      fast_reset <= '0';
  48 --                              end if;
  49 --                      end if;
  50 --              end if;
  51 --      end process;
  52
  53         process(system_clk)
  54         begin
  55                 if rising_edge(system_clk) then
  56                         if reset_n = '0' then
  57                                 slow_reset <= '1';
  58                                 counter <= RESET_CYCLE_COUNT;
  59                         else
  60                                 if counter = 0 then
  61                                         slow_reset <= '0';
  62                                 else
  63                                         counter <= counter - 1;
  64                                 end if;
  65                         end if;
  66                 end if;
  67         end process;
  68
  69 end architecture behaviour;