fpga/soc_reset_tb.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity soc_reset_tb is
   5 end soc_reset_tb;
   6
   7 architecture behave of soc_reset_tb is
   8     signal ext_clk       : std_ulogic;
   9     signal pll_clk       : std_ulogic;
  10
  11     signal pll_locked_in : std_ulogic;
  12     signal ext_rst_in    : std_ulogic;
  13
  14     signal pll_rst_out          : std_ulogic;
  15     signal rst_out                : std_ulogic;
  16
  17     constant clk_period : time := 10 ns;
  18
  19     type test_vector is record
  20         pll_locked_in : std_ulogic;
  21         ext_rst_in    : std_ulogic;
  22         pll_rst_out   : std_ulogic;
  23         rst_out       : std_ulogic;
  24     end record;
  25
  26     type test_vector_array is array (natural range <>) of test_vector;
  27     constant test_vectors : test_vector_array := (
  28         -- PLL not locked, reset button not pressed
  29         ('0', '1', '1', '1'),
  30         ('0', '1', '1', '1'),
  31         ('0', '1', '1', '1'),
  32         ('0', '1', '1', '1'),
  33         ('0', '1', '1', '1'),
  34         ('0', '1', '1', '1'),
  35         -- Reset is removed from the PLL
  36         ('0', '1', '0', '1'),
  37         ('0', '1', '0', '1'),
  38         ('0', '1', '0', '1'),
  39         -- At some point PLL comes out of reset
  40         ('1', '1', '0', '1'),
  41         ('1', '1', '0', '1'),
  42         ('1', '1', '0', '1'),
  43         ('1', '1', '0', '1'),
  44         ('1', '1', '0', '1'),
  45         ('1', '1', '0', '1'),
  46         -- Finally SOC comes out of reset
  47         ('1', '1', '0', '0'),
  48         ('1', '1', '0', '0'),
  49
  50         -- PLL locked, reset button pressed
  51         ('1', '0', '0', '0'),
  52         ('1', '0', '0', '0'),
  53         ('1', '0', '0', '0'),
  54         ('1', '0', '1', '1'),
  55         -- PLL locked, reset button released
  56         ('1', '1', '1', '1'),
  57         ('1', '1', '1', '1'),
  58         ('1', '1', '1', '1'),
  59         ('1', '1', '1', '1'),
  60         ('1', '1', '1', '1'),
  61         ('1', '1', '1', '1'),
  62         ('1', '1', '0', '1'),
  63         ('1', '1', '0', '1'),
  64         ('1', '1', '0', '1'),
  65         ('1', '1', '0', '1'),
  66         ('1', '1', '0', '1'),
  67         ('1', '1', '0', '1'),
  68         -- Finally SOC comes out of reset
  69         ('1', '1', '0', '0')
  70         );
  71 begin
  72     soc_reset_0: entity work.soc_reset
  73         generic map (
  74             PLL_RESET_BITS => 2,
  75             SOC_RESET_BITS => 2,
  76             RESET_LOW => true
  77             )
  78         port map (
  79             ext_clk => ext_clk,
  80             pll_clk => pll_clk,
  81             pll_locked_in => pll_locked_in,
  82             ext_rst_in => ext_rst_in,
  83             pll_rst_out => pll_rst_out,
  84             rst_out => rst_out
  85             );
  86
  87     clock: process
  88     begin
  89         ext_clk <= '0';
  90         pll_clk <= '0';
  91         wait for clk_period/2;
  92         ext_clk <= '1';
  93         pll_clk <= '1';
  94         wait for clk_period/2;
  95     end process clock;
  96
  97     stim: process
  98         variable tv : test_vector;
  99     begin
 100         -- skew us a bit
 101         wait for clk_period/4;
 102
 103         for i in test_vectors'range loop
 104             tv := test_vectors(i);
 105
 106             pll_locked_in <= tv.pll_locked_in;
 107             ext_rst_in <= tv.ext_rst_in;
 108
 109             report " ** STEP " & integer'image(i);
 110             report "pll_locked_in " & std_ulogic'image(pll_locked_in);
 111             report "ext_rst_in " & std_ulogic'image(ext_rst_in);
 112             report "pll_rst_out " & std_ulogic'image(pll_rst_out);
 113             report "rst_out" & std_ulogic'image(rst_out);
 114
 115             assert tv.pll_rst_out = pll_rst_out report
 116                 "pll_rst_out bad exp="  & std_ulogic'image(tv.pll_rst_out) &
 117                 " got=" & std_ulogic'image(pll_rst_out);
 118             assert tv.rst_out    =  rst_out     report
 119                 "rst_out bad exp=" & std_ulogic'image(tv.rst_out) &
 120                 " got=" & std_ulogic'image(rst_out);
 121
 122             wait for clk_period;
 123         end loop;
 124
 125         wait for clk_period;
 126
 127         std.env.finish;
 128     end process;
 129 end behave;