fpga/top-arty.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library unisim;
   6 use unisim.vcomponents.all;
   7
   8 library work;
   9 use work.wishbone_types.all;
  10
  11 entity toplevel is
  12     generic (
  13         MEMORY_SIZE   : positive := 16384;
  14         RAM_INIT_FILE : string   := "firmware.hex";
  15         RESET_LOW     : boolean  := true;
  16         CLK_FREQUENCY : positive := 100000000;
  17         USE_LITEDRAM  : boolean  := false;
  18         DISABLE_FLATTEN_CORE : boolean := false
  19         );
  20     port(
  21         ext_clk   : in  std_ulogic;
  22         ext_rst   : in  std_ulogic;
  23
  24         -- UART0 signals:
  25         uart_main_tx : out std_ulogic;
  26         uart_main_rx : in  std_ulogic;
  27
  28         -- DRAM UART signals (PMOD)
  29         uart_pmod_tx    : out std_ulogic;
  30         uart_pmod_rx    : in std_ulogic;
  31         uart_pmod_cts_n : in std_ulogic;
  32         uart_pmod_rts_n : out std_ulogic;
  33
  34         -- LEDs
  35         led0_b  : out std_ulogic;
  36         led0_g  : out std_ulogic;
  37         led0_r  : out std_ulogic;
  38
  39         -- DRAM wires
  40         ddram_a       : out std_ulogic_vector(13 downto 0);
  41         ddram_ba      : out std_ulogic_vector(2 downto 0);
  42         ddram_ras_n   : out std_ulogic;
  43         ddram_cas_n   : out std_ulogic;
  44         ddram_we_n    : out std_ulogic;
  45         ddram_cs_n    : out std_ulogic;
  46         ddram_dm      : out std_ulogic_vector(1 downto 0);
  47         ddram_dq      : inout std_ulogic_vector(15 downto 0);
  48         ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
  49         ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
  50         ddram_clk_p   : out std_ulogic;
  51         ddram_clk_n   : out std_ulogic;
  52         ddram_cke     : out std_ulogic;
  53         ddram_odt     : out std_ulogic;
  54         ddram_reset_n : out std_ulogic
  55         );
  56 end entity toplevel;
  57
  58 architecture behaviour of toplevel is
  59
  60     -- Reset signals:
  61     signal soc_rst : std_ulogic;
  62     signal pll_rst : std_ulogic;
  63
  64     -- Internal clock signals:
  65     signal system_clk : std_ulogic;
  66     signal system_clk_locked : std_ulogic;
  67
  68     -- DRAM main data wishbone connection
  69     signal wb_dram_in       : wishbone_master_out;
  70     signal wb_dram_out      : wishbone_slave_out;
  71
  72     -- DRAM control wishbone connection
  73     signal wb_dram_ctrl_in  : wb_io_master_out;
  74     signal wb_dram_ctrl_out : wb_io_slave_out;
  75     signal wb_dram_is_csr   : std_ulogic;
  76     signal wb_dram_is_init  : std_ulogic;
  77
  78     -- Control/status
  79     signal core_alt_reset : std_ulogic;
  80
  81     -- Status LED
  82     signal led0_b_pwm : std_ulogic;
  83     signal led0_r_pwm : std_ulogic;
  84     signal led0_g_pwm : std_ulogic;
  85
  86     -- Dumb PWM for the LEDs, those RGB LEDs are too bright otherwise
  87     signal pwm_counter  : std_ulogic_vector(8 downto 0);
  88 begin
  89
  90     uart_pmod_rts_n <= '0';
  91
  92     -- Main SoC
  93     soc0: entity work.soc
  94         generic map(
  95             MEMORY_SIZE   => MEMORY_SIZE,
  96             RAM_INIT_FILE => RAM_INIT_FILE,
  97             RESET_LOW     => RESET_LOW,
  98             SIM           => false,
  99             CLK_FREQ      => CLK_FREQUENCY,
 100             HAS_DRAM      => USE_LITEDRAM,
 101             DRAM_SIZE     => 256 * 1024 * 1024,
 102             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
 103             )
 104         port map (
 105             system_clk        => system_clk,
 106             rst               => soc_rst,
 107             uart0_txd         => uart_main_tx,
 108             uart0_rxd         => uart_main_rx,
 109             wb_dram_in        => wb_dram_in,
 110             wb_dram_out       => wb_dram_out,
 111             wb_dram_ctrl_in   => wb_dram_ctrl_in,
 112             wb_dram_ctrl_out  => wb_dram_ctrl_out,
 113             wb_dram_is_csr    => wb_dram_is_csr,
 114             wb_dram_is_init   => wb_dram_is_init,
 115             alt_reset         => core_alt_reset
 116             );
 117
 118     nodram: if not USE_LITEDRAM generate
 119         signal ddram_clk_dummy : std_ulogic;
 120     begin
 121         reset_controller: entity work.soc_reset
 122             generic map(
 123                 RESET_LOW => RESET_LOW
 124                 )
 125             port map(
 126                 ext_clk => ext_clk,
 127                 pll_clk => system_clk,
 128                 pll_locked_in => system_clk_locked,
 129                 ext_rst_in => ext_rst,
 130                 pll_rst_out => pll_rst,
 131                 rst_out => soc_rst
 132                 );
 133
 134         clkgen: entity work.clock_generator
 135             generic map(
 136                 CLK_INPUT_HZ => 100000000,
 137                 CLK_OUTPUT_HZ => CLK_FREQUENCY
 138                 )
 139             port map(
 140                 ext_clk => ext_clk,
 141                 pll_rst_in => pll_rst,
 142                 pll_clk_out => system_clk,
 143                 pll_locked_out => system_clk_locked
 144                 );
 145
 146         led0_b_pwm <= '1';
 147         led0_r_pwm <= '1';
 148         led0_g_pwm <= '0';
 149         core_alt_reset <= '0';
 150
 151         -- Vivado barfs on those differential signals if left
 152         -- unconnected. So instanciate a diff. buffer and feed
 153         -- it a constant '0'.
 154         dummy_dram_clk: OBUFDS
 155             port map (
 156                 O => ddram_clk_p,
 157                 OB => ddram_clk_n,
 158                 I => ddram_clk_dummy
 159                 );
 160         ddram_clk_dummy <= '0';
 161
 162    end generate;
 163
 164     has_dram: if USE_LITEDRAM generate
 165         signal dram_init_done  : std_ulogic;
 166         signal dram_init_error : std_ulogic;
 167         signal dram_sys_rst    : std_ulogic;
 168     begin
 169
 170         -- Eventually dig out the frequency from the generator
 171         -- but for now, assert it's 100Mhz
 172         assert CLK_FREQUENCY = 100000000;
 173
 174         reset_controller: entity work.soc_reset
 175             generic map(
 176                 RESET_LOW => RESET_LOW,
 177                 PLL_RESET_BITS => 18,
 178                 SOC_RESET_BITS => 1
 179                 )
 180             port map(
 181                 ext_clk => ext_clk,
 182                 pll_clk => system_clk,
 183                 pll_locked_in => '1',
 184                 ext_rst_in => ext_rst,
 185                 pll_rst_out => pll_rst,
 186                 rst_out => open
 187                 );
 188
 189         dram: entity work.litedram_wrapper
 190             generic map(
 191                 DRAM_ABITS => 24,
 192                 DRAM_ALINES => 14
 193                 )
 194             port map(
 195                 clk_in          => ext_clk,
 196                 rst             => pll_rst,
 197                 system_clk      => system_clk,
 198                 system_reset    => soc_rst,
 199                 core_alt_reset  => core_alt_reset,
 200                 pll_locked      => system_clk_locked,
 201
 202                 wb_in           => wb_dram_in,
 203                 wb_out          => wb_dram_out,
 204                 wb_ctrl_in      => wb_dram_ctrl_in,
 205                 wb_ctrl_out     => wb_dram_ctrl_out,
 206                 wb_ctrl_is_csr  => wb_dram_is_csr,
 207                 wb_ctrl_is_init => wb_dram_is_init,
 208
 209                 serial_tx       => uart_pmod_tx,
 210                 serial_rx       => uart_pmod_rx,
 211
 212                 init_done       => dram_init_done,
 213                 init_error      => dram_init_error,
 214
 215                 ddram_a         => ddram_a,
 216                 ddram_ba        => ddram_ba,
 217                 ddram_ras_n     => ddram_ras_n,
 218                 ddram_cas_n     => ddram_cas_n,
 219                 ddram_we_n      => ddram_we_n,
 220                 ddram_cs_n      => ddram_cs_n,
 221                 ddram_dm        => ddram_dm,
 222                 ddram_dq        => ddram_dq,
 223                 ddram_dqs_p     => ddram_dqs_p,
 224                 ddram_dqs_n     => ddram_dqs_n,
 225                 ddram_clk_p     => ddram_clk_p,
 226                 ddram_clk_n     => ddram_clk_n,
 227                 ddram_cke       => ddram_cke,
 228                 ddram_odt       => ddram_odt,
 229                 ddram_reset_n   => ddram_reset_n
 230                 );
 231
 232         led0_b_pwm <= not dram_init_done;
 233         led0_r_pwm <= dram_init_error;
 234         led0_g_pwm <= dram_init_done and not dram_init_error;
 235
 236     end generate;
 237
 238     leds_pwm : process(system_clk)
 239     begin
 240         if rising_edge(system_clk) then
 241             pwm_counter <= std_ulogic_vector(signed(pwm_counter) + 1);
 242             if pwm_counter(8 downto 4) = "00000" then
 243                 led0_b <= led0_b_pwm;
 244                 led0_r <= led0_r_pwm;
 245                 led0_g <= led0_g_pwm;
 246             else
 247                 led0_b <= '0';
 248                 led0_r <= '0';
 249                 led0_g <= '0';
 250             end if;
 251         end if;
 252     end process;
 253
 254 end architecture behaviour;