fpga/top-generic.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.wishbone_types.all;
   6
   7 entity toplevel is
   8     generic (
   9         MEMORY_SIZE   : positive := (384*1024);
  10         RAM_INIT_FILE : string   := "firmware.hex";
  11         RESET_LOW     : boolean  := true;
  12         CLK_INPUT     : positive := 100000000;
  13         CLK_FREQUENCY : positive := 100000000;
  14         DISABLE_FLATTEN_CORE : boolean := false
  15         );
  16     port(
  17         ext_clk   : in  std_ulogic;
  18         ext_rst   : in  std_ulogic;
  19
  20         -- UART0 signals:
  21         uart0_txd : out std_ulogic;
  22         uart0_rxd : in  std_ulogic
  23         );
  24 end entity toplevel;
  25
  26 architecture behaviour of toplevel is
  27
  28     -- Reset signals:
  29     signal soc_rst : std_ulogic;
  30     signal pll_rst : std_ulogic;
  31
  32     -- Internal clock signals:
  33     signal system_clk : std_ulogic;
  34     signal system_clk_locked : std_ulogic;
  35
  36     -- DRAM main data wishbone connection
  37     signal wb_dram_in       : wishbone_master_out;
  38     signal wb_dram_out      : wishbone_slave_out;
  39
  40     -- DRAM control wishbone connection
  41     signal wb_dram_ctrl_in  : wb_io_master_out;
  42     signal wb_dram_ctrl_out : wb_io_slave_out;
  43     signal wb_dram_is_csr   : std_ulogic;
  44     signal wb_dram_is_init  : std_ulogic;
  45
  46 begin
  47
  48     reset_controller: entity work.soc_reset
  49         generic map(
  50             RESET_LOW => RESET_LOW
  51             )
  52         port map(
  53             ext_clk => ext_clk,
  54             pll_clk => system_clk,
  55             pll_locked_in => system_clk_locked,
  56             ext_rst_in => ext_rst,
  57             pll_rst_out => pll_rst,
  58             rst_out => soc_rst
  59             );
  60
  61     clkgen: entity work.clock_generator
  62         generic map(
  63             CLK_INPUT_HZ => CLK_INPUT,
  64             CLK_OUTPUT_HZ => CLK_FREQUENCY
  65             )
  66         port map(
  67             ext_clk => ext_clk,
  68             pll_rst_in => pll_rst,
  69             pll_clk_out => system_clk,
  70             pll_locked_out => system_clk_locked
  71             );
  72
  73     -- Main SoC
  74     soc0: entity work.soc
  75         generic map(
  76             MEMORY_SIZE   => MEMORY_SIZE,
  77             RAM_INIT_FILE => RAM_INIT_FILE,
  78             RESET_LOW     => RESET_LOW,
  79             SIM           => false,
  80             CLK_FREQ      => CLK_FREQUENCY,
  81             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
  82             )
  83         port map (
  84             system_clk        => system_clk,
  85             rst               => soc_rst,
  86             uart0_txd         => uart0_txd,
  87             uart0_rxd         => uart0_rxd,
  88             wb_dram_in        => wb_dram_in,
  89             wb_dram_out       => wb_dram_out,
  90             wb_dram_ctrl_in   => wb_dram_ctrl_in,
  91             wb_dram_ctrl_out  => wb_dram_ctrl_out,
  92             wb_dram_is_csr    => wb_dram_is_csr,
  93             wb_dram_is_init   => wb_dram_is_init,
  94             alt_reset         => '0'
  95             );
  96
  97     -- Dummy DRAM
  98     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
  99     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
 100     wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
 101     wb_dram_ctrl_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
 102     wb_dram_ctrl_out.dat <= x"FFFFFFFF";
 103     wb_dram_ctrl_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
 104
 105 end architecture behaviour;