fpga/top-generic.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity toplevel is
   5     generic (
   6         MEMORY_SIZE   : positive := (384*1024);
   7         RAM_INIT_FILE : string   := "firmware.hex";
   8         RESET_LOW     : boolean  := true;
   9         CLK_INPUT     : positive := 100000000;
  10         CLK_FREQUENCY : positive := 100000000;
  11         DISABLE_FLATTEN_CORE : boolean := false
  12         );
  13     port(
  14         ext_clk   : in  std_ulogic;
  15         ext_rst   : in  std_ulogic;
  16
  17         -- UART0 signals:
  18         uart0_txd : out std_ulogic;
  19         uart0_rxd : in  std_ulogic
  20         );
  21 end entity toplevel;
  22
  23 architecture behaviour of toplevel is
  24
  25     -- Reset signals:
  26     signal soc_rst : std_ulogic;
  27     signal pll_rst : std_ulogic;
  28
  29     -- Internal clock signals:
  30     signal system_clk : std_ulogic;
  31     signal system_clk_locked : std_ulogic;
  32
  33     -- Dummy DRAM
  34     signal wb_dram_in : wishbone_master_out;
  35     signal wb_dram_out : wishbone_slave_out;
  36
  37 begin
  38
  39     reset_controller: entity work.soc_reset
  40         generic map(
  41             RESET_LOW => RESET_LOW
  42             )
  43         port map(
  44             ext_clk => ext_clk,
  45             pll_clk => system_clk,
  46             pll_locked_in => system_clk_locked,
  47             ext_rst_in => ext_rst,
  48             pll_rst_out => pll_rst,
  49             rst_out => soc_rst
  50             );
  51
  52     clkgen: entity work.clock_generator
  53         generic map(
  54             CLK_INPUT_HZ => CLK_INPUT,
  55             CLK_OUTPUT_HZ => CLK_FREQUENCY
  56             )
  57         port map(
  58             ext_clk => ext_clk,
  59             pll_rst_in => pll_rst,
  60             pll_clk_out => system_clk,
  61             pll_locked_out => system_clk_locked
  62             );
  63
  64     -- Main SoC
  65     soc0: entity work.soc
  66         generic map(
  67             MEMORY_SIZE   => MEMORY_SIZE,
  68             RAM_INIT_FILE => RAM_INIT_FILE,
  69             RESET_LOW     => RESET_LOW,
  70             SIM           => false,
  71             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
  72             )
  73         port map (
  74             system_clk        => system_clk,
  75             rst               => soc_rst,
  76             uart0_txd         => uart0_txd,
  77             uart0_rxd         => uart0_rxd
  78             );
  79
  80     -- Dummy DRAM
  81     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
  82     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
  83     wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
  84
  85 end architecture behaviour;