fpga/top-generic.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.wishbone_types.all;
   6
   7 entity toplevel is
   8     generic (
   9         MEMORY_SIZE   : positive := (384*1024);
  10         RAM_INIT_FILE : string   := "firmware.hex";
  11         RESET_LOW     : boolean  := true;
  12         CLK_INPUT     : positive := 100000000;
  13         CLK_FREQUENCY : positive := 100000000;
  14         HAS_FPU       : boolean  := true;
  15         LOG_LENGTH    : natural := 512;
  16         DISABLE_FLATTEN_CORE : boolean := false;
  17         UART_IS_16550 : boolean  := true
  18         );
  19     port(
  20         ext_clk   : in  std_ulogic;
  21         ext_rst   : in  std_ulogic;
  22
  23         -- UART0 signals:
  24         uart0_txd : out std_ulogic;
  25         uart0_rxd : in  std_ulogic
  26         );
  27 end entity toplevel;
  28
  29 architecture behaviour of toplevel is
  30
  31     -- Reset signals:
  32     signal soc_rst : std_ulogic;
  33     signal pll_rst : std_ulogic;
  34
  35     -- Internal clock signals:
  36     signal system_clk : std_ulogic;
  37     signal system_clk_locked : std_ulogic;
  38
  39 begin
  40
  41     reset_controller: entity work.soc_reset
  42         generic map(
  43             RESET_LOW => RESET_LOW
  44             )
  45         port map(
  46             ext_clk => ext_clk,
  47             pll_clk => system_clk,
  48             pll_locked_in => system_clk_locked,
  49             ext_rst_in => ext_rst,
  50             pll_rst_out => pll_rst,
  51             rst_out => soc_rst
  52             );
  53
  54     clkgen: entity work.clock_generator
  55         generic map(
  56             CLK_INPUT_HZ => CLK_INPUT,
  57             CLK_OUTPUT_HZ => CLK_FREQUENCY
  58             )
  59         port map(
  60             ext_clk => ext_clk,
  61             pll_rst_in => pll_rst,
  62             pll_clk_out => system_clk,
  63             pll_locked_out => system_clk_locked
  64             );
  65
  66     -- Main SoC
  67     soc0: entity work.soc
  68         generic map(
  69             MEMORY_SIZE   => MEMORY_SIZE,
  70             RAM_INIT_FILE => RAM_INIT_FILE,
  71             SIM           => false,
  72             CLK_FREQ      => CLK_FREQUENCY,
  73             HAS_FPU       => HAS_FPU,
  74             LOG_LENGTH    => LOG_LENGTH,
  75             DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
  76             UART0_IS_16550     => UART_IS_16550
  77             )
  78         port map (
  79             system_clk        => system_clk,
  80             rst               => soc_rst,
  81             uart0_txd         => uart0_txd,
  82             uart0_rxd         => uart0_rxd
  83             );
  84
  85 end architecture behaviour;