litedram: Remove remnants of riscv-inits
[microwatt.git] / fpga / top-nexys-video.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4
5 library unisim;
6 use unisim.vcomponents.all;
7
8 library work;
9 use work.wishbone_types.all;
10
11 entity toplevel is
12 generic (
13 MEMORY_SIZE : integer := 16384;
14 RAM_INIT_FILE : string := "firmware.hex";
15 RESET_LOW : boolean := true;
16 CLK_FREQUENCY : positive := 100000000;
17 USE_LITEDRAM : boolean := false;
18 NO_BRAM : boolean := false;
19 DISABLE_FLATTEN_CORE : boolean := false
20 );
21 port(
22 ext_clk : in std_ulogic;
23 ext_rst : in std_ulogic;
24
25 -- UART0 signals:
26 uart_main_tx : out std_ulogic;
27 uart_main_rx : in std_ulogic;
28
29 -- LEDs
30 led0 : out std_logic;
31 led1 : out std_logic;
32
33 -- DRAM wires
34 ddram_a : out std_logic_vector(14 downto 0);
35 ddram_ba : out std_logic_vector(2 downto 0);
36 ddram_ras_n : out std_logic;
37 ddram_cas_n : out std_logic;
38 ddram_we_n : out std_logic;
39 ddram_dm : out std_logic_vector(1 downto 0);
40 ddram_dq : inout std_logic_vector(15 downto 0);
41 ddram_dqs_p : inout std_logic_vector(1 downto 0);
42 ddram_dqs_n : inout std_logic_vector(1 downto 0);
43 ddram_clk_p : out std_logic;
44 ddram_clk_n : out std_logic;
45 ddram_cke : out std_logic;
46 ddram_odt : out std_logic;
47 ddram_reset_n : out std_logic
48 );
49 end entity toplevel;
50
51 architecture behaviour of toplevel is
52
53 -- Reset signals:
54 signal soc_rst : std_ulogic;
55 signal pll_rst : std_ulogic;
56
57 -- Internal clock signals:
58 signal system_clk : std_ulogic;
59 signal system_clk_locked : std_ulogic;
60
61 -- DRAM main data wishbone connection
62 signal wb_dram_in : wishbone_master_out;
63 signal wb_dram_out : wishbone_slave_out;
64
65 -- DRAM control wishbone connection
66 signal wb_dram_ctrl_in : wb_io_master_out;
67 signal wb_dram_ctrl_out : wb_io_slave_out;
68 signal wb_dram_is_csr : std_ulogic;
69 signal wb_dram_is_init : std_ulogic;
70
71 -- Control/status
72 signal core_alt_reset : std_ulogic;
73
74 -- Fixup various memory sizes based on generics
75 function get_bram_size return natural is
76 begin
77 if USE_LITEDRAM and NO_BRAM then
78 return 0;
79 else
80 return MEMORY_SIZE;
81 end if;
82 end function;
83
84 function get_payload_size return natural is
85 begin
86 if USE_LITEDRAM and NO_BRAM then
87 return MEMORY_SIZE;
88 else
89 return 0;
90 end if;
91 end function;
92
93 constant BRAM_SIZE : natural := get_bram_size;
94 constant PAYLOAD_SIZE : natural := get_payload_size;
95 begin
96
97 -- Main SoC
98 soc0: entity work.soc
99 generic map(
100 MEMORY_SIZE => BRAM_SIZE,
101 RAM_INIT_FILE => RAM_INIT_FILE,
102 RESET_LOW => RESET_LOW,
103 SIM => false,
104 CLK_FREQ => CLK_FREQUENCY,
105 HAS_DRAM => USE_LITEDRAM,
106 DRAM_SIZE => 512 * 1024 * 1024,
107 DRAM_INIT_SIZE => PAYLOAD_SIZE,
108 DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE
109 )
110 port map (
111 system_clk => system_clk,
112 rst => soc_rst,
113 uart0_txd => uart_main_tx,
114 uart0_rxd => uart_main_rx,
115 wb_dram_in => wb_dram_in,
116 wb_dram_out => wb_dram_out,
117 wb_dram_ctrl_in => wb_dram_ctrl_in,
118 wb_dram_ctrl_out => wb_dram_ctrl_out,
119 wb_dram_is_csr => wb_dram_is_csr,
120 wb_dram_is_init => wb_dram_is_init,
121 alt_reset => core_alt_reset
122 );
123
124 nodram: if not USE_LITEDRAM generate
125 signal ddram_clk_dummy : std_ulogic;
126 begin
127 reset_controller: entity work.soc_reset
128 generic map(
129 RESET_LOW => RESET_LOW
130 )
131 port map(
132 ext_clk => ext_clk,
133 pll_clk => system_clk,
134 pll_locked_in => system_clk_locked,
135 ext_rst_in => ext_rst,
136 pll_rst_out => pll_rst,
137 rst_out => soc_rst
138 );
139
140 clkgen: entity work.clock_generator
141 generic map(
142 CLK_INPUT_HZ => 100000000,
143 CLK_OUTPUT_HZ => CLK_FREQUENCY
144 )
145 port map(
146 ext_clk => ext_clk,
147 pll_rst_in => pll_rst,
148 pll_clk_out => system_clk,
149 pll_locked_out => system_clk_locked
150 );
151
152 led0 <= '1';
153 led1 <= not soc_rst;
154 core_alt_reset <= '0';
155
156 -- Vivado barfs on those differential signals if left
157 -- unconnected. So instanciate a diff. buffer and feed
158 -- it a constant '0'.
159 dummy_dram_clk: OBUFDS
160 port map (
161 O => ddram_clk_p,
162 OB => ddram_clk_n,
163 I => ddram_clk_dummy
164 );
165 ddram_clk_dummy <= '0';
166
167 end generate;
168
169 has_dram: if USE_LITEDRAM generate
170 signal dram_init_done : std_ulogic;
171 signal dram_init_error : std_ulogic;
172 signal dram_sys_rst : std_ulogic;
173 begin
174
175 -- Eventually dig out the frequency from the generator
176 -- but for now, assert it's 100Mhz
177 assert CLK_FREQUENCY = 100000000;
178
179 reset_controller: entity work.soc_reset
180 generic map(
181 RESET_LOW => RESET_LOW,
182 PLL_RESET_BITS => 18,
183 SOC_RESET_BITS => 1
184 )
185 port map(
186 ext_clk => ext_clk,
187 pll_clk => system_clk,
188 pll_locked_in => '1',
189 ext_rst_in => ext_rst,
190 pll_rst_out => pll_rst,
191 rst_out => open
192 );
193
194 dram: entity work.litedram_wrapper
195 generic map(
196 DRAM_ABITS => 25,
197 DRAM_ALINES => 15,
198 PAYLOAD_FILE => RAM_INIT_FILE,
199 PAYLOAD_SIZE => PAYLOAD_SIZE
200 )
201 port map(
202 clk_in => ext_clk,
203 rst => pll_rst,
204 system_clk => system_clk,
205 system_reset => soc_rst,
206 pll_locked => system_clk_locked,
207
208 wb_in => wb_dram_in,
209 wb_out => wb_dram_out,
210 wb_ctrl_in => wb_dram_ctrl_in,
211 wb_ctrl_out => wb_dram_ctrl_out,
212 wb_ctrl_is_csr => wb_dram_is_csr,
213 wb_ctrl_is_init => wb_dram_is_init,
214
215 init_done => dram_init_done,
216 init_error => dram_init_error,
217
218 ddram_a => ddram_a,
219 ddram_ba => ddram_ba,
220 ddram_ras_n => ddram_ras_n,
221 ddram_cas_n => ddram_cas_n,
222 ddram_we_n => ddram_we_n,
223 ddram_cs_n => open,
224 ddram_dm => ddram_dm,
225 ddram_dq => ddram_dq,
226 ddram_dqs_p => ddram_dqs_p,
227 ddram_dqs_n => ddram_dqs_n,
228 ddram_clk_p => ddram_clk_p,
229 ddram_clk_n => ddram_clk_n,
230 ddram_cke => ddram_cke,
231 ddram_odt => ddram_odt,
232 ddram_reset_n => ddram_reset_n
233 );
234
235 led0 <= dram_init_done and not dram_init_error;
236 led1 <= dram_init_error; -- Make it blink ?
237
238 end generate;
239 end architecture behaviour;