frontends/aiger/aigerparse.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *                2019  Eddie Hung <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #ifndef ABC_AIGERPARSE
  22 #define ABC_AIGERPARSE
  23
  24 #include "kernel/yosys.h"
  25
  26 YOSYS_NAMESPACE_BEGIN
  27
  28 struct AigerReader
  29 {
  30     RTLIL::Design *design;
  31     std::istream &f;
  32     RTLIL::IdString clk_name;
  33     RTLIL::Module *module;
  34     std::string map_filename;
  35     bool wideports;
  36     const int aiger_autoidx;
  37
  38     unsigned M, I, L, O, A;
  39     unsigned B, C, J, F; // Optional in AIGER 1.9
  40     unsigned line_count;
  41     uint32_t piNum, flopNum;
  42
  43     std::vector<RTLIL::Wire*> inputs;
  44     std::vector<RTLIL::Wire*> latches;
  45     std::vector<RTLIL::Wire*> outputs;
  46     std::vector<RTLIL::Wire*> bad_properties;
  47     std::vector<RTLIL::Cell*> boxes;
  48     std::vector<int> mergeability, initial_state;
  49
  50     AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
  51     void parse_aiger();
  52     void parse_xaiger();
  53     void parse_aiger_ascii();
  54     void parse_aiger_binary();
  55     void post_process();
  56
  57     RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal);
  58 };
  59
  60 YOSYS_NAMESPACE_END
  61
  62 #endif