2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #ifndef ABC_AIGERPARSE
22 #define ABC_AIGERPARSE
24 #include "kernel/yosys.h"
30 RTLIL::Design
*design
;
32 RTLIL::IdString clk_name
;
33 RTLIL::Module
*module
;
34 std::string map_filename
;
36 const int aiger_autoidx
;
38 unsigned M
, I
, L
, O
, A
;
39 unsigned B
, C
, J
, F
; // Optional in AIGER 1.9
41 uint32_t piNum
, flopNum
;
43 std::vector
<RTLIL::Wire
*> inputs
;
44 std::vector
<RTLIL::Wire
*> latches
;
45 std::vector
<RTLIL::Wire
*> outputs
;
46 std::vector
<RTLIL::Wire
*> bad_properties
;
47 std::vector
<RTLIL::Cell
*> boxes
;
49 AigerReader(RTLIL::Design
*design
, std::istream
&f
, RTLIL::IdString module_name
, RTLIL::IdString clk_name
, std::string map_filename
, bool wideports
);
52 void parse_aiger_ascii();
53 void parse_aiger_binary();
56 RTLIL::Wire
* createWireIfNotExists(RTLIL::Module
*module
, unsigned literal
);