2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
38 using namespace AST_INTERNAL
;
40 // instanciate global variables (public API)
42 std::string current_filename
;
43 void (*set_line_num
)(int) = NULL
;
44 int (*get_line_num
)() = NULL
;
47 // instanciate global variables (private API)
48 namespace AST_INTERNAL
{
49 bool flag_dump_ast1
, flag_dump_ast2
, flag_dump_vlog
, flag_nolatches
, flag_nomem2reg
, flag_mem2reg
, flag_lib
, flag_noopt
, flag_icells
, flag_autowire
;
50 AstNode
*current_ast
, *current_ast_mod
;
51 std::map
<std::string
, AstNode
*> current_scope
;
52 RTLIL::SigSpec
*genRTLIL_subst_from
= NULL
;
53 RTLIL::SigSpec
*genRTLIL_subst_to
= NULL
;
54 RTLIL::SigSpec ignoreThisSignalsInInitial
;
55 AstNode
*current_top_block
, *current_block
, *current_block_child
;
56 AstModule
*current_module
;
59 // convert node types to string
60 std::string
AST::type2str(AstNodeType type
)
64 #define X(_item) case _item: return #_item;
155 // check if attribute exists and has non-zero value
156 bool AstNode::get_bool_attribute(RTLIL::IdString id
)
158 if (attributes
.count(id
) == 0)
161 AstNode
*attr
= attributes
.at(id
);
162 if (attr
->type
!= AST_CONSTANT
)
163 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
164 id
.c_str(), attr
->filename
.c_str(), attr
->linenum
);
166 return attr
->integer
!= 0;
169 // create new node (AstNode constructor)
170 // (the optional child arguments make it easier to create AST trees)
171 AstNode::AstNode(AstNodeType type
, AstNode
*child1
, AstNode
*child2
)
174 filename
= current_filename
;
175 linenum
= get_line_num();
190 children
.push_back(child1
);
192 children
.push_back(child2
);
195 // create a (deep recursive) copy of a node
196 AstNode
*AstNode::clone()
198 AstNode
*that
= new AstNode
;
200 for (auto &it
: that
->children
)
202 for (auto &it
: that
->attributes
)
203 it
.second
= it
.second
->clone();
207 // create a (deep recursive) copy of a node use 'other' as target root node
208 void AstNode::cloneInto(AstNode
*other
)
210 AstNode
*tmp
= clone();
211 other
->delete_children();
213 tmp
->children
.clear();
214 tmp
->attributes
.clear();
218 // delete all children in this node
219 void AstNode::delete_children()
221 for (auto &it
: children
)
225 for (auto &it
: attributes
)
230 // AstNode destructor
236 // create a nice text representation of the node
237 // (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
238 void AstNode::dumpAst(FILE *f
, std::string indent
)
241 for (auto f
: log_files
)
246 std::string type_name
= type2str(type
);
247 fprintf(f
, "%s%s <%s:%d>", indent
.c_str(), type_name
.c_str(), filename
.c_str(), linenum
);
250 fprintf(f
, " [%p -> %p]", this, id2ast
);
252 fprintf(f
, " [%p]", this);
255 fprintf(f
, " str='%s'", str
.c_str());
257 fprintf(f
, " bits='");
258 for (size_t i
= bits
.size(); i
> 0; i
--)
259 fprintf(f
, "%c", bits
[i
-1] == RTLIL::S0
? '0' :
260 bits
[i
-1] == RTLIL::S1
? '1' :
261 bits
[i
-1] == RTLIL::Sx
? 'x' :
262 bits
[i
-1] == RTLIL::Sz
? 'z' : '?');
263 fprintf(f
, "'(%zd)", bits
.size());
266 fprintf(f
, " input");
268 fprintf(f
, " output");
272 fprintf(f
, " signed");
274 fprintf(f
, " port=%d", port_id
);
275 if (range_valid
|| range_left
!= -1 || range_right
!= 0)
276 fprintf(f
, " range=[%d:%d]%s", range_left
, range_right
, range_valid
? "" : "!");
278 fprintf(f
, " int=%u", (int)integer
);
281 for (auto &it
: attributes
) {
282 fprintf(f
, "%s ATTR %s:\n", indent
.c_str(), it
.first
.c_str());
283 it
.second
->dumpAst(f
, indent
+ " ");
286 for (size_t i
= 0; i
< children
.size(); i
++)
287 children
[i
]->dumpAst(f
, indent
+ " ");
290 // helper function for AstNode::dumpVlog()
291 static std::string
id2vl(std::string txt
)
293 if (txt
.size() > 1 && txt
[0] == '\\')
295 for (size_t i
= 0; i
< txt
.size(); i
++) {
296 if ('A' <= txt
[i
] && txt
[i
] <= 'Z') continue;
297 if ('a' <= txt
[i
] && txt
[i
] <= 'z') continue;
298 if ('0' <= txt
[i
] && txt
[i
] <= '9') continue;
299 if (txt
[i
] == '_') continue;
300 txt
= "\\" + txt
+ " ";
306 // dump AST node as verilog pseudo-code
307 void AstNode::dumpVlog(FILE *f
, std::string indent
)
311 std::vector
<AstNode
*> rem_children1
, rem_children2
;
314 for (auto f
: log_files
)
319 for (auto &it
: attributes
) {
320 fprintf(f
, "%s" "(* %s = ", indent
.c_str(), id2vl(it
.first
).c_str());
321 it
.second
->dumpVlog(f
, "");
322 fprintf(f
, " *)%s", indent
.empty() ? "" : "\n");
328 fprintf(f
, "%s" "module %s(", indent
.c_str(), id2vl(str
).c_str());
329 for (auto child
: children
)
330 if (child
->type
== AST_WIRE
&& (child
->is_input
|| child
->is_output
)) {
331 fprintf(f
, "%s%s", first
? "" : ", ", id2vl(child
->str
).c_str());
336 for (auto child
: children
)
337 if (child
->type
== AST_PARAMETER
|| child
->type
== AST_LOCALPARAM
|| child
->type
== AST_DEFPARAM
)
338 child
->dumpVlog(f
, indent
+ " ");
340 rem_children1
.push_back(child
);
342 for (auto child
: rem_children1
)
343 if (child
->type
== AST_WIRE
|| child
->type
== AST_AUTOWIRE
|| child
->type
== AST_MEMORY
)
344 child
->dumpVlog(f
, indent
+ " ");
346 rem_children2
.push_back(child
);
347 rem_children1
.clear();
349 for (auto child
: rem_children2
)
350 if (child
->type
== AST_TASK
|| child
->type
== AST_FUNCTION
)
351 child
->dumpVlog(f
, indent
+ " ");
353 rem_children1
.push_back(child
);
354 rem_children2
.clear();
356 for (auto child
: rem_children1
)
357 child
->dumpVlog(f
, indent
+ " ");
358 rem_children1
.clear();
360 fprintf(f
, "%s" "endmodule\n", indent
.c_str());
364 if (is_input
&& is_output
)
365 fprintf(f
, "%s" "inout", indent
.c_str());
367 fprintf(f
, "%s" "input", indent
.c_str());
369 fprintf(f
, "%s" "output", indent
.c_str());
371 fprintf(f
, "%s" "wire", indent
.c_str());
373 fprintf(f
, "%s" "reg", (is_input
|| is_output
) ? " " : indent
.c_str());
375 fprintf(f
, " signed");
376 for (auto child
: children
) {
378 child
->dumpVlog(f
, "");
380 fprintf(f
, " %s", id2vl(str
).c_str());
385 fprintf(f
, "%s" "memory", indent
.c_str());
387 fprintf(f
, " signed");
388 for (auto child
: children
) {
390 child
->dumpVlog(f
, "");
392 fprintf(f
, " %s", id2vl(str
).c_str());
400 fprintf(f
, "[%d:%d]", range_left
, range_right
);
402 for (auto child
: children
) {
403 fprintf(f
, "%c", first
? '[' : ':');
404 child
->dumpVlog(f
, "");
412 fprintf(f
, "%s" "always @(", indent
.c_str());
413 for (auto child
: children
) {
414 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
418 child
->dumpVlog(f
, "");
422 for (auto child
: children
) {
423 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
424 child
->dumpVlog(f
, indent
+ " ");
429 fprintf(f
, "%s" "initial\n", indent
.c_str());
430 for (auto child
: children
) {
431 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
432 child
->dumpVlog(f
, indent
+ " ");
439 if (type
== AST_POSEDGE
)
440 fprintf(f
, "posedge ");
441 if (type
== AST_NEGEDGE
)
442 fprintf(f
, "negedge ");
443 for (auto child
: children
)
444 child
->dumpVlog(f
, "");
448 fprintf(f
, "%s", id2vl(str
).c_str());
449 for (auto child
: children
)
450 child
->dumpVlog(f
, "");
455 fprintf(f
, "\"%s\"", str
.c_str());
456 else if (bits
.size() == 32)
457 fprintf(f
, "%d", RTLIL::Const(bits
).as_int());
459 fprintf(f
, "%zd'b %s", bits
.size(), RTLIL::Const(bits
).as_string().c_str());
463 if (children
.size() == 1) {
464 children
[0]->dumpVlog(f
, indent
);
466 fprintf(f
, "%s" "begin\n", indent
.c_str());
467 for (auto child
: children
)
468 child
->dumpVlog(f
, indent
+ " ");
469 fprintf(f
, "%s" "end\n", indent
.c_str());
474 fprintf(f
, "%s" "case (", indent
.c_str());
475 children
[0]->dumpVlog(f
, "");
477 for (size_t i
= 1; i
< children
.size(); i
++) {
478 AstNode
*child
= children
[i
];
479 child
->dumpVlog(f
, indent
+ " ");
481 fprintf(f
, "%s" "endcase\n", indent
.c_str());
485 for (auto child
: children
) {
486 if (child
->type
== AST_BLOCK
) {
488 child
->dumpVlog(f
, indent
+ " ");
491 fprintf(f
, "%s", first
? indent
.c_str() : ", ");
492 if (child
->type
== AST_DEFAULT
)
493 fprintf(f
, "default");
495 child
->dumpVlog(f
, "");
503 fprintf(f
, "%s", indent
.c_str());
504 children
[0]->dumpVlog(f
, "");
505 fprintf(f
, " %s ", type
== AST_ASSIGN_EQ
? "=" : "<=");
506 children
[1]->dumpVlog(f
, "");
512 for (auto child
: children
) {
515 child
->dumpVlog(f
, "");
523 children
[0]->dumpVlog(f
, "");
525 children
[1]->dumpVlog(f
, "");
529 if (0) { case AST_BIT_NOT
: txt
= "~"; }
530 if (0) { case AST_REDUCE_AND
: txt
= "&"; }
531 if (0) { case AST_REDUCE_OR
: txt
= "|"; }
532 if (0) { case AST_REDUCE_XOR
: txt
= "^"; }
533 if (0) { case AST_REDUCE_XNOR
: txt
= "~^"; }
534 if (0) { case AST_REDUCE_BOOL
: txt
= "|"; }
535 if (0) { case AST_POS
: txt
= "+"; }
536 if (0) { case AST_NEG
: txt
= "-"; }
537 if (0) { case AST_LOGIC_NOT
: txt
= "!"; }
538 fprintf(f
, "%s(", txt
.c_str());
539 children
[0]->dumpVlog(f
, "");
543 if (0) { case AST_BIT_AND
: txt
= "&"; }
544 if (0) { case AST_BIT_OR
: txt
= "|"; }
545 if (0) { case AST_BIT_XOR
: txt
= "^"; }
546 if (0) { case AST_BIT_XNOR
: txt
= "~^"; }
547 if (0) { case AST_SHIFT_LEFT
: txt
= "<<"; }
548 if (0) { case AST_SHIFT_RIGHT
: txt
= ">>"; }
549 if (0) { case AST_SHIFT_SLEFT
: txt
= "<<<"; }
550 if (0) { case AST_SHIFT_SRIGHT
: txt
= ">>>"; }
551 if (0) { case AST_LT
: txt
= "<"; }
552 if (0) { case AST_LE
: txt
= "<="; }
553 if (0) { case AST_EQ
: txt
= "=="; }
554 if (0) { case AST_NE
: txt
= "!="; }
555 if (0) { case AST_EQX
: txt
= "==="; }
556 if (0) { case AST_NEX
: txt
= "!=="; }
557 if (0) { case AST_GE
: txt
= ">="; }
558 if (0) { case AST_GT
: txt
= ">"; }
559 if (0) { case AST_ADD
: txt
= "+"; }
560 if (0) { case AST_SUB
: txt
= "-"; }
561 if (0) { case AST_MUL
: txt
= "*"; }
562 if (0) { case AST_DIV
: txt
= "/"; }
563 if (0) { case AST_MOD
: txt
= "%"; }
564 if (0) { case AST_POW
: txt
= "**"; }
565 if (0) { case AST_LOGIC_AND
: txt
= "&&"; }
566 if (0) { case AST_LOGIC_OR
: txt
= "||"; }
568 children
[0]->dumpVlog(f
, "");
569 fprintf(f
, ")%s(", txt
.c_str());
570 children
[1]->dumpVlog(f
, "");
576 children
[0]->dumpVlog(f
, "");
578 children
[1]->dumpVlog(f
, "");
580 children
[2]->dumpVlog(f
, "");
585 std::string type_name
= type2str(type
);
586 fprintf(f
, "%s" "/** %s **/%s", indent
.c_str(), type_name
.c_str(), indent
.empty() ? "" : "\n");
587 // dumpAst(f, indent, NULL);
591 // check if two AST nodes are identical
592 bool AstNode::operator==(const AstNode
&other
) const
594 if (type
!= other
.type
)
596 if (children
.size() != other
.children
.size())
598 if (str
!= other
.str
)
600 if (bits
!= other
.bits
)
602 if (is_input
!= other
.is_input
)
604 if (is_output
!= other
.is_output
)
606 if (is_reg
!= other
.is_reg
)
608 if (is_signed
!= other
.is_signed
)
610 if (is_string
!= other
.is_string
)
612 if (range_valid
!= other
.range_valid
)
614 if (port_id
!= other
.port_id
)
616 if (range_left
!= other
.range_left
)
618 if (range_right
!= other
.range_right
)
620 if (integer
!= other
.integer
)
622 for (size_t i
= 0; i
< children
.size(); i
++)
623 if (*children
[i
] != *other
.children
[i
])
628 // check if two AST nodes are not identical
629 bool AstNode::operator!=(const AstNode
&other
) const
631 return !(*this == other
);
634 // check if this AST contains the given node
635 bool AstNode::contains(const AstNode
*other
) const
639 for (auto child
: children
)
640 if (child
->contains(other
))
645 // create an AST node for a constant (using a 32 bit int as value)
646 AstNode
*AstNode::mkconst_int(uint32_t v
, bool is_signed
, int width
)
648 AstNode
*node
= new AstNode(AST_CONSTANT
);
650 node
->is_signed
= is_signed
;
651 for (int i
= 0; i
< width
; i
++) {
652 node
->bits
.push_back((v
& 1) ? RTLIL::S1
: RTLIL::S0
);
655 node
->range_valid
= true;
656 node
->range_left
= width
-1;
657 node
->range_right
= 0;
661 // create an AST node for a constant (using a bit vector as value)
662 AstNode
*AstNode::mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
)
664 AstNode
*node
= new AstNode(AST_CONSTANT
);
665 node
->is_signed
= is_signed
;
667 for (size_t i
= 0; i
< 32; i
++) {
668 if (i
< node
->bits
.size())
669 node
->integer
|= (node
->bits
[i
] == RTLIL::S1
) << i
;
671 node
->integer
|= (node
->bits
.back() == RTLIL::S1
) << i
;
673 node
->range_valid
= true;
674 node
->range_left
= node
->bits
.size()-1;
675 node
->range_right
= 0;
679 // create an AST node for a constant (using a string in bit vector form as value)
680 AstNode
*AstNode::mkconst_str(const std::vector
<RTLIL::State
> &v
)
682 AstNode
*node
= mkconst_str(RTLIL::Const(v
).decode_string());
683 log_assert(node
->bits
== v
);
687 // create an AST node for a constant (using a string as value)
688 AstNode
*AstNode::mkconst_str(const std::string
&str
)
690 std::vector
<RTLIL::State
> data
;
691 data
.reserve(str
.size() * 8);
692 for (size_t i
= 0; i
< str
.size(); i
++) {
693 unsigned char ch
= str
[str
.size() - i
- 1];
694 for (int j
= 0; j
< 8; j
++) {
695 data
.push_back((ch
& 1) ? RTLIL::S1
: RTLIL::S0
);
699 AstNode
*node
= AstNode::mkconst_bits(data
, false);
700 node
->is_string
= true;
705 RTLIL::Const
AstNode::bitsAsConst(int width
, bool is_signed
)
707 std::vector
<RTLIL::State
> bits
= this->bits
;
708 if (width
>= 0 && width
< int(bits
.size()))
710 if (width
>= 0 && width
> int(bits
.size())) {
711 RTLIL::State extbit
= RTLIL::State::S0
;
712 if (is_signed
&& !bits
.empty())
713 extbit
= bits
.back();
714 while (width
> int(bits
.size()))
715 bits
.push_back(extbit
);
717 return RTLIL::Const(bits
);
720 RTLIL::Const
AstNode::bitsAsConst(int width
)
722 return bitsAsConst(width
, is_signed
);
725 RTLIL::Const
AstNode::asAttrConst()
727 log_assert(type
== AST_CONSTANT
);
733 val
.flags
|= RTLIL::CONST_FLAG_STRING
;
734 log_assert(val
.decode_string() == str
);
740 RTLIL::Const
AstNode::asParaConst()
742 RTLIL::Const val
= asAttrConst();
744 val
.flags
|= RTLIL::CONST_FLAG_SIGNED
;
748 bool AstNode::asBool()
750 log_assert(type
== AST_CONSTANT
);
751 for (auto &bit
: bits
)
752 if (bit
== RTLIL::State::S1
)
757 // create a new AstModule from an AST_MODULE AST node
758 static AstModule
* process_module(AstNode
*ast
, bool defer
)
760 assert(ast
->type
== AST_MODULE
);
763 log("Storing AST representation for module `%s'.\n", ast
->str
.c_str());
765 log("Generating RTLIL representation for module `%s'.\n", ast
->str
.c_str());
767 current_module
= new AstModule
;
768 current_module
->ast
= NULL
;
769 current_module
->name
= ast
->str
;
770 current_module
->attributes
["\\src"] = stringf("%s:%d", ast
->filename
.c_str(), ast
->linenum
);
772 current_ast_mod
= ast
;
773 AstNode
*ast_before_simplify
= ast
->clone();
775 if (flag_dump_ast1
) {
776 log("Dumping verilog AST before simplification:\n");
777 ast
->dumpAst(NULL
, " ");
778 log("--- END OF AST DUMP ---\n");
783 while (ast
->simplify(!flag_noopt
, false, false, 0, -1, false, false)) { }
785 if (flag_dump_ast2
) {
786 log("Dumping verilog AST after simplification:\n");
787 ast
->dumpAst(NULL
, " ");
788 log("--- END OF AST DUMP ---\n");
791 if (flag_dump_vlog
) {
792 log("Dumping verilog AST (as requested by dump_vlog option):\n");
793 ast
->dumpVlog(NULL
, " ");
794 log("--- END OF AST DUMP ---\n");
798 std::vector
<AstNode
*> new_children
;
799 for (auto child
: ast
->children
) {
800 if (child
->type
== AST_WIRE
&& (child
->is_input
|| child
->is_output
))
801 new_children
.push_back(child
);
805 ast
->children
.swap(new_children
);
806 ast
->attributes
["\\blackbox"] = AstNode::mkconst_int(1, false);
809 ignoreThisSignalsInInitial
= RTLIL::SigSpec();
811 for (auto &attr
: ast
->attributes
) {
812 if (attr
.second
->type
!= AST_CONSTANT
)
813 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
814 attr
.first
.c_str(), ast
->filename
.c_str(), ast
->linenum
);
815 current_module
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
817 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
818 AstNode
*node
= ast
->children
[i
];
819 if (node
->type
== AST_WIRE
|| node
->type
== AST_MEMORY
)
822 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
823 AstNode
*node
= ast
->children
[i
];
824 if (node
->type
!= AST_WIRE
&& node
->type
!= AST_MEMORY
&& node
->type
!= AST_INITIAL
)
828 ignoreThisSignalsInInitial
.sort_and_unify();
830 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
831 AstNode
*node
= ast
->children
[i
];
832 if (node
->type
== AST_INITIAL
)
836 ignoreThisSignalsInInitial
= RTLIL::SigSpec();
839 current_module
->ast
= ast_before_simplify
;
840 current_module
->nolatches
= flag_nolatches
;
841 current_module
->nomem2reg
= flag_nomem2reg
;
842 current_module
->mem2reg
= flag_mem2reg
;
843 current_module
->lib
= flag_lib
;
844 current_module
->noopt
= flag_noopt
;
845 current_module
->icells
= flag_icells
;
846 current_module
->autowire
= flag_autowire
;
847 return current_module
;
850 // create AstModule instances for all modules in the AST tree and add them to 'design'
851 void AST::process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast1
, bool dump_ast2
, bool dump_vlog
, bool nolatches
, bool nomem2reg
, bool mem2reg
, bool lib
, bool noopt
, bool icells
, bool ignore_redef
, bool defer
, bool autowire
)
854 flag_dump_ast1
= dump_ast1
;
855 flag_dump_ast2
= dump_ast2
;
856 flag_dump_vlog
= dump_vlog
;
857 flag_nolatches
= nolatches
;
858 flag_nomem2reg
= nomem2reg
;
859 flag_mem2reg
= mem2reg
;
862 flag_icells
= icells
;
863 flag_autowire
= autowire
;
865 assert(current_ast
->type
== AST_DESIGN
);
866 for (auto it
= current_ast
->children
.begin(); it
!= current_ast
->children
.end(); it
++) {
867 if (flag_icells
&& (*it
)->str
.substr(0, 2) == "\\$")
868 (*it
)->str
= (*it
)->str
.substr(1);
870 (*it
)->str
= "$abstract" + (*it
)->str
;
871 if (design
->modules
.count((*it
)->str
)) {
873 log_error("Re-definition of module `%s' at %s:%d!\n",
874 (*it
)->str
.c_str(), (*it
)->filename
.c_str(), (*it
)->linenum
);
875 log_error("Ignoring re-definition of module `%s' at %s:%d!\n",
876 (*it
)->str
.c_str(), (*it
)->filename
.c_str(), (*it
)->linenum
);
879 design
->modules
[(*it
)->str
] = process_module(*it
, defer
);
883 // AstModule destructor
884 AstModule::~AstModule()
890 // create a new parametric module (when needed) and return the name of the generated module
891 RTLIL::IdString
AstModule::derive(RTLIL::Design
*design
, std::map
<RTLIL::IdString
, RTLIL::Const
> parameters
)
893 std::string stripped_name
= name
;
895 if (stripped_name
.substr(0, 9) == "$abstract")
896 stripped_name
= stripped_name
.substr(9);
898 log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name
.c_str());
901 flag_dump_ast1
= false;
902 flag_dump_ast2
= false;
903 flag_dump_vlog
= false;
904 flag_nolatches
= nolatches
;
905 flag_nomem2reg
= nomem2reg
;
906 flag_mem2reg
= mem2reg
;
909 flag_icells
= icells
;
910 flag_autowire
= autowire
;
911 use_internal_line_num();
913 std::string para_info
;
914 std::vector
<unsigned char> hash_data
;
915 hash_data
.insert(hash_data
.end(), stripped_name
.begin(), stripped_name
.end());
916 hash_data
.push_back(0);
918 AstNode
*new_ast
= ast
->clone();
920 int para_counter
= 0;
921 int orig_parameters_n
= parameters
.size();
922 for (auto it
= new_ast
->children
.begin(); it
!= new_ast
->children
.end(); it
++) {
923 AstNode
*child
= *it
;
924 if (child
->type
!= AST_PARAMETER
)
927 std::string para_id
= child
->str
;
928 if (parameters
.count(para_id
) > 0) {
929 log("Parameter %s = %s\n", child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[child
->str
])));
931 para_info
+= stringf("%s=%s", child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[para_id
])));
932 delete child
->children
.at(0);
933 child
->children
[0] = AstNode::mkconst_bits(parameters
[para_id
].bits
, (parameters
[para_id
].flags
& RTLIL::CONST_FLAG_SIGNED
) != 0);
934 hash_data
.insert(hash_data
.end(), child
->str
.begin(), child
->str
.end());
935 hash_data
.push_back(0);
936 hash_data
.insert(hash_data
.end(), parameters
[para_id
].bits
.begin(), parameters
[para_id
].bits
.end());
937 hash_data
.push_back(0xff);
938 parameters
.erase(para_id
);
941 para_id
= stringf("$%d", para_counter
);
942 if (parameters
.count(para_id
) > 0) {
943 log("Parameter %d (%s) = %s\n", para_counter
, child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[para_id
])));
944 goto rewrite_parameter
;
947 if (parameters
.size() > 0)
948 log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters
.begin()->first
.c_str(), stripped_name
.c_str());
952 if (orig_parameters_n
== 0)
954 modname
= stripped_name
;
957 if (para_info
.size() > 60)
959 unsigned char hash
[20];
960 unsigned char *hash_data2
= new unsigned char[hash_data
.size()];
961 for (size_t i
= 0; i
< hash_data
.size(); i
++)
962 hash_data2
[i
] = hash_data
[i
];
963 sha1::calc(hash_data2
, hash_data
.size(), hash
);
967 sha1::toHexString(hash
, hexstring
);
969 modname
= "$paramod$" + std::string(hexstring
) + stripped_name
;
973 modname
= "$paramod" + stripped_name
+ para_info
;
976 if (design
->modules
.count(modname
) == 0) {
977 new_ast
->str
= modname
;
978 design
->modules
[modname
] = process_module(new_ast
, false);
979 design
->modules
[modname
]->check();
981 log("Found cached RTLIL representation for module `%s'.\n", modname
.c_str());
988 RTLIL::Module
*AstModule::clone() const
990 AstModule
*new_mod
= new AstModule
;
993 new_mod
->ast
= ast
->clone();
994 new_mod
->nolatches
= nolatches
;
995 new_mod
->nomem2reg
= nomem2reg
;
996 new_mod
->mem2reg
= mem2reg
;
998 new_mod
->noopt
= noopt
;
999 new_mod
->icells
= icells
;
1000 new_mod
->autowire
= autowire
;
1005 // internal dummy line number callbacks
1007 int internal_line_num
;
1008 void internal_set_line_num(int n
) {
1009 internal_line_num
= n
;
1011 int internal_get_line_num() {
1012 return internal_line_num
;
1016 // use internal dummy line number callbacks
1017 void AST::use_internal_line_num()
1019 set_line_num
= &internal_set_line_num
;
1020 get_line_num
= &internal_get_line_num
;