frontends/ast/ast.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  This is the AST frontend library.
  21  *
  22  *  The AST frontend library is not a frontend on it's own but provides a
  23  *  generic abstract syntax tree (AST) abstraction for HDL code and can be
  24  *  used by HDL frontends. See "ast.h" for an overview of the API and the
  25  *  Verilog frontend for an usage example.
  26  *
  27  */
  28
  29 #include "kernel/log.h"
  30 #include "libs/sha1/sha1.h"
  31 #include "ast.h"
  32
  33 #include <sstream>
  34 #include <stdarg.h>
  35 #include <assert.h>
  36
  37 using namespace AST;
  38 using namespace AST_INTERNAL;
  39
  40 // instanciate global variables (public API)
  41 namespace AST {
  42         std::string current_filename;
  43         void (*set_line_num)(int) = NULL;
  44         int (*get_line_num)() = NULL;
  45 }
  46
  47 // instanciate global variables (private API)
  48 namespace AST_INTERNAL {
  49         bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt;
  50         AstNode *current_ast, *current_ast_mod;
  51         std::map<std::string, AstNode*> current_scope;
  52         RTLIL::SigSpec *genRTLIL_subst_from = NULL;
  53         RTLIL::SigSpec *genRTLIL_subst_to = NULL;
  54         RTLIL::SigSpec ignoreThisSignalsInInitial;
  55         AstNode *current_top_block, *current_block, *current_block_child;
  56         AstModule *current_module;
  57 }
  58
  59 // convert node types to string
  60 std::string AST::type2str(AstNodeType type)
  61 {
  62         switch (type)
  63         {
  64 #define X(_item) case _item: return #_item;
  65         X(AST_NONE)
  66         X(AST_DESIGN)
  67         X(AST_MODULE)
  68         X(AST_TASK)
  69         X(AST_FUNCTION)
  70         X(AST_WIRE)
  71         X(AST_MEMORY)
  72         X(AST_AUTOWIRE)
  73         X(AST_PARAMETER)
  74         X(AST_LOCALPARAM)
  75         X(AST_DEFPARAM)
  76         X(AST_PARASET)
  77         X(AST_ARGUMENT)
  78         X(AST_RANGE)
  79         X(AST_CONSTANT)
  80         X(AST_CELLTYPE)
  81         X(AST_IDENTIFIER)
  82         X(AST_PREFIX)
  83         X(AST_FCALL)
  84         X(AST_TO_SIGNED)
  85         X(AST_TO_UNSIGNED)
  86         X(AST_CONCAT)
  87         X(AST_REPLICATE)
  88         X(AST_BIT_NOT)
  89         X(AST_BIT_AND)
  90         X(AST_BIT_OR)
  91         X(AST_BIT_XOR)
  92         X(AST_BIT_XNOR)
  93         X(AST_REDUCE_AND)
  94         X(AST_REDUCE_OR)
  95         X(AST_REDUCE_XOR)
  96         X(AST_REDUCE_XNOR)
  97         X(AST_REDUCE_BOOL)
  98         X(AST_SHIFT_LEFT)
  99         X(AST_SHIFT_RIGHT)
 100         X(AST_SHIFT_SLEFT)
 101         X(AST_SHIFT_SRIGHT)
 102         X(AST_LT)
 103         X(AST_LE)
 104         X(AST_EQ)
 105         X(AST_NE)
 106         X(AST_GE)
 107         X(AST_GT)
 108         X(AST_ADD)
 109         X(AST_SUB)
 110         X(AST_MUL)
 111         X(AST_DIV)
 112         X(AST_MOD)
 113         X(AST_POW)
 114         X(AST_POS)
 115         X(AST_NEG)
 116         X(AST_LOGIC_AND)
 117         X(AST_LOGIC_OR)
 118         X(AST_LOGIC_NOT)
 119         X(AST_TERNARY)
 120         X(AST_MEMRD)
 121         X(AST_MEMWR)
 122         X(AST_TCALL)
 123         X(AST_ASSIGN)
 124         X(AST_CELL)
 125         X(AST_PRIMITIVE)
 126         X(AST_ALWAYS)
 127         X(AST_INITIAL)
 128         X(AST_BLOCK)
 129         X(AST_ASSIGN_EQ)
 130         X(AST_ASSIGN_LE)
 131         X(AST_CASE)
 132         X(AST_COND)
 133         X(AST_DEFAULT)
 134         X(AST_FOR)
 135         X(AST_GENVAR)
 136         X(AST_GENFOR)
 137         X(AST_GENIF)
 138         X(AST_GENBLOCK)
 139         X(AST_POSEDGE)
 140         X(AST_NEGEDGE)
 141         X(AST_EDGE)
 142 #undef X
 143         default:
 144                 log_abort();
 145         }
 146 }
 147
 148 // check if attribute exists and has non-zero value
 149 bool AstNode::get_bool_attribute(RTLIL::IdString id)
 150 {
 151         if (attributes.count(id) == 0)
 152                 return false;
 153
 154         AstNode *attr = attributes.at(id);
 155         if (attr->type != AST_CONSTANT)
 156                 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 157                                 id.c_str(), attr->filename.c_str(), attr->linenum);
 158
 159         return attr->integer != 0;
 160 }
 161
 162 // create new node (AstNode constructor)
 163 // (the optional child arguments make it easier to create AST trees)
 164 AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
 165 {
 166         this->type = type;
 167         filename = current_filename;
 168         linenum = get_line_num();
 169         is_input = false;
 170         is_output = false;
 171         is_reg = false;
 172         is_signed = false;
 173         range_valid = false;
 174         port_id = 0;
 175         range_left = -1;
 176         range_right = 0;
 177         integer = 0;
 178         id2ast = NULL;
 179
 180         if (child1)
 181                 children.push_back(child1);
 182         if (child2)
 183                 children.push_back(child2);
 184 }
 185
 186 // create a (deep recursive) copy of a node
 187 AstNode *AstNode::clone()
 188 {
 189         AstNode *that = new AstNode;
 190         *that = *this;
 191         for (auto &it : that->children)
 192                 it = it->clone();
 193         for (auto &it : that->attributes)
 194                 it.second = it.second->clone();
 195         return that;
 196 }
 197
 198 // create a (deep recursive) copy of a node use 'other' as target root node
 199 void AstNode::cloneInto(AstNode *other)
 200 {
 201         AstNode *tmp = clone();
 202         other->delete_children();
 203         *other = *tmp;
 204         tmp->children.clear();
 205         tmp->attributes.clear();
 206         delete tmp;
 207 }
 208
 209 // delete all children in this node
 210 void AstNode::delete_children()
 211 {
 212         for (auto &it : children)
 213                 delete it;
 214         children.clear();
 215
 216         for (auto &it : attributes)
 217                 delete it.second;
 218         attributes.clear();
 219 }
 220
 221 // AstNode destructor
 222 AstNode::~AstNode()
 223 {
 224         delete_children();
 225 }
 226
 227 // create a nice text representation of the node
 228 // (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
 229 void AstNode::dumpAst(FILE *f, std::string indent)
 230 {
 231         if (f == NULL) {
 232                 for (auto f : log_files)
 233                         dumpAst(f, indent);
 234                 return;
 235         }
 236
 237         std::string type_name = type2str(type);
 238         fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
 239         if (!str.empty())
 240                 fprintf(f, " str='%s'", str.c_str());
 241         if (!bits.empty()) {
 242                 fprintf(f, " bits='");
 243                 for (size_t i = bits.size(); i > 0; i--)
 244                         fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
 245                                         bits[i-1] == RTLIL::S1 ? '1' :
 246                                         bits[i-1] == RTLIL::Sx ? 'x' :
 247                                         bits[i-1] == RTLIL::Sz ? 'z' : '?');
 248                 fprintf(f, "'(%zd)", bits.size());
 249         }
 250         if (is_input)
 251                 fprintf(f, " input");
 252         if (is_output)
 253                 fprintf(f, " output");
 254         if (is_reg)
 255                 fprintf(f, " reg");
 256         if (is_signed)
 257                 fprintf(f, " signed");
 258         if (port_id > 0)
 259                 fprintf(f, " port=%d", port_id);
 260         if (range_valid || range_left != -1 || range_right != 0)
 261                 fprintf(f, " range=[%d:%d]%s", range_left, range_right, range_valid ? "" : "!");
 262         if (integer != 0)
 263                 fprintf(f, " int=%u", (int)integer);
 264         fprintf(f, "\n");
 265
 266         for (size_t i = 0; i < children.size(); i++)
 267                 children[i]->dumpAst(f, indent + "  ");
 268 }
 269
 270 // helper function for AstNode::dumpVlog()
 271 static std::string id2vl(std::string txt)
 272 {
 273         if (txt.size() > 1 && txt[0] == '\\')
 274                 txt = txt.substr(1);
 275         for (size_t i = 0; i < txt.size(); i++) {
 276                 if ('A' <= txt[i] && txt[i] <= 'Z') continue;
 277                 if ('a' <= txt[i] && txt[i] <= 'z') continue;
 278                 if ('0' <= txt[i] && txt[i] <= '9') continue;
 279                 if (txt[i] == '_') continue;
 280                 txt = "\\" + txt + " ";
 281                 break;
 282         }
 283         return txt;
 284 }
 285
 286 // dump AST node as verilog pseudo-code
 287 void AstNode::dumpVlog(FILE *f, std::string indent)
 288 {
 289         bool first = true;
 290         std::string txt;
 291         std::vector<AstNode*> rem_children1, rem_children2;
 292
 293         if (f == NULL) {
 294                 for (auto f : log_files)
 295                         dumpVlog(f, indent);
 296                 return;
 297         }
 298
 299         switch (type)
 300         {
 301         case AST_MODULE:
 302                 fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
 303                 for (auto child : children)
 304                         if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
 305                                 fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
 306                                 first = false;
 307                         }
 308                 fprintf(f, ");\n");
 309
 310                 for (auto child : children)
 311                         if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
 312                                 child->dumpVlog(f, indent + "  ");
 313                         else
 314                                 rem_children1.push_back(child);
 315
 316                 for (auto child : rem_children1)
 317                         if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
 318                                 child->dumpVlog(f, indent + "  ");
 319                         else
 320                                 rem_children2.push_back(child);
 321                 rem_children1.clear();
 322
 323                 for (auto child : rem_children2)
 324                         if (child->type == AST_TASK || child->type == AST_FUNCTION)
 325                                 child->dumpVlog(f, indent + "  ");
 326                         else
 327                                 rem_children1.push_back(child);
 328                 rem_children2.clear();
 329
 330                 for (auto child : rem_children1)
 331                         child->dumpVlog(f, indent + "  ");
 332                 rem_children1.clear();
 333
 334                 fprintf(f, "%s" "endmodule\n", indent.c_str());
 335                 break;
 336
 337         case AST_WIRE:
 338                 if (is_input && is_output)
 339                         fprintf(f, "%s" "inout", indent.c_str());
 340                 else if (is_input)
 341                         fprintf(f, "%s" "input", indent.c_str());
 342                 else if (is_output)
 343                         fprintf(f, "%s" "output", indent.c_str());
 344                 else if (!is_reg)
 345                         fprintf(f, "%s" "wire", indent.c_str());
 346                 if (is_reg)
 347                         fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
 348                 if (is_signed)
 349                         fprintf(f, " signed");
 350                 for (auto child : children) {
 351                         fprintf(f, " ");
 352                         child->dumpVlog(f, "");
 353                 }
 354                 fprintf(f, " %s", id2vl(str).c_str());
 355                 fprintf(f, ";\n");
 356                 break;
 357
 358         case AST_MEMORY:
 359                 fprintf(f, "%s" "memory", indent.c_str());
 360                 if (is_signed)
 361                         fprintf(f, " signed");
 362                 for (auto child : children) {
 363                         fprintf(f, " ");
 364                         child->dumpVlog(f, "");
 365                         if (first)
 366                                 fprintf(f, " %s", id2vl(str).c_str());
 367                         first = false;
 368                 }
 369                 fprintf(f, ";\n");
 370                 break;
 371
 372         case AST_RANGE:
 373                 if (range_valid)
 374                         fprintf(f, "[%d:%d]", range_left, range_right);
 375                 else {
 376                         for (auto child : children) {
 377                                 fprintf(f, "%c", first ? '[' : ':');
 378                                 child->dumpVlog(f, "");
 379                                 first = false;
 380                         }
 381                         fprintf(f, "]");
 382                 }
 383                 break;
 384
 385         case AST_ALWAYS:
 386                 fprintf(f, "%s" "always @(", indent.c_str());
 387                 for (auto child : children) {
 388                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 389                                 continue;
 390                         if (!first)
 391                                 fprintf(f, ", ");
 392                         child->dumpVlog(f, "");
 393                         first = false;
 394                 }
 395                 fprintf(f, ")\n");
 396                 for (auto child : children) {
 397                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 398                                 child->dumpVlog(f, indent + "  ");
 399                 }
 400                 break;
 401
 402         case AST_INITIAL:
 403                 fprintf(f, "%s" "initial\n", indent.c_str());
 404                 for (auto child : children) {
 405                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 406                                 child->dumpVlog(f, indent + "  ");
 407                 }
 408                 break;
 409
 410         case AST_POSEDGE:
 411         case AST_NEGEDGE:
 412         case AST_EDGE:
 413                 if (type == AST_POSEDGE)
 414                         fprintf(f, "posedge ");
 415                 if (type == AST_NEGEDGE)
 416                         fprintf(f, "negedge ");
 417                 for (auto child : children)
 418                         child->dumpVlog(f, "");
 419                 break;
 420
 421         case AST_IDENTIFIER:
 422                 fprintf(f, "%s", id2vl(str).c_str());
 423                 for (auto child : children)
 424                         child->dumpVlog(f, "");
 425                 break;
 426
 427         case AST_CONSTANT:
 428                 if (!str.empty())
 429                         fprintf(f, "\"%s\"", str.c_str());
 430                 else if (bits.size() == 32)
 431                         fprintf(f, "%d", RTLIL::Const(bits).as_int());
 432                 else
 433                         fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
 434                 break;
 435
 436         case AST_BLOCK:
 437                 if (children.size() == 1) {
 438                         children[0]->dumpVlog(f, indent);
 439                 } else {
 440                         fprintf(f, "%s" "begin\n", indent.c_str());
 441                         for (auto child : children)
 442                                 child->dumpVlog(f, indent + "  ");
 443                         fprintf(f, "%s" "end\n", indent.c_str());
 444                 }
 445                 break;
 446
 447         case AST_CASE:
 448                 fprintf(f, "%s" "case (", indent.c_str());
 449                 children[0]->dumpVlog(f, "");
 450                 fprintf(f, ")\n");
 451                 for (size_t i = 1; i < children.size(); i++) {
 452                         AstNode *child = children[i];
 453                         child->dumpVlog(f, indent + "  ");
 454                 }
 455                 fprintf(f, "%s" "endcase\n", indent.c_str());
 456                 break;
 457
 458         case AST_COND:
 459                 for (auto child : children) {
 460                         if (child->type == AST_BLOCK) {
 461                                 fprintf(f, ":\n");
 462                                 child->dumpVlog(f, indent + "  ");
 463                                 first = true;
 464                         } else {
 465                                 fprintf(f, "%s", first ? indent.c_str() : ", ");
 466                                 if (child->type == AST_DEFAULT)
 467                                         fprintf(f, "default");
 468                                 else
 469                                         child->dumpVlog(f, "");
 470                                 first = false;
 471                         }
 472                 }
 473                 break;
 474
 475         case AST_ASSIGN_EQ:
 476         case AST_ASSIGN_LE:
 477                 fprintf(f, "%s", indent.c_str());
 478                 children[0]->dumpVlog(f, "");
 479                 fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
 480                 children[1]->dumpVlog(f, "");
 481                 fprintf(f, ";\n");
 482                 break;
 483
 484         case AST_CONCAT:
 485                 fprintf(f, "{");
 486                 for (auto child : children) {
 487                         if (!first)
 488                                 fprintf(f, ", ");
 489                         child->dumpVlog(f, "");
 490                         first = false;
 491                 }
 492                 fprintf(f, "}");
 493                 break;
 494
 495         case AST_REPLICATE:
 496                 fprintf(f, "{");
 497                 children[0]->dumpVlog(f, "");
 498                 fprintf(f, "{");
 499                 children[1]->dumpVlog(f, "");
 500                 fprintf(f, "}}");
 501                 break;
 502
 503         if (0) { case AST_BIT_NOT:     txt = "~";  }
 504         if (0) { case AST_REDUCE_AND:  txt = "&";  }
 505         if (0) { case AST_REDUCE_OR:   txt = "|";  }
 506         if (0) { case AST_REDUCE_XOR:  txt = "^";  }
 507         if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
 508         if (0) { case AST_REDUCE_BOOL: txt = "|";  }
 509         if (0) { case AST_POS:         txt = "+";  }
 510         if (0) { case AST_NEG:         txt = "-";  }
 511         if (0) { case AST_LOGIC_NOT:   txt = "!";  }
 512                 fprintf(f, "%s(", txt.c_str());
 513                 children[0]->dumpVlog(f, "");
 514                 fprintf(f, ")");
 515                 break;
 516
 517         if (0) { case AST_BIT_AND:      txt = "&";   }
 518         if (0) { case AST_BIT_OR:       txt = "|";   }
 519         if (0) { case AST_BIT_XOR:      txt = "^";   }
 520         if (0) { case AST_BIT_XNOR:     txt = "~^";  }
 521         if (0) { case AST_SHIFT_LEFT:   txt = "<<";  }
 522         if (0) { case AST_SHIFT_RIGHT:  txt = ">>";  }
 523         if (0) { case AST_SHIFT_SLEFT:  txt = "<<<"; }
 524         if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
 525         if (0) { case AST_LT:           txt = "<";   }
 526         if (0) { case AST_LE:           txt = "<=";  }
 527         if (0) { case AST_EQ:           txt = "==";  }
 528         if (0) { case AST_NE:           txt = "!=";  }
 529         if (0) { case AST_GE:           txt = ">=";  }
 530         if (0) { case AST_GT:           txt = ">";   }
 531         if (0) { case AST_ADD:          txt = "+";   }
 532         if (0) { case AST_SUB:          txt = "-";   }
 533         if (0) { case AST_MUL:          txt = "*";   }
 534         if (0) { case AST_DIV:          txt = "/";   }
 535         if (0) { case AST_MOD:          txt = "%";   }
 536         if (0) { case AST_POW:          txt = "**";  }
 537         if (0) { case AST_LOGIC_AND:    txt = "&&";  }
 538         if (0) { case AST_LOGIC_OR:     txt = "||";  }
 539                 fprintf(f, "(");
 540                 children[0]->dumpVlog(f, "");
 541                 fprintf(f, ")%s(", txt.c_str());
 542                 children[1]->dumpVlog(f, "");
 543                 fprintf(f, ")");
 544                 break;
 545
 546         case AST_TERNARY:
 547                 fprintf(f, "(");
 548                 children[0]->dumpVlog(f, "");
 549                 fprintf(f, ") ? (");
 550                 children[1]->dumpVlog(f, "");
 551                 fprintf(f, ") : (");
 552                 children[2]->dumpVlog(f, "");
 553                 fprintf(f, ")");
 554                 break;
 555
 556         default:
 557                 std::string type_name = type2str(type);
 558                 fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
 559                 // dumpAst(f, indent, NULL);
 560         }
 561 }
 562
 563 // check if two AST nodes are identical
 564 bool AstNode::operator==(const AstNode &other) const
 565 {
 566         if (type != other.type)
 567                 return false;
 568         if (children.size() != other.children.size())
 569                 return false;
 570         if (str != other.str)
 571                 return false;
 572         if (bits != other.bits)
 573                 return false;
 574         if (is_input != other.is_input)
 575                 return false;
 576         if (is_output != other.is_output)
 577                 return false;
 578         if (is_reg != other.is_reg)
 579                 return false;
 580         if (is_signed != other.is_signed)
 581                 return false;
 582         if (range_valid != other.range_valid)
 583                 return false;
 584         if (port_id != other.port_id)
 585                 return false;
 586         if (range_left != other.range_left)
 587                 return false;
 588         if (range_right != other.range_right)
 589                 return false;
 590         if (integer != other.integer)
 591                 return false;
 592         for (size_t i = 0; i < children.size(); i++)
 593                 if (*children[i] != *other.children[i])
 594                         return false;
 595         return true;
 596 }
 597
 598 // check if two AST nodes are not identical
 599 bool AstNode::operator!=(const AstNode &other) const
 600 {
 601         return !(*this == other);
 602 }
 603
 604 // check if this AST contains the given node
 605 bool AstNode::contains(const AstNode *other) const
 606 {
 607         if (this == other)
 608                 return true;
 609         for (auto child : children)
 610                 if (child->contains(other))
 611                         return true;
 612         return false;
 613 }
 614
 615 // create an AST node for a constant (using a 32 bit int as value)
 616 AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
 617 {
 618         AstNode *node = new AstNode(AST_CONSTANT);
 619         node->integer = v;
 620         node->is_signed = is_signed;
 621         for (int i = 0; i < width; i++) {
 622                 node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
 623                 v = v >> 1;
 624         }
 625         node->range_valid = true;
 626         node->range_left = width-1;
 627         node->range_right = 0;
 628         return node;
 629 }
 630
 631 // create an AST node for a constant (using a bit vector as value)
 632 AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
 633 {
 634         AstNode *node = new AstNode(AST_CONSTANT);
 635         node->is_signed = is_signed;
 636         node->bits = v;
 637         for (size_t i = 0; i < 32; i++) {
 638                 if (i < node->bits.size())
 639                         node->integer |= (node->bits[i] == RTLIL::S1) << i;
 640                 else if (is_signed)
 641                         node->integer |= (node->bits.back() == RTLIL::S1) << i;
 642         }
 643         node->range_valid = true;
 644         node->range_left = node->bits.size()-1;
 645         node->range_right = 0;
 646         return node;
 647 }
 648
 649 RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
 650 {
 651         std::vector<RTLIL::State> bits = this->bits;
 652         if (width >= 0 && width < int(bits.size()))
 653                 bits.resize(width);
 654         if (width >= 0 && width > int(bits.size())) {
 655                 RTLIL::State extbit = RTLIL::State::S0;
 656                 if (is_signed && !bits.empty())
 657                         extbit = bits.back();
 658                 while (width > int(bits.size()))
 659                         bits.push_back(extbit);
 660         }
 661         return RTLIL::Const(bits);
 662 }
 663
 664 RTLIL::Const AstNode::bitsAsConst(int width)
 665 {
 666         return bitsAsConst(width, is_signed);
 667 }
 668
 669 // create a new AstModule from an AST_MODULE AST node
 670 static AstModule* process_module(AstNode *ast)
 671 {
 672         assert(ast->type == AST_MODULE);
 673         log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
 674
 675         current_module = new AstModule;
 676         current_module->ast = NULL;
 677         current_module->name = ast->str;
 678         current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
 679
 680         current_ast_mod = ast;
 681         AstNode *ast_before_simplify = ast->clone();
 682
 683         if (flag_dump_ast1) {
 684                 log("Dumping verilog AST before simplification:\n");
 685                 ast->dumpAst(NULL, "    ");
 686                 log("--- END OF AST DUMP ---\n");
 687         }
 688
 689         while (ast->simplify(!flag_noopt, false, false, 0, -1, false)) { }
 690
 691         if (flag_dump_ast2) {
 692                 log("Dumping verilog AST after simplification:\n");
 693                 ast->dumpAst(NULL, "    ");
 694                 log("--- END OF AST DUMP ---\n");
 695         }
 696
 697         if (flag_dump_vlog) {
 698                 log("Dumping verilog AST (as requested by dump_vlog option):\n");
 699                 ast->dumpVlog(NULL, "    ");
 700                 log("--- END OF AST DUMP ---\n");
 701         }
 702
 703         if (flag_lib) {
 704                 std::vector<AstNode*> new_children;
 705                 for (auto child : ast->children) {
 706                         if (child->type == AST_WIRE && (child->is_input || child->is_output))
 707                                 new_children.push_back(child);
 708                         else
 709                                 delete child;
 710                 }
 711                 ast->children.swap(new_children);
 712                 ast->attributes["\\placeholder"] = AstNode::mkconst_int(1, false);
 713         }
 714
 715         ignoreThisSignalsInInitial = RTLIL::SigSpec();
 716
 717         for (auto &attr : ast->attributes) {
 718                 if (attr.second->type != AST_CONSTANT)
 719                         log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 720                                         attr.first.c_str(), ast->filename.c_str(), ast->linenum);
 721                 current_module->attributes[attr.first].str = attr.second->str;
 722                 current_module->attributes[attr.first].bits = attr.second->bits;
 723         }
 724         for (size_t i = 0; i < ast->children.size(); i++) {
 725                 AstNode *node = ast->children[i];
 726                 if (node->type == AST_WIRE || node->type == AST_MEMORY)
 727                         node->genRTLIL();
 728         }
 729         for (size_t i = 0; i < ast->children.size(); i++) {
 730                 AstNode *node = ast->children[i];
 731                 if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
 732                         node->genRTLIL();
 733         }
 734
 735         ignoreThisSignalsInInitial.sort_and_unify();
 736
 737         for (size_t i = 0; i < ast->children.size(); i++) {
 738                 AstNode *node = ast->children[i];
 739                 if (node->type == AST_INITIAL)
 740                         node->genRTLIL();
 741         }
 742
 743         ignoreThisSignalsInInitial = RTLIL::SigSpec();
 744
 745         current_module->ast = ast_before_simplify;
 746         current_module->nolatches = flag_nolatches;
 747         current_module->nomem2reg = flag_nomem2reg;
 748         current_module->mem2reg = flag_mem2reg;
 749         current_module->lib = flag_lib;
 750         current_module->noopt = flag_noopt;
 751         return current_module;
 752 }
 753
 754 // create AstModule instances for all modules in the AST tree and add them to 'design'
 755 void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt)
 756 {
 757         current_ast = ast;
 758         flag_dump_ast1 = dump_ast1;
 759         flag_dump_ast2 = dump_ast2;
 760         flag_dump_vlog = dump_vlog;
 761         flag_nolatches = nolatches;
 762         flag_nomem2reg = nomem2reg;
 763         flag_mem2reg = mem2reg;
 764         flag_lib = lib;
 765         flag_noopt = noopt;
 766
 767         assert(current_ast->type == AST_DESIGN);
 768         for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
 769                 if (design->modules.count((*it)->str) != 0)
 770                         log_error("Re-definition of module `%s' at %s:%d!\n",
 771                                         (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 772                 design->modules[(*it)->str] = process_module(*it);
 773         }
 774 }
 775
 776 // AstModule destructor
 777 AstModule::~AstModule()
 778 {
 779         if (ast != NULL)
 780                 delete ast;
 781 }
 782
 783 // create a new parametric module (when needed) and return the name of the generated module
 784 RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
 785 {
 786         log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", name.c_str());
 787
 788         current_ast = NULL;
 789         flag_dump_ast1 = false;
 790         flag_dump_ast2 = false;
 791         flag_dump_vlog = false;
 792         flag_nolatches = nolatches;
 793         flag_nomem2reg = nomem2reg;
 794         flag_mem2reg = mem2reg;
 795         flag_lib = lib;
 796         flag_noopt = noopt;
 797         use_internal_line_num();
 798
 799         std::string para_info;
 800         std::vector<unsigned char> hash_data;
 801         hash_data.insert(hash_data.end(), name.begin(), name.end());
 802         hash_data.push_back(0);
 803
 804         AstNode *new_ast = ast->clone();
 805
 806         int para_counter = 0;
 807         for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
 808                 AstNode *child = *it;
 809                 if (child->type != AST_PARAMETER)
 810                         continue;
 811                 para_counter++;
 812                 std::string para_id = child->str;
 813                 if (parameters.count(para_id) > 0) {
 814                         log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
 815         rewrite_parameter:
 816                         para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 817                         delete child->children.at(0);
 818                         child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, child->is_signed);
 819                         hash_data.insert(hash_data.end(), child->str.begin(), child->str.end());
 820                         hash_data.push_back(0);
 821                         hash_data.insert(hash_data.end(), parameters[para_id].bits.begin(), parameters[para_id].bits.end());
 822                         hash_data.push_back(0xff);
 823                         parameters.erase(para_id);
 824                         continue;
 825                 }
 826                 para_id = stringf("$%d", para_counter);
 827                 if (parameters.count(para_id) > 0) {
 828                         log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
 829                         goto rewrite_parameter;
 830                 }
 831         }
 832         if (parameters.size() > 0)
 833                 log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), name.c_str());
 834
 835         std::string modname;
 836
 837         if (para_info.size() > 60)
 838         {
 839                 unsigned char hash[20];
 840                 unsigned char *hash_data2 = new unsigned char[hash_data.size()];
 841                 for (size_t i = 0; i < hash_data.size(); i++)
 842                         hash_data2[i] = hash_data[i];
 843                 sha1::calc(hash_data2, hash_data.size(), hash);
 844                 delete[] hash_data2;
 845
 846                 char hexstring[41];
 847                 sha1::toHexString(hash, hexstring);
 848
 849                 modname = "$paramod$" + std::string(hexstring) + name;
 850         }
 851         else
 852         {
 853                 modname = "$paramod" + name + para_info;
 854         }
 855
 856         if (design->modules.count(modname) == 0) {
 857                 new_ast->str = modname;
 858                 design->modules[modname] = process_module(new_ast);
 859         } else {
 860                 log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
 861         }
 862
 863         delete new_ast;
 864         return modname;
 865 }
 866
 867 // recompile a module from AST with updated widths for auto-wires
 868 // (auto-wires are wires that are used but not declared an thus have an automatically determined width)
 869 void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes)
 870 {
 871         log_header("Executing AST frontend in update_auto_wires mode using pre-parsed AST for module `%s'.\n", name.c_str());
 872
 873         current_ast = NULL;
 874         flag_dump_ast1 = false;
 875         flag_dump_ast2 = false;
 876         flag_dump_vlog = false;
 877         flag_nolatches = nolatches;
 878         flag_nomem2reg = nomem2reg;
 879         flag_mem2reg = mem2reg;
 880         flag_lib = lib;
 881         flag_noopt = noopt;
 882         use_internal_line_num();
 883
 884         for (auto it = auto_sizes.begin(); it != auto_sizes.end(); it++) {
 885                 log("Adding extra wire declaration to AST: wire [%d:0] %s\n", it->second - 1, it->first.c_str());
 886                 AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(it->second - 1, true), AstNode::mkconst_int(0, true)));
 887                 wire->str = it->first;
 888                 ast->children.insert(ast->children.begin(), wire);
 889         }
 890
 891         AstModule *newmod =  process_module(ast);
 892
 893         delete ast;
 894         ast = newmod->ast;
 895         newmod->ast = NULL;
 896
 897         wires.swap(newmod->wires);
 898         cells.swap(newmod->cells);
 899         processes.swap(newmod->processes);
 900         connections.swap(newmod->connections);
 901         attributes.swap(newmod->attributes);
 902         delete newmod;
 903 }
 904
 905 RTLIL::Module *AstModule::clone() const
 906 {
 907         AstModule *new_mod = new AstModule;
 908         cloneInto(new_mod);
 909
 910         new_mod->ast = ast->clone();
 911         new_mod->nolatches = nolatches;
 912         new_mod->nomem2reg = nomem2reg;
 913         new_mod->mem2reg = mem2reg;
 914         new_mod->lib = lib;
 915         new_mod->noopt = noopt;
 916
 917         return new_mod;
 918 }
 919
 920 // internal dummy line number callbacks
 921 namespace {
 922         int internal_line_num;
 923         void internal_set_line_num(int n) {
 924                 internal_line_num = n;
 925         }
 926         int internal_get_line_num() {
 927                 return internal_line_num;
 928         }
 929 }
 930
 931 // use internal dummy line number callbacks
 932 void AST::use_internal_line_num()
 933 {
 934         set_line_num = &internal_set_line_num;
 935         get_line_num = &internal_get_line_num;
 936 }
 937