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[yosys.git] / frontends / ast / ast.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/yosys.h"
30 #include "libs/sha1/sha1.h"
31 #include "ast.h"
32
33 YOSYS_NAMESPACE_BEGIN
34
35 using namespace AST;
36 using namespace AST_INTERNAL;
37
38 // instanciate global variables (public API)
39 namespace AST {
40 std::string current_filename;
41 void (*set_line_num)(int) = NULL;
42 int (*get_line_num)() = NULL;
43 }
44
45 // instanciate global variables (private API)
46 namespace AST_INTERNAL {
47 bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
48 bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
49 AstNode *current_ast, *current_ast_mod;
50 std::map<std::string, AstNode*> current_scope;
51 const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
52 RTLIL::SigSpec ignoreThisSignalsInInitial;
53 AstNode *current_always, *current_top_block, *current_block, *current_block_child;
54 AstModule *current_module;
55 bool current_always_clocked;
56 }
57
58 // convert node types to string
59 std::string AST::type2str(AstNodeType type)
60 {
61 switch (type)
62 {
63 #define X(_item) case _item: return #_item;
64 X(AST_NONE)
65 X(AST_DESIGN)
66 X(AST_MODULE)
67 X(AST_TASK)
68 X(AST_FUNCTION)
69 X(AST_DPI_FUNCTION)
70 X(AST_WIRE)
71 X(AST_MEMORY)
72 X(AST_AUTOWIRE)
73 X(AST_PARAMETER)
74 X(AST_LOCALPARAM)
75 X(AST_DEFPARAM)
76 X(AST_PARASET)
77 X(AST_ARGUMENT)
78 X(AST_RANGE)
79 X(AST_MULTIRANGE)
80 X(AST_CONSTANT)
81 X(AST_REALVALUE)
82 X(AST_CELLTYPE)
83 X(AST_IDENTIFIER)
84 X(AST_PREFIX)
85 X(AST_ASSERT)
86 X(AST_ASSUME)
87 X(AST_FCALL)
88 X(AST_TO_BITS)
89 X(AST_TO_SIGNED)
90 X(AST_TO_UNSIGNED)
91 X(AST_CONCAT)
92 X(AST_REPLICATE)
93 X(AST_BIT_NOT)
94 X(AST_BIT_AND)
95 X(AST_BIT_OR)
96 X(AST_BIT_XOR)
97 X(AST_BIT_XNOR)
98 X(AST_REDUCE_AND)
99 X(AST_REDUCE_OR)
100 X(AST_REDUCE_XOR)
101 X(AST_REDUCE_XNOR)
102 X(AST_REDUCE_BOOL)
103 X(AST_SHIFT_LEFT)
104 X(AST_SHIFT_RIGHT)
105 X(AST_SHIFT_SLEFT)
106 X(AST_SHIFT_SRIGHT)
107 X(AST_LT)
108 X(AST_LE)
109 X(AST_EQ)
110 X(AST_NE)
111 X(AST_EQX)
112 X(AST_NEX)
113 X(AST_GE)
114 X(AST_GT)
115 X(AST_ADD)
116 X(AST_SUB)
117 X(AST_MUL)
118 X(AST_DIV)
119 X(AST_MOD)
120 X(AST_POW)
121 X(AST_POS)
122 X(AST_NEG)
123 X(AST_LOGIC_AND)
124 X(AST_LOGIC_OR)
125 X(AST_LOGIC_NOT)
126 X(AST_TERNARY)
127 X(AST_MEMRD)
128 X(AST_MEMWR)
129 X(AST_MEMINIT)
130 X(AST_TCALL)
131 X(AST_ASSIGN)
132 X(AST_CELL)
133 X(AST_PRIMITIVE)
134 X(AST_CELLARRAY)
135 X(AST_ALWAYS)
136 X(AST_INITIAL)
137 X(AST_BLOCK)
138 X(AST_ASSIGN_EQ)
139 X(AST_ASSIGN_LE)
140 X(AST_CASE)
141 X(AST_COND)
142 X(AST_CONDX)
143 X(AST_CONDZ)
144 X(AST_DEFAULT)
145 X(AST_FOR)
146 X(AST_WHILE)
147 X(AST_REPEAT)
148 X(AST_GENVAR)
149 X(AST_GENFOR)
150 X(AST_GENIF)
151 X(AST_GENCASE)
152 X(AST_GENBLOCK)
153 X(AST_POSEDGE)
154 X(AST_NEGEDGE)
155 X(AST_EDGE)
156 X(AST_PACKAGE)
157 #undef X
158 default:
159 log_abort();
160 }
161 }
162
163 // check if attribute exists and has non-zero value
164 bool AstNode::get_bool_attribute(RTLIL::IdString id)
165 {
166 if (attributes.count(id) == 0)
167 return false;
168
169 AstNode *attr = attributes.at(id);
170 if (attr->type != AST_CONSTANT)
171 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
172 id.c_str(), attr->filename.c_str(), attr->linenum);
173
174 return attr->integer != 0;
175 }
176
177 // create new node (AstNode constructor)
178 // (the optional child arguments make it easier to create AST trees)
179 AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *child3)
180 {
181 static unsigned int hashidx_count = 123456789;
182 hashidx_count = mkhash_xorshift(hashidx_count);
183 hashidx_ = hashidx_count;
184
185 this->type = type;
186 filename = current_filename;
187 linenum = get_line_num();
188 is_input = false;
189 is_output = false;
190 is_reg = false;
191 is_signed = false;
192 is_string = false;
193 range_valid = false;
194 range_swapped = false;
195 port_id = 0;
196 range_left = -1;
197 range_right = 0;
198 integer = 0;
199 realvalue = 0;
200 id2ast = NULL;
201 basic_prep = false;
202
203 if (child1)
204 children.push_back(child1);
205 if (child2)
206 children.push_back(child2);
207 if (child3)
208 children.push_back(child3);
209 }
210
211 // create a (deep recursive) copy of a node
212 AstNode *AstNode::clone()
213 {
214 AstNode *that = new AstNode;
215 *that = *this;
216 for (auto &it : that->children)
217 it = it->clone();
218 for (auto &it : that->attributes)
219 it.second = it.second->clone();
220 return that;
221 }
222
223 // create a (deep recursive) copy of a node use 'other' as target root node
224 void AstNode::cloneInto(AstNode *other)
225 {
226 AstNode *tmp = clone();
227 other->delete_children();
228 *other = *tmp;
229 tmp->children.clear();
230 tmp->attributes.clear();
231 delete tmp;
232 }
233
234 // delete all children in this node
235 void AstNode::delete_children()
236 {
237 for (auto &it : children)
238 delete it;
239 children.clear();
240
241 for (auto &it : attributes)
242 delete it.second;
243 attributes.clear();
244 }
245
246 // AstNode destructor
247 AstNode::~AstNode()
248 {
249 delete_children();
250 }
251
252 // create a nice text representation of the node
253 // (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
254 void AstNode::dumpAst(FILE *f, std::string indent)
255 {
256 if (f == NULL) {
257 for (auto f : log_files)
258 dumpAst(f, indent);
259 return;
260 }
261
262 std::string type_name = type2str(type);
263 fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
264
265 if (id2ast)
266 fprintf(f, " [%p -> %p]", this, id2ast);
267 else
268 fprintf(f, " [%p]", this);
269
270 if (!str.empty())
271 fprintf(f, " str='%s'", str.c_str());
272 if (!bits.empty()) {
273 fprintf(f, " bits='");
274 for (size_t i = bits.size(); i > 0; i--)
275 fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
276 bits[i-1] == RTLIL::S1 ? '1' :
277 bits[i-1] == RTLIL::Sx ? 'x' :
278 bits[i-1] == RTLIL::Sz ? 'z' : '?');
279 fprintf(f, "'(%d)", GetSize(bits));
280 }
281 if (is_input)
282 fprintf(f, " input");
283 if (is_output)
284 fprintf(f, " output");
285 if (is_reg)
286 fprintf(f, " reg");
287 if (is_signed)
288 fprintf(f, " signed");
289 if (port_id > 0)
290 fprintf(f, " port=%d", port_id);
291 if (range_valid || range_left != -1 || range_right != 0)
292 fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
293 if (integer != 0)
294 fprintf(f, " int=%u", (int)integer);
295 if (realvalue != 0)
296 fprintf(f, " real=%e", realvalue);
297 if (!multirange_dimensions.empty()) {
298 fprintf(f, " multirange=[");
299 for (int v : multirange_dimensions)
300 fprintf(f, " %d", v);
301 fprintf(f, " ]");
302 }
303 fprintf(f, "\n");
304
305 for (auto &it : attributes) {
306 fprintf(f, "%s ATTR %s:\n", indent.c_str(), it.first.c_str());
307 it.second->dumpAst(f, indent + " ");
308 }
309
310 for (size_t i = 0; i < children.size(); i++)
311 children[i]->dumpAst(f, indent + " ");
312
313 fflush(f);
314 }
315
316 // helper function for AstNode::dumpVlog()
317 static std::string id2vl(std::string txt)
318 {
319 if (txt.size() > 1 && txt[0] == '\\')
320 txt = txt.substr(1);
321 for (size_t i = 0; i < txt.size(); i++) {
322 if ('A' <= txt[i] && txt[i] <= 'Z') continue;
323 if ('a' <= txt[i] && txt[i] <= 'z') continue;
324 if ('0' <= txt[i] && txt[i] <= '9') continue;
325 if (txt[i] == '_') continue;
326 txt = "\\" + txt + " ";
327 break;
328 }
329 return txt;
330 }
331
332 // dump AST node as Verilog pseudo-code
333 void AstNode::dumpVlog(FILE *f, std::string indent)
334 {
335 bool first = true;
336 std::string txt;
337 std::vector<AstNode*> rem_children1, rem_children2;
338
339 if (f == NULL) {
340 for (auto f : log_files)
341 dumpVlog(f, indent);
342 return;
343 }
344
345 for (auto &it : attributes) {
346 fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
347 it.second->dumpVlog(f, "");
348 fprintf(f, " *)%s", indent.empty() ? "" : "\n");
349 }
350
351 switch (type)
352 {
353 case AST_MODULE:
354 fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
355 for (auto child : children)
356 if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
357 fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
358 first = false;
359 }
360 fprintf(f, ");\n");
361
362 for (auto child : children)
363 if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
364 child->dumpVlog(f, indent + " ");
365 else
366 rem_children1.push_back(child);
367
368 for (auto child : rem_children1)
369 if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
370 child->dumpVlog(f, indent + " ");
371 else
372 rem_children2.push_back(child);
373 rem_children1.clear();
374
375 for (auto child : rem_children2)
376 if (child->type == AST_TASK || child->type == AST_FUNCTION)
377 child->dumpVlog(f, indent + " ");
378 else
379 rem_children1.push_back(child);
380 rem_children2.clear();
381
382 for (auto child : rem_children1)
383 child->dumpVlog(f, indent + " ");
384 rem_children1.clear();
385
386 fprintf(f, "%s" "endmodule\n", indent.c_str());
387 break;
388
389 case AST_WIRE:
390 if (is_input && is_output)
391 fprintf(f, "%s" "inout", indent.c_str());
392 else if (is_input)
393 fprintf(f, "%s" "input", indent.c_str());
394 else if (is_output)
395 fprintf(f, "%s" "output", indent.c_str());
396 else if (!is_reg)
397 fprintf(f, "%s" "wire", indent.c_str());
398 if (is_reg)
399 fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
400 if (is_signed)
401 fprintf(f, " signed");
402 for (auto child : children) {
403 fprintf(f, " ");
404 child->dumpVlog(f, "");
405 }
406 fprintf(f, " %s", id2vl(str).c_str());
407 fprintf(f, ";\n");
408 break;
409
410 case AST_MEMORY:
411 fprintf(f, "%s" "memory", indent.c_str());
412 if (is_signed)
413 fprintf(f, " signed");
414 for (auto child : children) {
415 fprintf(f, " ");
416 child->dumpVlog(f, "");
417 if (first)
418 fprintf(f, " %s", id2vl(str).c_str());
419 first = false;
420 }
421 fprintf(f, ";\n");
422 break;
423
424 case AST_RANGE:
425 if (range_valid)
426 fprintf(f, "[%d:%d]", range_left, range_right);
427 else {
428 for (auto child : children) {
429 fprintf(f, "%c", first ? '[' : ':');
430 child->dumpVlog(f, "");
431 first = false;
432 }
433 fprintf(f, "]");
434 }
435 break;
436
437 case AST_ALWAYS:
438 fprintf(f, "%s" "always @", indent.c_str());
439 for (auto child : children) {
440 if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
441 continue;
442 fprintf(f, first ? "(" : ", ");
443 child->dumpVlog(f, "");
444 first = false;
445 }
446 fprintf(f, first ? "*\n" : ")\n");
447 for (auto child : children) {
448 if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
449 child->dumpVlog(f, indent + " ");
450 }
451 break;
452
453 case AST_INITIAL:
454 fprintf(f, "%s" "initial\n", indent.c_str());
455 for (auto child : children) {
456 if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
457 child->dumpVlog(f, indent + " ");
458 }
459 break;
460
461 case AST_POSEDGE:
462 case AST_NEGEDGE:
463 case AST_EDGE:
464 if (type == AST_POSEDGE)
465 fprintf(f, "posedge ");
466 if (type == AST_NEGEDGE)
467 fprintf(f, "negedge ");
468 for (auto child : children)
469 child->dumpVlog(f, "");
470 break;
471
472 case AST_IDENTIFIER:
473 fprintf(f, "%s", id2vl(str).c_str());
474 for (auto child : children)
475 child->dumpVlog(f, "");
476 break;
477
478 case AST_CONSTANT:
479 if (!str.empty())
480 fprintf(f, "\"%s\"", str.c_str());
481 else if (bits.size() == 32)
482 fprintf(f, "%d", RTLIL::Const(bits).as_int());
483 else
484 fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
485 break;
486
487 case AST_REALVALUE:
488 fprintf(f, "%e", realvalue);
489 break;
490
491 case AST_BLOCK:
492 if (children.size() == 1) {
493 children[0]->dumpVlog(f, indent);
494 } else {
495 fprintf(f, "%s" "begin\n", indent.c_str());
496 for (auto child : children)
497 child->dumpVlog(f, indent + " ");
498 fprintf(f, "%s" "end\n", indent.c_str());
499 }
500 break;
501
502 case AST_CASE:
503 if (!children.empty() && children[0]->type == AST_CONDX)
504 fprintf(f, "%s" "casex (", indent.c_str());
505 else if (!children.empty() && children[0]->type == AST_CONDZ)
506 fprintf(f, "%s" "casez (", indent.c_str());
507 else
508 fprintf(f, "%s" "case (", indent.c_str());
509 children[0]->dumpVlog(f, "");
510 fprintf(f, ")\n");
511 for (size_t i = 1; i < children.size(); i++) {
512 AstNode *child = children[i];
513 child->dumpVlog(f, indent + " ");
514 }
515 fprintf(f, "%s" "endcase\n", indent.c_str());
516 break;
517
518 case AST_COND:
519 case AST_CONDX:
520 case AST_CONDZ:
521 for (auto child : children) {
522 if (child->type == AST_BLOCK) {
523 fprintf(f, ":\n");
524 child->dumpVlog(f, indent + " ");
525 first = true;
526 } else {
527 fprintf(f, "%s", first ? indent.c_str() : ", ");
528 if (child->type == AST_DEFAULT)
529 fprintf(f, "default");
530 else
531 child->dumpVlog(f, "");
532 first = false;
533 }
534 }
535 break;
536
537 case AST_ASSIGN:
538 fprintf(f, "%sassign ", indent.c_str());
539 children[0]->dumpVlog(f, "");
540 fprintf(f, " = ");
541 children[1]->dumpVlog(f, "");
542 fprintf(f, ";\n");
543 break;
544
545 case AST_ASSIGN_EQ:
546 case AST_ASSIGN_LE:
547 fprintf(f, "%s", indent.c_str());
548 children[0]->dumpVlog(f, "");
549 fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
550 children[1]->dumpVlog(f, "");
551 fprintf(f, ";\n");
552 break;
553
554 case AST_CONCAT:
555 fprintf(f, "{");
556 for (auto child : children) {
557 if (!first)
558 fprintf(f, ", ");
559 child->dumpVlog(f, "");
560 first = false;
561 }
562 fprintf(f, "}");
563 break;
564
565 case AST_REPLICATE:
566 fprintf(f, "{");
567 children[0]->dumpVlog(f, "");
568 fprintf(f, "{");
569 children[1]->dumpVlog(f, "");
570 fprintf(f, "}}");
571 break;
572
573 if (0) { case AST_BIT_NOT: txt = "~"; }
574 if (0) { case AST_REDUCE_AND: txt = "&"; }
575 if (0) { case AST_REDUCE_OR: txt = "|"; }
576 if (0) { case AST_REDUCE_XOR: txt = "^"; }
577 if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
578 if (0) { case AST_REDUCE_BOOL: txt = "|"; }
579 if (0) { case AST_POS: txt = "+"; }
580 if (0) { case AST_NEG: txt = "-"; }
581 if (0) { case AST_LOGIC_NOT: txt = "!"; }
582 fprintf(f, "%s(", txt.c_str());
583 children[0]->dumpVlog(f, "");
584 fprintf(f, ")");
585 break;
586
587 if (0) { case AST_BIT_AND: txt = "&"; }
588 if (0) { case AST_BIT_OR: txt = "|"; }
589 if (0) { case AST_BIT_XOR: txt = "^"; }
590 if (0) { case AST_BIT_XNOR: txt = "~^"; }
591 if (0) { case AST_SHIFT_LEFT: txt = "<<"; }
592 if (0) { case AST_SHIFT_RIGHT: txt = ">>"; }
593 if (0) { case AST_SHIFT_SLEFT: txt = "<<<"; }
594 if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
595 if (0) { case AST_LT: txt = "<"; }
596 if (0) { case AST_LE: txt = "<="; }
597 if (0) { case AST_EQ: txt = "=="; }
598 if (0) { case AST_NE: txt = "!="; }
599 if (0) { case AST_EQX: txt = "==="; }
600 if (0) { case AST_NEX: txt = "!=="; }
601 if (0) { case AST_GE: txt = ">="; }
602 if (0) { case AST_GT: txt = ">"; }
603 if (0) { case AST_ADD: txt = "+"; }
604 if (0) { case AST_SUB: txt = "-"; }
605 if (0) { case AST_MUL: txt = "*"; }
606 if (0) { case AST_DIV: txt = "/"; }
607 if (0) { case AST_MOD: txt = "%"; }
608 if (0) { case AST_POW: txt = "**"; }
609 if (0) { case AST_LOGIC_AND: txt = "&&"; }
610 if (0) { case AST_LOGIC_OR: txt = "||"; }
611 fprintf(f, "(");
612 children[0]->dumpVlog(f, "");
613 fprintf(f, ")%s(", txt.c_str());
614 children[1]->dumpVlog(f, "");
615 fprintf(f, ")");
616 break;
617
618 case AST_TERNARY:
619 fprintf(f, "(");
620 children[0]->dumpVlog(f, "");
621 fprintf(f, ") ? (");
622 children[1]->dumpVlog(f, "");
623 fprintf(f, ") : (");
624 children[2]->dumpVlog(f, "");
625 fprintf(f, ")");
626 break;
627
628 default:
629 std::string type_name = type2str(type);
630 fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
631 // dumpAst(f, indent, NULL);
632 }
633
634 fflush(f);
635 }
636
637 // check if two AST nodes are identical
638 bool AstNode::operator==(const AstNode &other) const
639 {
640 if (type != other.type)
641 return false;
642 if (children.size() != other.children.size())
643 return false;
644 if (str != other.str)
645 return false;
646 if (bits != other.bits)
647 return false;
648 if (is_input != other.is_input)
649 return false;
650 if (is_output != other.is_output)
651 return false;
652 if (is_reg != other.is_reg)
653 return false;
654 if (is_signed != other.is_signed)
655 return false;
656 if (is_string != other.is_string)
657 return false;
658 if (range_valid != other.range_valid)
659 return false;
660 if (range_swapped != other.range_swapped)
661 return false;
662 if (port_id != other.port_id)
663 return false;
664 if (range_left != other.range_left)
665 return false;
666 if (range_right != other.range_right)
667 return false;
668 if (integer != other.integer)
669 return false;
670 for (size_t i = 0; i < children.size(); i++)
671 if (*children[i] != *other.children[i])
672 return false;
673 return true;
674 }
675
676 // check if two AST nodes are not identical
677 bool AstNode::operator!=(const AstNode &other) const
678 {
679 return !(*this == other);
680 }
681
682 // check if this AST contains the given node
683 bool AstNode::contains(const AstNode *other) const
684 {
685 if (this == other)
686 return true;
687 for (auto child : children)
688 if (child->contains(other))
689 return true;
690 return false;
691 }
692
693 // create an AST node for a constant (using a 32 bit int as value)
694 AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
695 {
696 AstNode *node = new AstNode(AST_CONSTANT);
697 node->integer = v;
698 node->is_signed = is_signed;
699 for (int i = 0; i < width; i++) {
700 node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
701 v = v >> 1;
702 }
703 node->range_valid = true;
704 node->range_left = width-1;
705 node->range_right = 0;
706 return node;
707 }
708
709 // create an AST node for a constant (using a bit vector as value)
710 AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
711 {
712 AstNode *node = new AstNode(AST_CONSTANT);
713 node->is_signed = is_signed;
714 node->bits = v;
715 for (size_t i = 0; i < 32; i++) {
716 if (i < node->bits.size())
717 node->integer |= (node->bits[i] == RTLIL::S1) << i;
718 else if (is_signed && !node->bits.empty())
719 node->integer |= (node->bits.back() == RTLIL::S1) << i;
720 }
721 node->range_valid = true;
722 node->range_left = node->bits.size()-1;
723 node->range_right = 0;
724 return node;
725 }
726
727 // create an AST node for a constant (using a string in bit vector form as value)
728 AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
729 {
730 AstNode *node = mkconst_str(RTLIL::Const(v).decode_string());
731 while (GetSize(node->bits) < GetSize(v))
732 node->bits.push_back(RTLIL::State::S0);
733 log_assert(node->bits == v);
734 return node;
735 }
736
737 // create an AST node for a constant (using a string as value)
738 AstNode *AstNode::mkconst_str(const std::string &str)
739 {
740 std::vector<RTLIL::State> data;
741 data.reserve(str.size() * 8);
742 for (size_t i = 0; i < str.size(); i++) {
743 unsigned char ch = str[str.size() - i - 1];
744 for (int j = 0; j < 8; j++) {
745 data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
746 ch = ch >> 1;
747 }
748 }
749 AstNode *node = AstNode::mkconst_bits(data, false);
750 node->is_string = true;
751 node->str = str;
752 return node;
753 }
754
755 bool AstNode::bits_only_01()
756 {
757 for (auto bit : bits)
758 if (bit != RTLIL::S0 && bit != RTLIL::S1)
759 return false;
760 return true;
761 }
762
763 RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
764 {
765 std::vector<RTLIL::State> bits = this->bits;
766 if (width >= 0 && width < int(bits.size()))
767 bits.resize(width);
768 if (width >= 0 && width > int(bits.size())) {
769 RTLIL::State extbit = RTLIL::State::S0;
770 if (is_signed && !bits.empty())
771 extbit = bits.back();
772 while (width > int(bits.size()))
773 bits.push_back(extbit);
774 }
775 return RTLIL::Const(bits);
776 }
777
778 RTLIL::Const AstNode::bitsAsConst(int width)
779 {
780 return bitsAsConst(width, is_signed);
781 }
782
783 RTLIL::Const AstNode::asAttrConst()
784 {
785 log_assert(type == AST_CONSTANT);
786
787 RTLIL::Const val;
788 val.bits = bits;
789
790 if (is_string) {
791 val.flags |= RTLIL::CONST_FLAG_STRING;
792 log_assert(val.decode_string() == str);
793 }
794
795 return val;
796 }
797
798 RTLIL::Const AstNode::asParaConst()
799 {
800 RTLIL::Const val = asAttrConst();
801 if (is_signed)
802 val.flags |= RTLIL::CONST_FLAG_SIGNED;
803 return val;
804 }
805
806 bool AstNode::asBool()
807 {
808 log_assert(type == AST_CONSTANT);
809 for (auto &bit : bits)
810 if (bit == RTLIL::State::S1)
811 return true;
812 return false;
813 }
814
815 int AstNode::isConst()
816 {
817 if (type == AST_CONSTANT)
818 return 1;
819 if (type == AST_REALVALUE)
820 return 2;
821 return 0;
822 }
823
824 uint64_t AstNode::asInt(bool is_signed)
825 {
826 if (type == AST_CONSTANT)
827 {
828 RTLIL::Const v = bitsAsConst(64, is_signed);
829 uint64_t ret = 0;
830
831 for (int i = 0; i < 64; i++)
832 if (v.bits.at(i) == RTLIL::State::S1)
833 ret |= uint64_t(1) << i;
834
835 return ret;
836 }
837
838 if (type == AST_REALVALUE)
839 return uint64_t(realvalue);
840
841 log_abort();
842 }
843
844 double AstNode::asReal(bool is_signed)
845 {
846 if (type == AST_CONSTANT)
847 {
848 RTLIL::Const val(bits);
849
850 bool is_negative = is_signed && !val.bits.empty() && val.bits.back() == RTLIL::State::S1;
851 if (is_negative)
852 val = const_neg(val, val, false, false, val.bits.size());
853
854 double v = 0;
855 for (size_t i = 0; i < val.bits.size(); i++)
856 // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
857 // the net or the variable shall be treated as zero upon conversion.
858 if (val.bits.at(i) == RTLIL::State::S1)
859 v += exp2(i);
860 if (is_negative)
861 v *= -1;
862
863 return v;
864 }
865
866 if (type == AST_REALVALUE)
867 return realvalue;
868
869 log_abort();
870 }
871
872 RTLIL::Const AstNode::realAsConst(int width)
873 {
874 double v = round(realvalue);
875 RTLIL::Const result;
876 #ifdef EMSCRIPTEN
877 if (!isfinite(v)) {
878 #else
879 if (!std::isfinite(v)) {
880 #endif
881 result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
882 } else {
883 bool is_negative = v < 0;
884 if (is_negative)
885 v *= -1;
886 for (int i = 0; i < width; i++, v /= 2)
887 result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
888 if (is_negative)
889 result = const_neg(result, result, false, false, result.bits.size());
890 }
891 return result;
892 }
893
894 // create a new AstModule from an AST_MODULE AST node
895 static AstModule* process_module(AstNode *ast, bool defer)
896 {
897 log_assert(ast->type == AST_MODULE);
898
899 if (defer)
900 log("Storing AST representation for module `%s'.\n", ast->str.c_str());
901 else
902 log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
903
904 current_module = new AstModule;
905 current_module->ast = NULL;
906 current_module->name = ast->str;
907 current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
908
909 current_ast_mod = ast;
910 AstNode *ast_before_simplify = ast->clone();
911
912 if (flag_dump_ast1) {
913 log("Dumping Verilog AST before simplification:\n");
914 ast->dumpAst(NULL, " ");
915 log("--- END OF AST DUMP ---\n");
916 }
917
918 if (!defer)
919 {
920 while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
921
922 if (flag_dump_ast2) {
923 log("Dumping Verilog AST after simplification:\n");
924 ast->dumpAst(NULL, " ");
925 log("--- END OF AST DUMP ---\n");
926 }
927
928 if (flag_dump_vlog) {
929 log("Dumping Verilog AST (as requested by dump_vlog option):\n");
930 ast->dumpVlog(NULL, " ");
931 log("--- END OF AST DUMP ---\n");
932 }
933
934 if (flag_lib) {
935 std::vector<AstNode*> new_children;
936 for (auto child : ast->children) {
937 if (child->type == AST_WIRE && (child->is_input || child->is_output))
938 new_children.push_back(child);
939 else
940 delete child;
941 }
942 ast->children.swap(new_children);
943 ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
944 }
945
946 ignoreThisSignalsInInitial = RTLIL::SigSpec();
947
948 for (auto &attr : ast->attributes) {
949 if (attr.second->type != AST_CONSTANT)
950 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
951 attr.first.c_str(), ast->filename.c_str(), ast->linenum);
952 current_module->attributes[attr.first] = attr.second->asAttrConst();
953 }
954 for (size_t i = 0; i < ast->children.size(); i++) {
955 AstNode *node = ast->children[i];
956 if (node->type == AST_WIRE || node->type == AST_MEMORY)
957 node->genRTLIL();
958 }
959 for (size_t i = 0; i < ast->children.size(); i++) {
960 AstNode *node = ast->children[i];
961 if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
962 node->genRTLIL();
963 }
964
965 ignoreThisSignalsInInitial.sort_and_unify();
966
967 for (size_t i = 0; i < ast->children.size(); i++) {
968 AstNode *node = ast->children[i];
969 if (node->type == AST_INITIAL)
970 node->genRTLIL();
971 }
972
973 ignoreThisSignalsInInitial = RTLIL::SigSpec();
974 }
975
976 current_module->ast = ast_before_simplify;
977 current_module->nolatches = flag_nolatches;
978 current_module->nomeminit = flag_nomeminit;
979 current_module->nomem2reg = flag_nomem2reg;
980 current_module->mem2reg = flag_mem2reg;
981 current_module->lib = flag_lib;
982 current_module->noopt = flag_noopt;
983 current_module->icells = flag_icells;
984 current_module->autowire = flag_autowire;
985 current_module->fixup_ports();
986
987 if (flag_dump_rtlil) {
988 log("Dumping generated RTLIL:\n");
989 log_module(current_module);
990 log("--- END OF RTLIL DUMP ---\n");
991 }
992
993 return current_module;
994 }
995
996 // create AstModule instances for all modules in the AST tree and add them to 'design'
997 void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
998 bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
999 {
1000 current_ast = ast;
1001 flag_dump_ast1 = dump_ast1;
1002 flag_dump_ast2 = dump_ast2;
1003 flag_dump_vlog = dump_vlog;
1004 flag_dump_rtlil = dump_rtlil;
1005 flag_nolatches = nolatches;
1006 flag_nomeminit = nomeminit;
1007 flag_nomem2reg = nomem2reg;
1008 flag_mem2reg = mem2reg;
1009 flag_lib = lib;
1010 flag_noopt = noopt;
1011 flag_icells = icells;
1012 flag_autowire = autowire;
1013
1014 std::vector<AstNode*> global_decls;
1015
1016 log_assert(current_ast->type == AST_DESIGN);
1017 for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
1018 {
1019 if ((*it)->type == AST_MODULE)
1020 {
1021 for (auto n : global_decls)
1022 (*it)->children.push_back(n->clone());
1023
1024 for (auto n : design->verilog_packages){
1025 for (auto o : n->children) {
1026 AstNode *cloned_node = o->clone();
1027 cloned_node->str = n->str + std::string("::") + cloned_node->str.substr(1);
1028 (*it)->children.push_back(cloned_node);
1029 }
1030 }
1031
1032 if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
1033 (*it)->str = (*it)->str.substr(1);
1034
1035 if (defer)
1036 (*it)->str = "$abstract" + (*it)->str;
1037
1038 if (design->has((*it)->str)) {
1039 if (!ignore_redef)
1040 log_error("Re-definition of module `%s' at %s:%d!\n",
1041 (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
1042 log("Ignoring re-definition of module `%s' at %s:%d!\n",
1043 (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
1044 continue;
1045 }
1046
1047 design->add(process_module(*it, defer));
1048 }
1049 else if ((*it)->type == AST_PACKAGE)
1050 design->verilog_packages.push_back((*it)->clone());
1051 else
1052 global_decls.push_back(*it);
1053 }
1054 }
1055
1056 // AstModule destructor
1057 AstModule::~AstModule()
1058 {
1059 if (ast != NULL)
1060 delete ast;
1061 }
1062
1063 // create a new parametric module (when needed) and return the name of the generated module
1064 RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters)
1065 {
1066 std::string stripped_name = name.str();
1067
1068 if (stripped_name.substr(0, 9) == "$abstract")
1069 stripped_name = stripped_name.substr(9);
1070
1071 log_header(design, "Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
1072
1073 current_ast = NULL;
1074 flag_dump_ast1 = false;
1075 flag_dump_ast2 = false;
1076 flag_dump_vlog = false;
1077 flag_nolatches = nolatches;
1078 flag_nomeminit = nomeminit;
1079 flag_nomem2reg = nomem2reg;
1080 flag_mem2reg = mem2reg;
1081 flag_lib = lib;
1082 flag_noopt = noopt;
1083 flag_icells = icells;
1084 flag_autowire = autowire;
1085 use_internal_line_num();
1086
1087 std::string para_info;
1088 AstNode *new_ast = ast->clone();
1089
1090 int para_counter = 0;
1091 int orig_parameters_n = parameters.size();
1092 for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
1093 AstNode *child = *it;
1094 if (child->type != AST_PARAMETER)
1095 continue;
1096 para_counter++;
1097 std::string para_id = child->str;
1098 if (parameters.count(para_id) > 0) {
1099 log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
1100 rewrite_parameter:
1101 para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
1102 delete child->children.at(0);
1103 child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
1104 parameters.erase(para_id);
1105 continue;
1106 }
1107 para_id = stringf("$%d", para_counter);
1108 if (parameters.count(para_id) > 0) {
1109 log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
1110 goto rewrite_parameter;
1111 }
1112 }
1113 if (parameters.size() > 0)
1114 log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), stripped_name.c_str());
1115
1116 std::string modname;
1117
1118 if (orig_parameters_n == 0)
1119 modname = stripped_name;
1120 else if (para_info.size() > 60)
1121 modname = "$paramod$" + sha1(para_info) + stripped_name;
1122 else
1123 modname = "$paramod" + stripped_name + para_info;
1124
1125 if (!design->has(modname)) {
1126 new_ast->str = modname;
1127 design->add(process_module(new_ast, false));
1128 design->module(modname)->check();
1129 } else {
1130 log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
1131 }
1132
1133 delete new_ast;
1134 return modname;
1135 }
1136
1137 RTLIL::Module *AstModule::clone() const
1138 {
1139 AstModule *new_mod = new AstModule;
1140 new_mod->name = name;
1141 cloneInto(new_mod);
1142
1143 new_mod->ast = ast->clone();
1144 new_mod->nolatches = nolatches;
1145 new_mod->nomeminit = nomeminit;
1146 new_mod->nomem2reg = nomem2reg;
1147 new_mod->mem2reg = mem2reg;
1148 new_mod->lib = lib;
1149 new_mod->noopt = noopt;
1150 new_mod->icells = icells;
1151 new_mod->autowire = autowire;
1152
1153 return new_mod;
1154 }
1155
1156 // internal dummy line number callbacks
1157 namespace {
1158 int internal_line_num;
1159 void internal_set_line_num(int n) {
1160 internal_line_num = n;
1161 }
1162 int internal_get_line_num() {
1163 return internal_line_num;
1164 }
1165 }
1166
1167 // use internal dummy line number callbacks
1168 void AST::use_internal_line_num()
1169 {
1170 set_line_num = &internal_set_line_num;
1171 get_line_num = &internal_get_line_num;
1172 }
1173
1174 YOSYS_NAMESPACE_END
1175