frontends/ast/ast.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  This is the AST frontend library.
  21  *
  22  *  The AST frontend library is not a frontend on it's own but provides a
  23  *  generic abstract syntax tree (AST) abstraction for HDL code and can be
  24  *  used by HDL frontends. See "ast.h" for an overview of the API and the
  25  *  Verilog frontend for an usage example.
  26  *
  27  */
  28
  29 #include "kernel/log.h"
  30 #include "libs/sha1/sha1.h"
  31 #include "ast.h"
  32
  33 #include <sstream>
  34 #include <stdarg.h>
  35 #include <math.h>
  36
  37 YOSYS_NAMESPACE_BEGIN
  38
  39 using namespace AST;
  40 using namespace AST_INTERNAL;
  41
  42 // instanciate global variables (public API)
  43 namespace AST {
  44         std::string current_filename;
  45         void (*set_line_num)(int) = NULL;
  46         int (*get_line_num)() = NULL;
  47 }
  48
  49 // instanciate global variables (private API)
  50 namespace AST_INTERNAL {
  51         bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
  52         AstNode *current_ast, *current_ast_mod;
  53         std::map<std::string, AstNode*> current_scope;
  54         const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
  55         RTLIL::SigSpec ignoreThisSignalsInInitial;
  56         AstNode *current_top_block, *current_block, *current_block_child;
  57         AstModule *current_module;
  58 }
  59
  60 // convert node types to string
  61 std::string AST::type2str(AstNodeType type)
  62 {
  63         switch (type)
  64         {
  65 #define X(_item) case _item: return #_item;
  66         X(AST_NONE)
  67         X(AST_DESIGN)
  68         X(AST_MODULE)
  69         X(AST_TASK)
  70         X(AST_FUNCTION)
  71         X(AST_DPI_FUNCTION)
  72         X(AST_WIRE)
  73         X(AST_MEMORY)
  74         X(AST_AUTOWIRE)
  75         X(AST_PARAMETER)
  76         X(AST_LOCALPARAM)
  77         X(AST_DEFPARAM)
  78         X(AST_PARASET)
  79         X(AST_ARGUMENT)
  80         X(AST_RANGE)
  81         X(AST_MULTIRANGE)
  82         X(AST_CONSTANT)
  83         X(AST_REALVALUE)
  84         X(AST_CELLTYPE)
  85         X(AST_IDENTIFIER)
  86         X(AST_PREFIX)
  87         X(AST_ASSERT)
  88         X(AST_FCALL)
  89         X(AST_TO_BITS)
  90         X(AST_TO_SIGNED)
  91         X(AST_TO_UNSIGNED)
  92         X(AST_CONCAT)
  93         X(AST_REPLICATE)
  94         X(AST_BIT_NOT)
  95         X(AST_BIT_AND)
  96         X(AST_BIT_OR)
  97         X(AST_BIT_XOR)
  98         X(AST_BIT_XNOR)
  99         X(AST_REDUCE_AND)
 100         X(AST_REDUCE_OR)
 101         X(AST_REDUCE_XOR)
 102         X(AST_REDUCE_XNOR)
 103         X(AST_REDUCE_BOOL)
 104         X(AST_SHIFT_LEFT)
 105         X(AST_SHIFT_RIGHT)
 106         X(AST_SHIFT_SLEFT)
 107         X(AST_SHIFT_SRIGHT)
 108         X(AST_LT)
 109         X(AST_LE)
 110         X(AST_EQ)
 111         X(AST_NE)
 112         X(AST_EQX)
 113         X(AST_NEX)
 114         X(AST_GE)
 115         X(AST_GT)
 116         X(AST_ADD)
 117         X(AST_SUB)
 118         X(AST_MUL)
 119         X(AST_DIV)
 120         X(AST_MOD)
 121         X(AST_POW)
 122         X(AST_POS)
 123         X(AST_NEG)
 124         X(AST_LOGIC_AND)
 125         X(AST_LOGIC_OR)
 126         X(AST_LOGIC_NOT)
 127         X(AST_TERNARY)
 128         X(AST_MEMRD)
 129         X(AST_MEMWR)
 130         X(AST_TCALL)
 131         X(AST_ASSIGN)
 132         X(AST_CELL)
 133         X(AST_PRIMITIVE)
 134         X(AST_CELLARRAY)
 135         X(AST_ALWAYS)
 136         X(AST_INITIAL)
 137         X(AST_BLOCK)
 138         X(AST_ASSIGN_EQ)
 139         X(AST_ASSIGN_LE)
 140         X(AST_CASE)
 141         X(AST_COND)
 142         X(AST_DEFAULT)
 143         X(AST_FOR)
 144         X(AST_WHILE)
 145         X(AST_REPEAT)
 146         X(AST_GENVAR)
 147         X(AST_GENFOR)
 148         X(AST_GENIF)
 149         X(AST_GENCASE)
 150         X(AST_GENBLOCK)
 151         X(AST_POSEDGE)
 152         X(AST_NEGEDGE)
 153         X(AST_EDGE)
 154 #undef X
 155         default:
 156                 log_abort();
 157         }
 158 }
 159
 160 // check if attribute exists and has non-zero value
 161 bool AstNode::get_bool_attribute(RTLIL::IdString id)
 162 {
 163         if (attributes.count(id) == 0)
 164                 return false;
 165
 166         AstNode *attr = attributes.at(id);
 167         if (attr->type != AST_CONSTANT)
 168                 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 169                                 id.c_str(), attr->filename.c_str(), attr->linenum);
 170
 171         return attr->integer != 0;
 172 }
 173
 174 // create new node (AstNode constructor)
 175 // (the optional child arguments make it easier to create AST trees)
 176 AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2)
 177 {
 178         this->type = type;
 179         filename = current_filename;
 180         linenum = get_line_num();
 181         is_input = false;
 182         is_output = false;
 183         is_reg = false;
 184         is_signed = false;
 185         is_string = false;
 186         range_valid = false;
 187         range_swapped = false;
 188         port_id = 0;
 189         range_left = -1;
 190         range_right = 0;
 191         integer = 0;
 192         realvalue = 0;
 193         id2ast = NULL;
 194         basic_prep = false;
 195
 196         if (child1)
 197                 children.push_back(child1);
 198         if (child2)
 199                 children.push_back(child2);
 200 }
 201
 202 // create a (deep recursive) copy of a node
 203 AstNode *AstNode::clone()
 204 {
 205         AstNode *that = new AstNode;
 206         *that = *this;
 207         for (auto &it : that->children)
 208                 it = it->clone();
 209         for (auto &it : that->attributes)
 210                 it.second = it.second->clone();
 211         return that;
 212 }
 213
 214 // create a (deep recursive) copy of a node use 'other' as target root node
 215 void AstNode::cloneInto(AstNode *other)
 216 {
 217         AstNode *tmp = clone();
 218         other->delete_children();
 219         *other = *tmp;
 220         tmp->children.clear();
 221         tmp->attributes.clear();
 222         delete tmp;
 223 }
 224
 225 // delete all children in this node
 226 void AstNode::delete_children()
 227 {
 228         for (auto &it : children)
 229                 delete it;
 230         children.clear();
 231
 232         for (auto &it : attributes)
 233                 delete it.second;
 234         attributes.clear();
 235 }
 236
 237 // AstNode destructor
 238 AstNode::~AstNode()
 239 {
 240         delete_children();
 241 }
 242
 243 // create a nice text representation of the node
 244 // (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
 245 void AstNode::dumpAst(FILE *f, std::string indent)
 246 {
 247         if (f == NULL) {
 248                 for (auto f : log_files)
 249                         dumpAst(f, indent);
 250                 return;
 251         }
 252
 253         std::string type_name = type2str(type);
 254         fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
 255
 256         if (id2ast)
 257                 fprintf(f, " [%p -> %p]", this, id2ast);
 258         else
 259                 fprintf(f, " [%p]", this);
 260
 261         if (!str.empty())
 262                 fprintf(f, " str='%s'", str.c_str());
 263         if (!bits.empty()) {
 264                 fprintf(f, " bits='");
 265                 for (size_t i = bits.size(); i > 0; i--)
 266                         fprintf(f, "%c", bits[i-1] == RTLIL::S0 ? '0' :
 267                                         bits[i-1] == RTLIL::S1 ? '1' :
 268                                         bits[i-1] == RTLIL::Sx ? 'x' :
 269                                         bits[i-1] == RTLIL::Sz ? 'z' : '?');
 270                 fprintf(f, "'(%d)", GetSize(bits));
 271         }
 272         if (is_input)
 273                 fprintf(f, " input");
 274         if (is_output)
 275                 fprintf(f, " output");
 276         if (is_reg)
 277                 fprintf(f, " reg");
 278         if (is_signed)
 279                 fprintf(f, " signed");
 280         if (port_id > 0)
 281                 fprintf(f, " port=%d", port_id);
 282         if (range_valid || range_left != -1 || range_right != 0)
 283                 fprintf(f, " %srange=[%d:%d]%s", range_swapped ? "swapped_" : "", range_left, range_right, range_valid ? "" : "!");
 284         if (integer != 0)
 285                 fprintf(f, " int=%u", (int)integer);
 286         if (realvalue != 0)
 287                 fprintf(f, " real=%e", realvalue);
 288         if (!multirange_dimensions.empty()) {
 289                 fprintf(f, " multirange=[");
 290                 for (int v : multirange_dimensions)
 291                         fprintf(f, " %d", v);
 292                 fprintf(f, " ]");
 293         }
 294         fprintf(f, "\n");
 295
 296         for (auto &it : attributes) {
 297                 fprintf(f, "%s  ATTR %s:\n", indent.c_str(), it.first.c_str());
 298                 it.second->dumpAst(f, indent + "    ");
 299         }
 300
 301         for (size_t i = 0; i < children.size(); i++)
 302                 children[i]->dumpAst(f, indent + "  ");
 303 }
 304
 305 // helper function for AstNode::dumpVlog()
 306 static std::string id2vl(std::string txt)
 307 {
 308         if (txt.size() > 1 && txt[0] == '\\')
 309                 txt = txt.substr(1);
 310         for (size_t i = 0; i < txt.size(); i++) {
 311                 if ('A' <= txt[i] && txt[i] <= 'Z') continue;
 312                 if ('a' <= txt[i] && txt[i] <= 'z') continue;
 313                 if ('0' <= txt[i] && txt[i] <= '9') continue;
 314                 if (txt[i] == '_') continue;
 315                 txt = "\\" + txt + " ";
 316                 break;
 317         }
 318         return txt;
 319 }
 320
 321 // dump AST node as verilog pseudo-code
 322 void AstNode::dumpVlog(FILE *f, std::string indent)
 323 {
 324         bool first = true;
 325         std::string txt;
 326         std::vector<AstNode*> rem_children1, rem_children2;
 327
 328         if (f == NULL) {
 329                 for (auto f : log_files)
 330                         dumpVlog(f, indent);
 331                 return;
 332         }
 333
 334         for (auto &it : attributes) {
 335                 fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
 336                 it.second->dumpVlog(f, "");
 337                 fprintf(f, " *)%s", indent.empty() ? "" : "\n");
 338         }
 339
 340         switch (type)
 341         {
 342         case AST_MODULE:
 343                 fprintf(f, "%s" "module %s(", indent.c_str(), id2vl(str).c_str());
 344                 for (auto child : children)
 345                         if (child->type == AST_WIRE && (child->is_input || child->is_output)) {
 346                                 fprintf(f, "%s%s", first ? "" : ", ", id2vl(child->str).c_str());
 347                                 first = false;
 348                         }
 349                 fprintf(f, ");\n");
 350
 351                 for (auto child : children)
 352                         if (child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || child->type == AST_DEFPARAM)
 353                                 child->dumpVlog(f, indent + "  ");
 354                         else
 355                                 rem_children1.push_back(child);
 356
 357                 for (auto child : rem_children1)
 358                         if (child->type == AST_WIRE || child->type == AST_AUTOWIRE || child->type == AST_MEMORY)
 359                                 child->dumpVlog(f, indent + "  ");
 360                         else
 361                                 rem_children2.push_back(child);
 362                 rem_children1.clear();
 363
 364                 for (auto child : rem_children2)
 365                         if (child->type == AST_TASK || child->type == AST_FUNCTION)
 366                                 child->dumpVlog(f, indent + "  ");
 367                         else
 368                                 rem_children1.push_back(child);
 369                 rem_children2.clear();
 370
 371                 for (auto child : rem_children1)
 372                         child->dumpVlog(f, indent + "  ");
 373                 rem_children1.clear();
 374
 375                 fprintf(f, "%s" "endmodule\n", indent.c_str());
 376                 break;
 377
 378         case AST_WIRE:
 379                 if (is_input && is_output)
 380                         fprintf(f, "%s" "inout", indent.c_str());
 381                 else if (is_input)
 382                         fprintf(f, "%s" "input", indent.c_str());
 383                 else if (is_output)
 384                         fprintf(f, "%s" "output", indent.c_str());
 385                 else if (!is_reg)
 386                         fprintf(f, "%s" "wire", indent.c_str());
 387                 if (is_reg)
 388                         fprintf(f, "%s" "reg", (is_input || is_output) ? " " : indent.c_str());
 389                 if (is_signed)
 390                         fprintf(f, " signed");
 391                 for (auto child : children) {
 392                         fprintf(f, " ");
 393                         child->dumpVlog(f, "");
 394                 }
 395                 fprintf(f, " %s", id2vl(str).c_str());
 396                 fprintf(f, ";\n");
 397                 break;
 398
 399         case AST_MEMORY:
 400                 fprintf(f, "%s" "memory", indent.c_str());
 401                 if (is_signed)
 402                         fprintf(f, " signed");
 403                 for (auto child : children) {
 404                         fprintf(f, " ");
 405                         child->dumpVlog(f, "");
 406                         if (first)
 407                                 fprintf(f, " %s", id2vl(str).c_str());
 408                         first = false;
 409                 }
 410                 fprintf(f, ";\n");
 411                 break;
 412
 413         case AST_RANGE:
 414                 if (range_valid)
 415                         fprintf(f, "[%d:%d]", range_left, range_right);
 416                 else {
 417                         for (auto child : children) {
 418                                 fprintf(f, "%c", first ? '[' : ':');
 419                                 child->dumpVlog(f, "");
 420                                 first = false;
 421                         }
 422                         fprintf(f, "]");
 423                 }
 424                 break;
 425
 426         case AST_ALWAYS:
 427                 fprintf(f, "%s" "always @(", indent.c_str());
 428                 for (auto child : children) {
 429                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 430                                 continue;
 431                         if (!first)
 432                                 fprintf(f, ", ");
 433                         child->dumpVlog(f, "");
 434                         first = false;
 435                 }
 436                 fprintf(f, ")\n");
 437                 for (auto child : children) {
 438                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 439                                 child->dumpVlog(f, indent + "  ");
 440                 }
 441                 break;
 442
 443         case AST_INITIAL:
 444                 fprintf(f, "%s" "initial\n", indent.c_str());
 445                 for (auto child : children) {
 446                         if (child->type != AST_POSEDGE && child->type != AST_NEGEDGE && child->type != AST_EDGE)
 447                                 child->dumpVlog(f, indent + "  ");
 448                 }
 449                 break;
 450
 451         case AST_POSEDGE:
 452         case AST_NEGEDGE:
 453         case AST_EDGE:
 454                 if (type == AST_POSEDGE)
 455                         fprintf(f, "posedge ");
 456                 if (type == AST_NEGEDGE)
 457                         fprintf(f, "negedge ");
 458                 for (auto child : children)
 459                         child->dumpVlog(f, "");
 460                 break;
 461
 462         case AST_IDENTIFIER:
 463                 fprintf(f, "%s", id2vl(str).c_str());
 464                 for (auto child : children)
 465                         child->dumpVlog(f, "");
 466                 break;
 467
 468         case AST_CONSTANT:
 469                 if (!str.empty())
 470                         fprintf(f, "\"%s\"", str.c_str());
 471                 else if (bits.size() == 32)
 472                         fprintf(f, "%d", RTLIL::Const(bits).as_int());
 473                 else
 474                         fprintf(f, "%d'b %s", GetSize(bits), RTLIL::Const(bits).as_string().c_str());
 475                 break;
 476
 477         case AST_REALVALUE:
 478                 fprintf(f, "%e", realvalue);
 479                 break;
 480
 481         case AST_BLOCK:
 482                 if (children.size() == 1) {
 483                         children[0]->dumpVlog(f, indent);
 484                 } else {
 485                         fprintf(f, "%s" "begin\n", indent.c_str());
 486                         for (auto child : children)
 487                                 child->dumpVlog(f, indent + "  ");
 488                         fprintf(f, "%s" "end\n", indent.c_str());
 489                 }
 490                 break;
 491
 492         case AST_CASE:
 493                 fprintf(f, "%s" "case (", indent.c_str());
 494                 children[0]->dumpVlog(f, "");
 495                 fprintf(f, ")\n");
 496                 for (size_t i = 1; i < children.size(); i++) {
 497                         AstNode *child = children[i];
 498                         child->dumpVlog(f, indent + "  ");
 499                 }
 500                 fprintf(f, "%s" "endcase\n", indent.c_str());
 501                 break;
 502
 503         case AST_COND:
 504                 for (auto child : children) {
 505                         if (child->type == AST_BLOCK) {
 506                                 fprintf(f, ":\n");
 507                                 child->dumpVlog(f, indent + "  ");
 508                                 first = true;
 509                         } else {
 510                                 fprintf(f, "%s", first ? indent.c_str() : ", ");
 511                                 if (child->type == AST_DEFAULT)
 512                                         fprintf(f, "default");
 513                                 else
 514                                         child->dumpVlog(f, "");
 515                                 first = false;
 516                         }
 517                 }
 518                 break;
 519
 520         case AST_ASSIGN_EQ:
 521         case AST_ASSIGN_LE:
 522                 fprintf(f, "%s", indent.c_str());
 523                 children[0]->dumpVlog(f, "");
 524                 fprintf(f, " %s ", type == AST_ASSIGN_EQ ? "=" : "<=");
 525                 children[1]->dumpVlog(f, "");
 526                 fprintf(f, ";\n");
 527                 break;
 528
 529         case AST_CONCAT:
 530                 fprintf(f, "{");
 531                 for (auto child : children) {
 532                         if (!first)
 533                                 fprintf(f, ", ");
 534                         child->dumpVlog(f, "");
 535                         first = false;
 536                 }
 537                 fprintf(f, "}");
 538                 break;
 539
 540         case AST_REPLICATE:
 541                 fprintf(f, "{");
 542                 children[0]->dumpVlog(f, "");
 543                 fprintf(f, "{");
 544                 children[1]->dumpVlog(f, "");
 545                 fprintf(f, "}}");
 546                 break;
 547
 548         if (0) { case AST_BIT_NOT:     txt = "~";  }
 549         if (0) { case AST_REDUCE_AND:  txt = "&";  }
 550         if (0) { case AST_REDUCE_OR:   txt = "|";  }
 551         if (0) { case AST_REDUCE_XOR:  txt = "^";  }
 552         if (0) { case AST_REDUCE_XNOR: txt = "~^"; }
 553         if (0) { case AST_REDUCE_BOOL: txt = "|";  }
 554         if (0) { case AST_POS:         txt = "+";  }
 555         if (0) { case AST_NEG:         txt = "-";  }
 556         if (0) { case AST_LOGIC_NOT:   txt = "!";  }
 557                 fprintf(f, "%s(", txt.c_str());
 558                 children[0]->dumpVlog(f, "");
 559                 fprintf(f, ")");
 560                 break;
 561
 562         if (0) { case AST_BIT_AND:      txt = "&";   }
 563         if (0) { case AST_BIT_OR:       txt = "|";   }
 564         if (0) { case AST_BIT_XOR:      txt = "^";   }
 565         if (0) { case AST_BIT_XNOR:     txt = "~^";  }
 566         if (0) { case AST_SHIFT_LEFT:   txt = "<<";  }
 567         if (0) { case AST_SHIFT_RIGHT:  txt = ">>";  }
 568         if (0) { case AST_SHIFT_SLEFT:  txt = "<<<"; }
 569         if (0) { case AST_SHIFT_SRIGHT: txt = ">>>"; }
 570         if (0) { case AST_LT:           txt = "<";   }
 571         if (0) { case AST_LE:           txt = "<=";  }
 572         if (0) { case AST_EQ:           txt = "==";  }
 573         if (0) { case AST_NE:           txt = "!=";  }
 574         if (0) { case AST_EQX:          txt = "===";  }
 575         if (0) { case AST_NEX:          txt = "!==";  }
 576         if (0) { case AST_GE:           txt = ">=";  }
 577         if (0) { case AST_GT:           txt = ">";   }
 578         if (0) { case AST_ADD:          txt = "+";   }
 579         if (0) { case AST_SUB:          txt = "-";   }
 580         if (0) { case AST_MUL:          txt = "*";   }
 581         if (0) { case AST_DIV:          txt = "/";   }
 582         if (0) { case AST_MOD:          txt = "%";   }
 583         if (0) { case AST_POW:          txt = "**";  }
 584         if (0) { case AST_LOGIC_AND:    txt = "&&";  }
 585         if (0) { case AST_LOGIC_OR:     txt = "||";  }
 586                 fprintf(f, "(");
 587                 children[0]->dumpVlog(f, "");
 588                 fprintf(f, ")%s(", txt.c_str());
 589                 children[1]->dumpVlog(f, "");
 590                 fprintf(f, ")");
 591                 break;
 592
 593         case AST_TERNARY:
 594                 fprintf(f, "(");
 595                 children[0]->dumpVlog(f, "");
 596                 fprintf(f, ") ? (");
 597                 children[1]->dumpVlog(f, "");
 598                 fprintf(f, ") : (");
 599                 children[2]->dumpVlog(f, "");
 600                 fprintf(f, ")");
 601                 break;
 602
 603         default:
 604                 std::string type_name = type2str(type);
 605                 fprintf(f, "%s" "/** %s **/%s", indent.c_str(), type_name.c_str(), indent.empty() ? "" : "\n");
 606                 // dumpAst(f, indent, NULL);
 607         }
 608 }
 609
 610 // check if two AST nodes are identical
 611 bool AstNode::operator==(const AstNode &other) const
 612 {
 613         if (type != other.type)
 614                 return false;
 615         if (children.size() != other.children.size())
 616                 return false;
 617         if (str != other.str)
 618                 return false;
 619         if (bits != other.bits)
 620                 return false;
 621         if (is_input != other.is_input)
 622                 return false;
 623         if (is_output != other.is_output)
 624                 return false;
 625         if (is_reg != other.is_reg)
 626                 return false;
 627         if (is_signed != other.is_signed)
 628                 return false;
 629         if (is_string != other.is_string)
 630                 return false;
 631         if (range_valid != other.range_valid)
 632                 return false;
 633         if (range_swapped != other.range_swapped)
 634                 return false;
 635         if (port_id != other.port_id)
 636                 return false;
 637         if (range_left != other.range_left)
 638                 return false;
 639         if (range_right != other.range_right)
 640                 return false;
 641         if (integer != other.integer)
 642                 return false;
 643         for (size_t i = 0; i < children.size(); i++)
 644                 if (*children[i] != *other.children[i])
 645                         return false;
 646         return true;
 647 }
 648
 649 // check if two AST nodes are not identical
 650 bool AstNode::operator!=(const AstNode &other) const
 651 {
 652         return !(*this == other);
 653 }
 654
 655 // check if this AST contains the given node
 656 bool AstNode::contains(const AstNode *other) const
 657 {
 658         if (this == other)
 659                 return true;
 660         for (auto child : children)
 661                 if (child->contains(other))
 662                         return true;
 663         return false;
 664 }
 665
 666 // create an AST node for a constant (using a 32 bit int as value)
 667 AstNode *AstNode::mkconst_int(uint32_t v, bool is_signed, int width)
 668 {
 669         AstNode *node = new AstNode(AST_CONSTANT);
 670         node->integer = v;
 671         node->is_signed = is_signed;
 672         for (int i = 0; i < width; i++) {
 673                 node->bits.push_back((v & 1) ? RTLIL::S1 : RTLIL::S0);
 674                 v = v >> 1;
 675         }
 676         node->range_valid = true;
 677         node->range_left = width-1;
 678         node->range_right = 0;
 679         return node;
 680 }
 681
 682 // create an AST node for a constant (using a bit vector as value)
 683 AstNode *AstNode::mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed)
 684 {
 685         AstNode *node = new AstNode(AST_CONSTANT);
 686         node->is_signed = is_signed;
 687         node->bits = v;
 688         for (size_t i = 0; i < 32; i++) {
 689                 if (i < node->bits.size())
 690                         node->integer |= (node->bits[i] == RTLIL::S1) << i;
 691                 else if (is_signed)
 692                         node->integer |= (node->bits.back() == RTLIL::S1) << i;
 693         }
 694         node->range_valid = true;
 695         node->range_left = node->bits.size()-1;
 696         node->range_right = 0;
 697         return node;
 698 }
 699
 700 // create an AST node for a constant (using a string in bit vector form as value)
 701 AstNode *AstNode::mkconst_str(const std::vector<RTLIL::State> &v)
 702 {
 703         AstNode *node = mkconst_str(RTLIL::Const(v).decode_string());
 704         log_assert(node->bits == v);
 705         return node;
 706 }
 707
 708 // create an AST node for a constant (using a string as value)
 709 AstNode *AstNode::mkconst_str(const std::string &str)
 710 {
 711         std::vector<RTLIL::State> data;
 712         data.reserve(str.size() * 8);
 713         for (size_t i = 0; i < str.size(); i++) {
 714                 unsigned char ch = str[str.size() - i - 1];
 715                 for (int j = 0; j < 8; j++) {
 716                         data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
 717                         ch = ch >> 1;
 718                 }
 719         }
 720         AstNode *node = AstNode::mkconst_bits(data, false);
 721         node->is_string = true;
 722         node->str = str;
 723         return node;
 724 }
 725
 726 bool AstNode::bits_only_01()
 727 {
 728         for (auto bit : bits)
 729                 if (bit != RTLIL::S0 && bit != RTLIL::S1)
 730                         return false;
 731         return true;
 732 }
 733
 734 RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
 735 {
 736         std::vector<RTLIL::State> bits = this->bits;
 737         if (width >= 0 && width < int(bits.size()))
 738                 bits.resize(width);
 739         if (width >= 0 && width > int(bits.size())) {
 740                 RTLIL::State extbit = RTLIL::State::S0;
 741                 if (is_signed && !bits.empty())
 742                         extbit = bits.back();
 743                 while (width > int(bits.size()))
 744                         bits.push_back(extbit);
 745         }
 746         return RTLIL::Const(bits);
 747 }
 748
 749 RTLIL::Const AstNode::bitsAsConst(int width)
 750 {
 751         return bitsAsConst(width, is_signed);
 752 }
 753
 754 RTLIL::Const AstNode::asAttrConst()
 755 {
 756         log_assert(type == AST_CONSTANT);
 757
 758         RTLIL::Const val;
 759         val.bits = bits;
 760
 761         if (is_string) {
 762                 val.flags |= RTLIL::CONST_FLAG_STRING;
 763                 log_assert(val.decode_string() == str);
 764         }
 765
 766         return val;
 767 }
 768
 769 RTLIL::Const AstNode::asParaConst()
 770 {
 771         RTLIL::Const val = asAttrConst();
 772         if (is_signed)
 773                 val.flags |= RTLIL::CONST_FLAG_SIGNED;
 774         return val;
 775 }
 776
 777 bool AstNode::asBool()
 778 {
 779         log_assert(type == AST_CONSTANT);
 780         for (auto &bit : bits)
 781                 if (bit == RTLIL::State::S1)
 782                         return true;
 783         return false;
 784 }
 785
 786 int AstNode::isConst()
 787 {
 788         if (type == AST_CONSTANT)
 789                 return 1;
 790         if (type == AST_REALVALUE)
 791                 return 2;
 792         return 0;
 793 }
 794
 795 uint64_t AstNode::asInt(bool is_signed)
 796 {
 797         if (type == AST_CONSTANT)
 798         {
 799                 RTLIL::Const v = bitsAsConst(64, is_signed);
 800                 uint64_t ret = 0;
 801
 802                 for (int i = 0; i < 64; i++)
 803                         if (v.bits.at(i) == RTLIL::State::S1)
 804                                 ret |= uint64_t(1) << i;
 805
 806                 return ret;
 807         }
 808
 809         if (type == AST_REALVALUE)
 810                 return realvalue;
 811
 812         log_abort();
 813 }
 814
 815 double AstNode::asReal(bool is_signed)
 816 {
 817         if (type == AST_CONSTANT)
 818         {
 819                 RTLIL::Const val(bits);
 820
 821                 bool is_negative = is_signed && val.bits.back() == RTLIL::State::S1;
 822                 if (is_negative)
 823                         val = const_neg(val, val, false, false, val.bits.size());
 824
 825                 double v = 0;
 826                 for (size_t i = 0; i < val.bits.size(); i++)
 827                         // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
 828                         // the net or the variable shall be treated as zero upon conversion.
 829                         if (val.bits.at(i) == RTLIL::State::S1)
 830                                 v += exp2(i);
 831                 if (is_negative)
 832                         v *= -1;
 833
 834                 return v;
 835         }
 836
 837         if (type == AST_REALVALUE)
 838                 return realvalue;
 839
 840         log_abort();
 841 }
 842
 843 RTLIL::Const AstNode::realAsConst(int width)
 844 {
 845         double v = round(realvalue);
 846         RTLIL::Const result;
 847 #ifdef EMSCRIPTEN
 848         if (!isfinite(v)) {
 849 #else
 850         if (!std::isfinite(v)) {
 851 #endif
 852                 result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
 853         } else {
 854                 bool is_negative = v < 0;
 855                 if (is_negative)
 856                         v *= -1;
 857                 for (int i = 0; i < width; i++, v /= 2)
 858                         result.bits.push_back((fmod(floor(v), 2) != 0) ? RTLIL::State::S1 : RTLIL::State::S0);
 859                 if (is_negative)
 860                         result = const_neg(result, result, false, false, result.bits.size());
 861         }
 862         return result;
 863 }
 864
 865 // create a new AstModule from an AST_MODULE AST node
 866 static AstModule* process_module(AstNode *ast, bool defer)
 867 {
 868         log_assert(ast->type == AST_MODULE);
 869
 870         if (defer)
 871                 log("Storing AST representation for module `%s'.\n", ast->str.c_str());
 872         else
 873                 log("Generating RTLIL representation for module `%s'.\n", ast->str.c_str());
 874
 875         current_module = new AstModule;
 876         current_module->ast = NULL;
 877         current_module->name = ast->str;
 878         current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
 879
 880         current_ast_mod = ast;
 881         AstNode *ast_before_simplify = ast->clone();
 882
 883         if (flag_dump_ast1) {
 884                 log("Dumping verilog AST before simplification:\n");
 885                 ast->dumpAst(NULL, "    ");
 886                 log("--- END OF AST DUMP ---\n");
 887         }
 888
 889         if (!defer)
 890         {
 891                 while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
 892
 893                 if (flag_dump_ast2) {
 894                         log("Dumping verilog AST after simplification:\n");
 895                         ast->dumpAst(NULL, "    ");
 896                         log("--- END OF AST DUMP ---\n");
 897                 }
 898
 899                 if (flag_dump_vlog) {
 900                         log("Dumping verilog AST (as requested by dump_vlog option):\n");
 901                         ast->dumpVlog(NULL, "    ");
 902                         log("--- END OF AST DUMP ---\n");
 903                 }
 904
 905                 if (flag_lib) {
 906                         std::vector<AstNode*> new_children;
 907                         for (auto child : ast->children) {
 908                                 if (child->type == AST_WIRE && (child->is_input || child->is_output))
 909                                         new_children.push_back(child);
 910                                 else
 911                                         delete child;
 912                         }
 913                         ast->children.swap(new_children);
 914                         ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false);
 915                 }
 916
 917                 ignoreThisSignalsInInitial = RTLIL::SigSpec();
 918
 919                 for (auto &attr : ast->attributes) {
 920                         if (attr.second->type != AST_CONSTANT)
 921                                 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
 922                                                 attr.first.c_str(), ast->filename.c_str(), ast->linenum);
 923                         current_module->attributes[attr.first] = attr.second->asAttrConst();
 924                 }
 925                 for (size_t i = 0; i < ast->children.size(); i++) {
 926                         AstNode *node = ast->children[i];
 927                         if (node->type == AST_WIRE || node->type == AST_MEMORY)
 928                                 node->genRTLIL();
 929                 }
 930                 for (size_t i = 0; i < ast->children.size(); i++) {
 931                         AstNode *node = ast->children[i];
 932                         if (node->type != AST_WIRE && node->type != AST_MEMORY && node->type != AST_INITIAL)
 933                                 node->genRTLIL();
 934                 }
 935
 936                 ignoreThisSignalsInInitial.sort_and_unify();
 937
 938                 for (size_t i = 0; i < ast->children.size(); i++) {
 939                         AstNode *node = ast->children[i];
 940                         if (node->type == AST_INITIAL)
 941                                 node->genRTLIL();
 942                 }
 943
 944                 ignoreThisSignalsInInitial = RTLIL::SigSpec();
 945         }
 946
 947         current_module->ast = ast_before_simplify;
 948         current_module->nolatches = flag_nolatches;
 949         current_module->nomem2reg = flag_nomem2reg;
 950         current_module->mem2reg = flag_mem2reg;
 951         current_module->lib = flag_lib;
 952         current_module->noopt = flag_noopt;
 953         current_module->icells = flag_icells;
 954         current_module->autowire = flag_autowire;
 955         current_module->fixup_ports();
 956         return current_module;
 957 }
 958
 959 // create AstModule instances for all modules in the AST tree and add them to 'design'
 960 void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
 961 {
 962         current_ast = ast;
 963         flag_dump_ast1 = dump_ast1;
 964         flag_dump_ast2 = dump_ast2;
 965         flag_dump_vlog = dump_vlog;
 966         flag_nolatches = nolatches;
 967         flag_nomem2reg = nomem2reg;
 968         flag_mem2reg = mem2reg;
 969         flag_lib = lib;
 970         flag_noopt = noopt;
 971         flag_icells = icells;
 972         flag_autowire = autowire;
 973
 974         std::vector<AstNode*> global_decls;
 975
 976         log_assert(current_ast->type == AST_DESIGN);
 977         for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
 978         {
 979                 if ((*it)->type == AST_MODULE)
 980                 {
 981                         for (auto n : global_decls)
 982                                 (*it)->children.push_back(n->clone());
 983
 984                         if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
 985                                 (*it)->str = (*it)->str.substr(1);
 986
 987                         if (defer)
 988                                 (*it)->str = "$abstract" + (*it)->str;
 989
 990                         if (design->has((*it)->str)) {
 991                                 if (!ignore_redef)
 992                                         log_error("Re-definition of module `%s' at %s:%d!\n",
 993                                                         (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 994                                 log("Ignoring re-definition of module `%s' at %s:%d!\n",
 995                                                 (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
 996                                 continue;
 997                         }
 998
 999                         design->add(process_module(*it, defer));
1000                 }
1001                 else
1002                         global_decls.push_back(*it);
1003         }
1004 }
1005
1006 // AstModule destructor
1007 AstModule::~AstModule()
1008 {
1009         if (ast != NULL)
1010                 delete ast;
1011 }
1012
1013 // create a new parametric module (when needed) and return the name of the generated module
1014 RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
1015 {
1016         std::string stripped_name = name.str();
1017
1018         if (stripped_name.substr(0, 9) == "$abstract")
1019                 stripped_name = stripped_name.substr(9);
1020
1021         log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name.c_str());
1022
1023         current_ast = NULL;
1024         flag_dump_ast1 = false;
1025         flag_dump_ast2 = false;
1026         flag_dump_vlog = false;
1027         flag_nolatches = nolatches;
1028         flag_nomem2reg = nomem2reg;
1029         flag_mem2reg = mem2reg;
1030         flag_lib = lib;
1031         flag_noopt = noopt;
1032         flag_icells = icells;
1033         flag_autowire = autowire;
1034         use_internal_line_num();
1035
1036         std::string para_info;
1037         AstNode *new_ast = ast->clone();
1038
1039         int para_counter = 0;
1040         int orig_parameters_n = parameters.size();
1041         for (auto it = new_ast->children.begin(); it != new_ast->children.end(); it++) {
1042                 AstNode *child = *it;
1043                 if (child->type != AST_PARAMETER)
1044                         continue;
1045                 para_counter++;
1046                 std::string para_id = child->str;
1047                 if (parameters.count(para_id) > 0) {
1048                         log("Parameter %s = %s\n", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[child->str])));
1049         rewrite_parameter:
1050                         para_info += stringf("%s=%s", child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
1051                         delete child->children.at(0);
1052                         child->children[0] = AstNode::mkconst_bits(parameters[para_id].bits, (parameters[para_id].flags & RTLIL::CONST_FLAG_SIGNED) != 0);
1053                         parameters.erase(para_id);
1054                         continue;
1055                 }
1056                 para_id = stringf("$%d", para_counter);
1057                 if (parameters.count(para_id) > 0) {
1058                         log("Parameter %d (%s) = %s\n", para_counter, child->str.c_str(), log_signal(RTLIL::SigSpec(parameters[para_id])));
1059                         goto rewrite_parameter;
1060                 }
1061         }
1062         if (parameters.size() > 0)
1063                 log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters.begin()->first.c_str(), stripped_name.c_str());
1064
1065         std::string modname;
1066
1067         if (orig_parameters_n == 0)
1068                 modname = stripped_name;
1069         else if (para_info.size() > 60)
1070                 modname = "$paramod$" + sha1(para_info) + stripped_name;
1071         else
1072                 modname = "$paramod" + stripped_name + para_info;
1073
1074         if (!design->has(modname)) {
1075                 new_ast->str = modname;
1076                 design->add(process_module(new_ast, false));
1077                 design->module(modname)->check();
1078         } else {
1079                 log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
1080         }
1081
1082         delete new_ast;
1083         return modname;
1084 }
1085
1086 RTLIL::Module *AstModule::clone() const
1087 {
1088         AstModule *new_mod = new AstModule;
1089         new_mod->name = name;
1090         cloneInto(new_mod);
1091
1092         new_mod->ast = ast->clone();
1093         new_mod->nolatches = nolatches;
1094         new_mod->nomem2reg = nomem2reg;
1095         new_mod->mem2reg = mem2reg;
1096         new_mod->lib = lib;
1097         new_mod->noopt = noopt;
1098         new_mod->icells = icells;
1099         new_mod->autowire = autowire;
1100
1101         return new_mod;
1102 }
1103
1104 // internal dummy line number callbacks
1105 namespace {
1106         int internal_line_num;
1107         void internal_set_line_num(int n) {
1108                 internal_line_num = n;
1109         }
1110         int internal_get_line_num() {
1111                 return internal_line_num;
1112         }
1113 }
1114
1115 // use internal dummy line number callbacks
1116 void AST::use_internal_line_num()
1117 {
1118         set_line_num = &internal_set_line_num;
1119         get_line_num = &internal_get_line_num;
1120 }
1121
1122 YOSYS_NAMESPACE_END
1123