2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
36 #if defined(__APPLE__)
45 using namespace AST_INTERNAL
;
47 // instanciate global variables (public API)
49 std::string current_filename
;
50 void (*set_line_num
)(int) = NULL
;
51 int (*get_line_num
)() = NULL
;
54 // instanciate global variables (private API)
55 namespace AST_INTERNAL
{
56 bool flag_dump_ast1
, flag_dump_ast2
, flag_dump_vlog
, flag_nolatches
, flag_nomem2reg
, flag_mem2reg
, flag_lib
, flag_noopt
, flag_icells
, flag_autowire
;
57 AstNode
*current_ast
, *current_ast_mod
;
58 std::map
<std::string
, AstNode
*> current_scope
;
59 const dict
<RTLIL::SigBit
, RTLIL::SigBit
> *genRTLIL_subst_ptr
= NULL
;
60 RTLIL::SigSpec ignoreThisSignalsInInitial
;
61 AstNode
*current_top_block
, *current_block
, *current_block_child
;
62 AstModule
*current_module
;
65 // convert node types to string
66 std::string
AST::type2str(AstNodeType type
)
70 #define X(_item) case _item: return #_item;
165 // check if attribute exists and has non-zero value
166 bool AstNode::get_bool_attribute(RTLIL::IdString id
)
168 if (attributes
.count(id
) == 0)
171 AstNode
*attr
= attributes
.at(id
);
172 if (attr
->type
!= AST_CONSTANT
)
173 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
174 id
.c_str(), attr
->filename
.c_str(), attr
->linenum
);
176 return attr
->integer
!= 0;
179 // create new node (AstNode constructor)
180 // (the optional child arguments make it easier to create AST trees)
181 AstNode::AstNode(AstNodeType type
, AstNode
*child1
, AstNode
*child2
)
183 static unsigned int hashidx_count
= 123456789;
184 hashidx_count
= mkhash_xorshift(hashidx_count
);
185 hashidx_
= hashidx_count
;
188 filename
= current_filename
;
189 linenum
= get_line_num();
196 range_swapped
= false;
206 children
.push_back(child1
);
208 children
.push_back(child2
);
211 // create a (deep recursive) copy of a node
212 AstNode
*AstNode::clone()
214 AstNode
*that
= new AstNode
;
216 for (auto &it
: that
->children
)
218 for (auto &it
: that
->attributes
)
219 it
.second
= it
.second
->clone();
223 // create a (deep recursive) copy of a node use 'other' as target root node
224 void AstNode::cloneInto(AstNode
*other
)
226 AstNode
*tmp
= clone();
227 other
->delete_children();
229 tmp
->children
.clear();
230 tmp
->attributes
.clear();
234 // delete all children in this node
235 void AstNode::delete_children()
237 for (auto &it
: children
)
241 for (auto &it
: attributes
)
246 // AstNode destructor
252 // create a nice text representation of the node
253 // (traverse tree by recursion, use 'other' pointer for diffing two AST trees)
254 void AstNode::dumpAst(FILE *f
, std::string indent
)
257 for (auto f
: log_files
)
262 std::string type_name
= type2str(type
);
263 fprintf(f
, "%s%s <%s:%d>", indent
.c_str(), type_name
.c_str(), filename
.c_str(), linenum
);
266 fprintf(f
, " [%p -> %p]", this, id2ast
);
268 fprintf(f
, " [%p]", this);
271 fprintf(f
, " str='%s'", str
.c_str());
273 fprintf(f
, " bits='");
274 for (size_t i
= bits
.size(); i
> 0; i
--)
275 fprintf(f
, "%c", bits
[i
-1] == RTLIL::S0
? '0' :
276 bits
[i
-1] == RTLIL::S1
? '1' :
277 bits
[i
-1] == RTLIL::Sx
? 'x' :
278 bits
[i
-1] == RTLIL::Sz
? 'z' : '?');
279 fprintf(f
, "'(%d)", GetSize(bits
));
282 fprintf(f
, " input");
284 fprintf(f
, " output");
288 fprintf(f
, " signed");
290 fprintf(f
, " port=%d", port_id
);
291 if (range_valid
|| range_left
!= -1 || range_right
!= 0)
292 fprintf(f
, " %srange=[%d:%d]%s", range_swapped
? "swapped_" : "", range_left
, range_right
, range_valid
? "" : "!");
294 fprintf(f
, " int=%u", (int)integer
);
296 fprintf(f
, " real=%e", realvalue
);
297 if (!multirange_dimensions
.empty()) {
298 fprintf(f
, " multirange=[");
299 for (int v
: multirange_dimensions
)
300 fprintf(f
, " %d", v
);
305 for (auto &it
: attributes
) {
306 fprintf(f
, "%s ATTR %s:\n", indent
.c_str(), it
.first
.c_str());
307 it
.second
->dumpAst(f
, indent
+ " ");
310 for (size_t i
= 0; i
< children
.size(); i
++)
311 children
[i
]->dumpAst(f
, indent
+ " ");
314 // helper function for AstNode::dumpVlog()
315 static std::string
id2vl(std::string txt
)
317 if (txt
.size() > 1 && txt
[0] == '\\')
319 for (size_t i
= 0; i
< txt
.size(); i
++) {
320 if ('A' <= txt
[i
] && txt
[i
] <= 'Z') continue;
321 if ('a' <= txt
[i
] && txt
[i
] <= 'z') continue;
322 if ('0' <= txt
[i
] && txt
[i
] <= '9') continue;
323 if (txt
[i
] == '_') continue;
324 txt
= "\\" + txt
+ " ";
330 // dump AST node as verilog pseudo-code
331 void AstNode::dumpVlog(FILE *f
, std::string indent
)
335 std::vector
<AstNode
*> rem_children1
, rem_children2
;
338 for (auto f
: log_files
)
343 for (auto &it
: attributes
) {
344 fprintf(f
, "%s" "(* %s = ", indent
.c_str(), id2vl(it
.first
.str()).c_str());
345 it
.second
->dumpVlog(f
, "");
346 fprintf(f
, " *)%s", indent
.empty() ? "" : "\n");
352 fprintf(f
, "%s" "module %s(", indent
.c_str(), id2vl(str
).c_str());
353 for (auto child
: children
)
354 if (child
->type
== AST_WIRE
&& (child
->is_input
|| child
->is_output
)) {
355 fprintf(f
, "%s%s", first
? "" : ", ", id2vl(child
->str
).c_str());
360 for (auto child
: children
)
361 if (child
->type
== AST_PARAMETER
|| child
->type
== AST_LOCALPARAM
|| child
->type
== AST_DEFPARAM
)
362 child
->dumpVlog(f
, indent
+ " ");
364 rem_children1
.push_back(child
);
366 for (auto child
: rem_children1
)
367 if (child
->type
== AST_WIRE
|| child
->type
== AST_AUTOWIRE
|| child
->type
== AST_MEMORY
)
368 child
->dumpVlog(f
, indent
+ " ");
370 rem_children2
.push_back(child
);
371 rem_children1
.clear();
373 for (auto child
: rem_children2
)
374 if (child
->type
== AST_TASK
|| child
->type
== AST_FUNCTION
)
375 child
->dumpVlog(f
, indent
+ " ");
377 rem_children1
.push_back(child
);
378 rem_children2
.clear();
380 for (auto child
: rem_children1
)
381 child
->dumpVlog(f
, indent
+ " ");
382 rem_children1
.clear();
384 fprintf(f
, "%s" "endmodule\n", indent
.c_str());
388 if (is_input
&& is_output
)
389 fprintf(f
, "%s" "inout", indent
.c_str());
391 fprintf(f
, "%s" "input", indent
.c_str());
393 fprintf(f
, "%s" "output", indent
.c_str());
395 fprintf(f
, "%s" "wire", indent
.c_str());
397 fprintf(f
, "%s" "reg", (is_input
|| is_output
) ? " " : indent
.c_str());
399 fprintf(f
, " signed");
400 for (auto child
: children
) {
402 child
->dumpVlog(f
, "");
404 fprintf(f
, " %s", id2vl(str
).c_str());
409 fprintf(f
, "%s" "memory", indent
.c_str());
411 fprintf(f
, " signed");
412 for (auto child
: children
) {
414 child
->dumpVlog(f
, "");
416 fprintf(f
, " %s", id2vl(str
).c_str());
424 fprintf(f
, "[%d:%d]", range_left
, range_right
);
426 for (auto child
: children
) {
427 fprintf(f
, "%c", first
? '[' : ':');
428 child
->dumpVlog(f
, "");
436 fprintf(f
, "%s" "always @(", indent
.c_str());
437 for (auto child
: children
) {
438 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
442 child
->dumpVlog(f
, "");
446 for (auto child
: children
) {
447 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
448 child
->dumpVlog(f
, indent
+ " ");
453 fprintf(f
, "%s" "initial\n", indent
.c_str());
454 for (auto child
: children
) {
455 if (child
->type
!= AST_POSEDGE
&& child
->type
!= AST_NEGEDGE
&& child
->type
!= AST_EDGE
)
456 child
->dumpVlog(f
, indent
+ " ");
463 if (type
== AST_POSEDGE
)
464 fprintf(f
, "posedge ");
465 if (type
== AST_NEGEDGE
)
466 fprintf(f
, "negedge ");
467 for (auto child
: children
)
468 child
->dumpVlog(f
, "");
472 fprintf(f
, "%s", id2vl(str
).c_str());
473 for (auto child
: children
)
474 child
->dumpVlog(f
, "");
479 fprintf(f
, "\"%s\"", str
.c_str());
480 else if (bits
.size() == 32)
481 fprintf(f
, "%d", RTLIL::Const(bits
).as_int());
483 fprintf(f
, "%d'b %s", GetSize(bits
), RTLIL::Const(bits
).as_string().c_str());
487 fprintf(f
, "%e", realvalue
);
491 if (children
.size() == 1) {
492 children
[0]->dumpVlog(f
, indent
);
494 fprintf(f
, "%s" "begin\n", indent
.c_str());
495 for (auto child
: children
)
496 child
->dumpVlog(f
, indent
+ " ");
497 fprintf(f
, "%s" "end\n", indent
.c_str());
502 fprintf(f
, "%s" "case (", indent
.c_str());
503 children
[0]->dumpVlog(f
, "");
505 for (size_t i
= 1; i
< children
.size(); i
++) {
506 AstNode
*child
= children
[i
];
507 child
->dumpVlog(f
, indent
+ " ");
509 fprintf(f
, "%s" "endcase\n", indent
.c_str());
513 for (auto child
: children
) {
514 if (child
->type
== AST_BLOCK
) {
516 child
->dumpVlog(f
, indent
+ " ");
519 fprintf(f
, "%s", first
? indent
.c_str() : ", ");
520 if (child
->type
== AST_DEFAULT
)
521 fprintf(f
, "default");
523 child
->dumpVlog(f
, "");
531 fprintf(f
, "%s", indent
.c_str());
532 children
[0]->dumpVlog(f
, "");
533 fprintf(f
, " %s ", type
== AST_ASSIGN_EQ
? "=" : "<=");
534 children
[1]->dumpVlog(f
, "");
540 for (auto child
: children
) {
543 child
->dumpVlog(f
, "");
551 children
[0]->dumpVlog(f
, "");
553 children
[1]->dumpVlog(f
, "");
557 if (0) { case AST_BIT_NOT
: txt
= "~"; }
558 if (0) { case AST_REDUCE_AND
: txt
= "&"; }
559 if (0) { case AST_REDUCE_OR
: txt
= "|"; }
560 if (0) { case AST_REDUCE_XOR
: txt
= "^"; }
561 if (0) { case AST_REDUCE_XNOR
: txt
= "~^"; }
562 if (0) { case AST_REDUCE_BOOL
: txt
= "|"; }
563 if (0) { case AST_POS
: txt
= "+"; }
564 if (0) { case AST_NEG
: txt
= "-"; }
565 if (0) { case AST_LOGIC_NOT
: txt
= "!"; }
566 fprintf(f
, "%s(", txt
.c_str());
567 children
[0]->dumpVlog(f
, "");
571 if (0) { case AST_BIT_AND
: txt
= "&"; }
572 if (0) { case AST_BIT_OR
: txt
= "|"; }
573 if (0) { case AST_BIT_XOR
: txt
= "^"; }
574 if (0) { case AST_BIT_XNOR
: txt
= "~^"; }
575 if (0) { case AST_SHIFT_LEFT
: txt
= "<<"; }
576 if (0) { case AST_SHIFT_RIGHT
: txt
= ">>"; }
577 if (0) { case AST_SHIFT_SLEFT
: txt
= "<<<"; }
578 if (0) { case AST_SHIFT_SRIGHT
: txt
= ">>>"; }
579 if (0) { case AST_LT
: txt
= "<"; }
580 if (0) { case AST_LE
: txt
= "<="; }
581 if (0) { case AST_EQ
: txt
= "=="; }
582 if (0) { case AST_NE
: txt
= "!="; }
583 if (0) { case AST_EQX
: txt
= "==="; }
584 if (0) { case AST_NEX
: txt
= "!=="; }
585 if (0) { case AST_GE
: txt
= ">="; }
586 if (0) { case AST_GT
: txt
= ">"; }
587 if (0) { case AST_ADD
: txt
= "+"; }
588 if (0) { case AST_SUB
: txt
= "-"; }
589 if (0) { case AST_MUL
: txt
= "*"; }
590 if (0) { case AST_DIV
: txt
= "/"; }
591 if (0) { case AST_MOD
: txt
= "%"; }
592 if (0) { case AST_POW
: txt
= "**"; }
593 if (0) { case AST_LOGIC_AND
: txt
= "&&"; }
594 if (0) { case AST_LOGIC_OR
: txt
= "||"; }
596 children
[0]->dumpVlog(f
, "");
597 fprintf(f
, ")%s(", txt
.c_str());
598 children
[1]->dumpVlog(f
, "");
604 children
[0]->dumpVlog(f
, "");
606 children
[1]->dumpVlog(f
, "");
608 children
[2]->dumpVlog(f
, "");
613 std::string type_name
= type2str(type
);
614 fprintf(f
, "%s" "/** %s **/%s", indent
.c_str(), type_name
.c_str(), indent
.empty() ? "" : "\n");
615 // dumpAst(f, indent, NULL);
619 // check if two AST nodes are identical
620 bool AstNode::operator==(const AstNode
&other
) const
622 if (type
!= other
.type
)
624 if (children
.size() != other
.children
.size())
626 if (str
!= other
.str
)
628 if (bits
!= other
.bits
)
630 if (is_input
!= other
.is_input
)
632 if (is_output
!= other
.is_output
)
634 if (is_reg
!= other
.is_reg
)
636 if (is_signed
!= other
.is_signed
)
638 if (is_string
!= other
.is_string
)
640 if (range_valid
!= other
.range_valid
)
642 if (range_swapped
!= other
.range_swapped
)
644 if (port_id
!= other
.port_id
)
646 if (range_left
!= other
.range_left
)
648 if (range_right
!= other
.range_right
)
650 if (integer
!= other
.integer
)
652 for (size_t i
= 0; i
< children
.size(); i
++)
653 if (*children
[i
] != *other
.children
[i
])
658 // check if two AST nodes are not identical
659 bool AstNode::operator!=(const AstNode
&other
) const
661 return !(*this == other
);
664 // check if this AST contains the given node
665 bool AstNode::contains(const AstNode
*other
) const
669 for (auto child
: children
)
670 if (child
->contains(other
))
675 // create an AST node for a constant (using a 32 bit int as value)
676 AstNode
*AstNode::mkconst_int(uint32_t v
, bool is_signed
, int width
)
678 AstNode
*node
= new AstNode(AST_CONSTANT
);
680 node
->is_signed
= is_signed
;
681 for (int i
= 0; i
< width
; i
++) {
682 node
->bits
.push_back((v
& 1) ? RTLIL::S1
: RTLIL::S0
);
685 node
->range_valid
= true;
686 node
->range_left
= width
-1;
687 node
->range_right
= 0;
691 // create an AST node for a constant (using a bit vector as value)
692 AstNode
*AstNode::mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
)
694 AstNode
*node
= new AstNode(AST_CONSTANT
);
695 node
->is_signed
= is_signed
;
697 for (size_t i
= 0; i
< 32; i
++) {
698 if (i
< node
->bits
.size())
699 node
->integer
|= (node
->bits
[i
] == RTLIL::S1
) << i
;
701 node
->integer
|= (node
->bits
.back() == RTLIL::S1
) << i
;
703 node
->range_valid
= true;
704 node
->range_left
= node
->bits
.size()-1;
705 node
->range_right
= 0;
709 // create an AST node for a constant (using a string in bit vector form as value)
710 AstNode
*AstNode::mkconst_str(const std::vector
<RTLIL::State
> &v
)
712 AstNode
*node
= mkconst_str(RTLIL::Const(v
).decode_string());
713 while (GetSize(node
->bits
) < GetSize(v
))
714 node
->bits
.push_back(RTLIL::State::S0
);
715 log_assert(node
->bits
== v
);
719 // create an AST node for a constant (using a string as value)
720 AstNode
*AstNode::mkconst_str(const std::string
&str
)
722 std::vector
<RTLIL::State
> data
;
723 data
.reserve(str
.size() * 8);
724 for (size_t i
= 0; i
< str
.size(); i
++) {
725 unsigned char ch
= str
[str
.size() - i
- 1];
726 for (int j
= 0; j
< 8; j
++) {
727 data
.push_back((ch
& 1) ? RTLIL::S1
: RTLIL::S0
);
731 AstNode
*node
= AstNode::mkconst_bits(data
, false);
732 node
->is_string
= true;
737 bool AstNode::bits_only_01()
739 for (auto bit
: bits
)
740 if (bit
!= RTLIL::S0
&& bit
!= RTLIL::S1
)
745 RTLIL::Const
AstNode::bitsAsConst(int width
, bool is_signed
)
747 std::vector
<RTLIL::State
> bits
= this->bits
;
748 if (width
>= 0 && width
< int(bits
.size()))
750 if (width
>= 0 && width
> int(bits
.size())) {
751 RTLIL::State extbit
= RTLIL::State::S0
;
752 if (is_signed
&& !bits
.empty())
753 extbit
= bits
.back();
754 while (width
> int(bits
.size()))
755 bits
.push_back(extbit
);
757 return RTLIL::Const(bits
);
760 RTLIL::Const
AstNode::bitsAsConst(int width
)
762 return bitsAsConst(width
, is_signed
);
765 RTLIL::Const
AstNode::asAttrConst()
767 log_assert(type
== AST_CONSTANT
);
773 val
.flags
|= RTLIL::CONST_FLAG_STRING
;
774 log_assert(val
.decode_string() == str
);
780 RTLIL::Const
AstNode::asParaConst()
782 RTLIL::Const val
= asAttrConst();
784 val
.flags
|= RTLIL::CONST_FLAG_SIGNED
;
788 bool AstNode::asBool()
790 log_assert(type
== AST_CONSTANT
);
791 for (auto &bit
: bits
)
792 if (bit
== RTLIL::State::S1
)
797 int AstNode::isConst()
799 if (type
== AST_CONSTANT
)
801 if (type
== AST_REALVALUE
)
806 uint64_t AstNode::asInt(bool is_signed
)
808 if (type
== AST_CONSTANT
)
810 RTLIL::Const v
= bitsAsConst(64, is_signed
);
813 for (int i
= 0; i
< 64; i
++)
814 if (v
.bits
.at(i
) == RTLIL::State::S1
)
815 ret
|= uint64_t(1) << i
;
820 if (type
== AST_REALVALUE
)
826 double AstNode::asReal(bool is_signed
)
828 if (type
== AST_CONSTANT
)
830 RTLIL::Const
val(bits
);
832 bool is_negative
= is_signed
&& val
.bits
.back() == RTLIL::State::S1
;
834 val
= const_neg(val
, val
, false, false, val
.bits
.size());
837 for (size_t i
= 0; i
< val
.bits
.size(); i
++)
838 // IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
839 // the net or the variable shall be treated as zero upon conversion.
840 if (val
.bits
.at(i
) == RTLIL::State::S1
)
848 if (type
== AST_REALVALUE
)
854 RTLIL::Const
AstNode::realAsConst(int width
)
856 double v
= round(realvalue
);
861 if (!std::isfinite(v
)) {
863 result
.bits
= std::vector
<RTLIL::State
>(width
, RTLIL::State::Sx
);
865 bool is_negative
= v
< 0;
868 for (int i
= 0; i
< width
; i
++, v
/= 2)
869 result
.bits
.push_back((fmod(floor(v
), 2) != 0) ? RTLIL::State::S1
: RTLIL::State::S0
);
871 result
= const_neg(result
, result
, false, false, result
.bits
.size());
876 // create a new AstModule from an AST_MODULE AST node
877 static AstModule
* process_module(AstNode
*ast
, bool defer
)
879 log_assert(ast
->type
== AST_MODULE
);
882 log("Storing AST representation for module `%s'.\n", ast
->str
.c_str());
884 log("Generating RTLIL representation for module `%s'.\n", ast
->str
.c_str());
886 current_module
= new AstModule
;
887 current_module
->ast
= NULL
;
888 current_module
->name
= ast
->str
;
889 current_module
->attributes
["\\src"] = stringf("%s:%d", ast
->filename
.c_str(), ast
->linenum
);
891 current_ast_mod
= ast
;
892 AstNode
*ast_before_simplify
= ast
->clone();
894 if (flag_dump_ast1
) {
895 log("Dumping verilog AST before simplification:\n");
896 ast
->dumpAst(NULL
, " ");
897 log("--- END OF AST DUMP ---\n");
902 while (ast
->simplify(!flag_noopt
, false, false, 0, -1, false, false)) { }
904 if (flag_dump_ast2
) {
905 log("Dumping verilog AST after simplification:\n");
906 ast
->dumpAst(NULL
, " ");
907 log("--- END OF AST DUMP ---\n");
910 if (flag_dump_vlog
) {
911 log("Dumping verilog AST (as requested by dump_vlog option):\n");
912 ast
->dumpVlog(NULL
, " ");
913 log("--- END OF AST DUMP ---\n");
917 std::vector
<AstNode
*> new_children
;
918 for (auto child
: ast
->children
) {
919 if (child
->type
== AST_WIRE
&& (child
->is_input
|| child
->is_output
))
920 new_children
.push_back(child
);
924 ast
->children
.swap(new_children
);
925 ast
->attributes
["\\blackbox"] = AstNode::mkconst_int(1, false);
928 ignoreThisSignalsInInitial
= RTLIL::SigSpec();
930 for (auto &attr
: ast
->attributes
) {
931 if (attr
.second
->type
!= AST_CONSTANT
)
932 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
933 attr
.first
.c_str(), ast
->filename
.c_str(), ast
->linenum
);
934 current_module
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
936 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
937 AstNode
*node
= ast
->children
[i
];
938 if (node
->type
== AST_WIRE
|| node
->type
== AST_MEMORY
)
941 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
942 AstNode
*node
= ast
->children
[i
];
943 if (node
->type
!= AST_WIRE
&& node
->type
!= AST_MEMORY
&& node
->type
!= AST_INITIAL
)
947 ignoreThisSignalsInInitial
.sort_and_unify();
949 for (size_t i
= 0; i
< ast
->children
.size(); i
++) {
950 AstNode
*node
= ast
->children
[i
];
951 if (node
->type
== AST_INITIAL
)
955 ignoreThisSignalsInInitial
= RTLIL::SigSpec();
958 current_module
->ast
= ast_before_simplify
;
959 current_module
->nolatches
= flag_nolatches
;
960 current_module
->nomem2reg
= flag_nomem2reg
;
961 current_module
->mem2reg
= flag_mem2reg
;
962 current_module
->lib
= flag_lib
;
963 current_module
->noopt
= flag_noopt
;
964 current_module
->icells
= flag_icells
;
965 current_module
->autowire
= flag_autowire
;
966 current_module
->fixup_ports();
967 return current_module
;
970 // create AstModule instances for all modules in the AST tree and add them to 'design'
971 void AST::process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast1
, bool dump_ast2
, bool dump_vlog
, bool nolatches
, bool nomem2reg
, bool mem2reg
, bool lib
, bool noopt
, bool icells
, bool ignore_redef
, bool defer
, bool autowire
)
974 flag_dump_ast1
= dump_ast1
;
975 flag_dump_ast2
= dump_ast2
;
976 flag_dump_vlog
= dump_vlog
;
977 flag_nolatches
= nolatches
;
978 flag_nomem2reg
= nomem2reg
;
979 flag_mem2reg
= mem2reg
;
982 flag_icells
= icells
;
983 flag_autowire
= autowire
;
985 std::vector
<AstNode
*> global_decls
;
987 log_assert(current_ast
->type
== AST_DESIGN
);
988 for (auto it
= current_ast
->children
.begin(); it
!= current_ast
->children
.end(); it
++)
990 if ((*it
)->type
== AST_MODULE
)
992 for (auto n
: global_decls
)
993 (*it
)->children
.push_back(n
->clone());
995 if (flag_icells
&& (*it
)->str
.substr(0, 2) == "\\$")
996 (*it
)->str
= (*it
)->str
.substr(1);
999 (*it
)->str
= "$abstract" + (*it
)->str
;
1001 if (design
->has((*it
)->str
)) {
1003 log_error("Re-definition of module `%s' at %s:%d!\n",
1004 (*it
)->str
.c_str(), (*it
)->filename
.c_str(), (*it
)->linenum
);
1005 log("Ignoring re-definition of module `%s' at %s:%d!\n",
1006 (*it
)->str
.c_str(), (*it
)->filename
.c_str(), (*it
)->linenum
);
1010 design
->add(process_module(*it
, defer
));
1013 global_decls
.push_back(*it
);
1017 // AstModule destructor
1018 AstModule::~AstModule()
1024 // create a new parametric module (when needed) and return the name of the generated module
1025 RTLIL::IdString
AstModule::derive(RTLIL::Design
*design
, dict
<RTLIL::IdString
, RTLIL::Const
> parameters
)
1027 std::string stripped_name
= name
.str();
1029 if (stripped_name
.substr(0, 9) == "$abstract")
1030 stripped_name
= stripped_name
.substr(9);
1032 log_header("Executing AST frontend in derive mode using pre-parsed AST for module `%s'.\n", stripped_name
.c_str());
1035 flag_dump_ast1
= false;
1036 flag_dump_ast2
= false;
1037 flag_dump_vlog
= false;
1038 flag_nolatches
= nolatches
;
1039 flag_nomem2reg
= nomem2reg
;
1040 flag_mem2reg
= mem2reg
;
1043 flag_icells
= icells
;
1044 flag_autowire
= autowire
;
1045 use_internal_line_num();
1047 std::string para_info
;
1048 AstNode
*new_ast
= ast
->clone();
1050 int para_counter
= 0;
1051 int orig_parameters_n
= parameters
.size();
1052 for (auto it
= new_ast
->children
.begin(); it
!= new_ast
->children
.end(); it
++) {
1053 AstNode
*child
= *it
;
1054 if (child
->type
!= AST_PARAMETER
)
1057 std::string para_id
= child
->str
;
1058 if (parameters
.count(para_id
) > 0) {
1059 log("Parameter %s = %s\n", child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[child
->str
])));
1061 para_info
+= stringf("%s=%s", child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[para_id
])));
1062 delete child
->children
.at(0);
1063 child
->children
[0] = AstNode::mkconst_bits(parameters
[para_id
].bits
, (parameters
[para_id
].flags
& RTLIL::CONST_FLAG_SIGNED
) != 0);
1064 parameters
.erase(para_id
);
1067 para_id
= stringf("$%d", para_counter
);
1068 if (parameters
.count(para_id
) > 0) {
1069 log("Parameter %d (%s) = %s\n", para_counter
, child
->str
.c_str(), log_signal(RTLIL::SigSpec(parameters
[para_id
])));
1070 goto rewrite_parameter
;
1073 if (parameters
.size() > 0)
1074 log_error("Requested parameter `%s' does not exist in module `%s'!\n", parameters
.begin()->first
.c_str(), stripped_name
.c_str());
1076 std::string modname
;
1078 if (orig_parameters_n
== 0)
1079 modname
= stripped_name
;
1080 else if (para_info
.size() > 60)
1081 modname
= "$paramod$" + sha1(para_info
) + stripped_name
;
1083 modname
= "$paramod" + stripped_name
+ para_info
;
1085 if (!design
->has(modname
)) {
1086 new_ast
->str
= modname
;
1087 design
->add(process_module(new_ast
, false));
1088 design
->module(modname
)->check();
1090 log("Found cached RTLIL representation for module `%s'.\n", modname
.c_str());
1097 RTLIL::Module
*AstModule::clone() const
1099 AstModule
*new_mod
= new AstModule
;
1100 new_mod
->name
= name
;
1103 new_mod
->ast
= ast
->clone();
1104 new_mod
->nolatches
= nolatches
;
1105 new_mod
->nomem2reg
= nomem2reg
;
1106 new_mod
->mem2reg
= mem2reg
;
1108 new_mod
->noopt
= noopt
;
1109 new_mod
->icells
= icells
;
1110 new_mod
->autowire
= autowire
;
1115 // internal dummy line number callbacks
1117 int internal_line_num
;
1118 void internal_set_line_num(int n
) {
1119 internal_line_num
= n
;
1121 int internal_get_line_num() {
1122 return internal_line_num
;
1126 // use internal dummy line number callbacks
1127 void AST::use_internal_line_num()
1129 set_line_num
= &internal_set_line_num
;
1130 get_line_num
= &internal_get_line_num
;