2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
32 #include "kernel/rtlil.h"
40 // all node types, type2str() must be extended
41 // whenever a new node type is added here
148 AST_INTERFACEPORTTYPE
,
154 // convert an node type to a string (e.g. for debug output)
155 std::string
type2str(AstNodeType type
);
157 // The AST is built using instances of this struct
160 // for dict<> and pool<>
161 unsigned int hashidx_
;
162 unsigned int hash() const { return hashidx_
; }
167 // the list of child nodes for this node
168 std::vector
<AstNode
*> children
;
170 // the list of attributes assigned to this node
171 std::map
<RTLIL::IdString
, AstNode
*> attributes
;
172 bool get_bool_attribute(RTLIL::IdString id
);
174 // node content - most of it is unused in most node types
176 std::vector
<RTLIL::State
> bits
;
177 bool is_input
, is_output
, is_reg
, is_logic
, is_signed
, is_string
, is_wand
, is_wor
, range_valid
, range_swapped
, was_checked
, is_unsized
;
178 int port_id
, range_left
, range_right
;
182 // if this is a multirange memory then this vector contains offset and length of each dimension
183 std::vector
<int> multirange_dimensions
;
185 // this is set by simplify and used during RTLIL generation
188 // this is used by simplify to detect if basic analysis has been performed already on the node
191 // this is the original sourcecode location that resulted in this AST node
192 // it is automatically set by the constructor using AST::current_filename and
193 // the AST::get_line_num() callback function.
194 std::string filename
;
197 // creating and deleting nodes
198 AstNode(AstNodeType type
= AST_NONE
, AstNode
*child1
= NULL
, AstNode
*child2
= NULL
, AstNode
*child3
= NULL
);
199 AstNode
*clone() const;
200 void cloneInto(AstNode
*other
) const;
201 void delete_children();
207 MEM2REG_FL_ALL
= 0x00000001,
208 MEM2REG_FL_ASYNC
= 0x00000002,
209 MEM2REG_FL_INIT
= 0x00000004,
211 /* candidate flags */
212 MEM2REG_FL_FORCED
= 0x00000100,
213 MEM2REG_FL_SET_INIT
= 0x00000200,
214 MEM2REG_FL_SET_ELSE
= 0x00000400,
215 MEM2REG_FL_SET_ASYNC
= 0x00000800,
216 MEM2REG_FL_EQ2
= 0x00001000,
217 MEM2REG_FL_CMPLX_LHS
= 0x00002000,
218 MEM2REG_FL_CONST_LHS
= 0x00004000,
219 MEM2REG_FL_VAR_LHS
= 0x00008000,
222 MEM2REG_FL_EQ1
= 0x01000000,
225 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
226 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
227 bool simplify(bool const_fold
, bool at_zero
, bool in_lvalue
, int stage
, int width_hint
, bool sign_hint
, bool in_param
);
228 AstNode
*readmem(bool is_readmemh
, std::string mem_filename
, AstNode
*memory
, int start_addr
, int finish_addr
, bool unconditional_init
);
229 void expand_genblock(std::string index_var
, std::string prefix
, std::map
<std::string
, std::string
> &name_map
);
230 void replace_ids(const std::string
&prefix
, const std::map
<std::string
, std::string
> &rules
);
231 void mem2reg_as_needed_pass1(dict
<AstNode
*, pool
<std::string
>> &mem2reg_places
,
232 dict
<AstNode
*, uint32_t> &mem2reg_flags
, dict
<AstNode
*, uint32_t> &proc_flags
, uint32_t &status_flags
);
233 bool mem2reg_as_needed_pass2(pool
<AstNode
*> &mem2reg_set
, AstNode
*mod
, AstNode
*block
, AstNode
*&async_block
);
234 bool mem2reg_check(pool
<AstNode
*> &mem2reg_set
);
235 void mem2reg_remove(pool
<AstNode
*> &mem2reg_set
, vector
<AstNode
*> &delnodes
);
236 void meminfo(int &mem_width
, int &mem_size
, int &addr_bits
);
238 // additional functionality for evaluating constant functions
239 struct varinfo_t
{ RTLIL::Const val
; int offset
; bool is_signed
; };
240 bool has_const_only_constructs(bool &recommend_const_eval
);
241 void replace_variables(std::map
<std::string
, varinfo_t
> &variables
, AstNode
*fcall
);
242 AstNode
*eval_const_function(AstNode
*fcall
);
243 bool is_simple_const_expr();
245 // create a human-readable text representation of the AST (for debugging)
246 void dumpAst(FILE *f
, std::string indent
) const;
247 void dumpVlog(FILE *f
, std::string indent
) const;
249 // used by genRTLIL() for detecting expression width and sign
250 void detectSignWidthWorker(int &width_hint
, bool &sign_hint
, bool *found_real
= NULL
);
251 void detectSignWidth(int &width_hint
, bool &sign_hint
, bool *found_real
= NULL
);
253 // create RTLIL code for this AST node
254 // for expressions the resulting signal vector is returned
255 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
256 RTLIL::SigSpec
genRTLIL(int width_hint
= -1, bool sign_hint
= false);
257 RTLIL::SigSpec
genWidthRTLIL(int width
, const dict
<RTLIL::SigBit
, RTLIL::SigBit
> *new_subst_ptr
= NULL
);
260 bool operator==(const AstNode
&other
) const;
261 bool operator!=(const AstNode
&other
) const;
262 bool contains(const AstNode
*other
) const;
264 // helper functions for creating AST nodes for constants
265 static AstNode
*mkconst_int(uint32_t v
, bool is_signed
, int width
= 32);
266 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
, bool is_unsized
);
267 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
);
268 static AstNode
*mkconst_str(const std::vector
<RTLIL::State
> &v
);
269 static AstNode
*mkconst_str(const std::string
&str
);
271 // helper function for creating sign-extended const objects
272 RTLIL::Const
bitsAsConst(int width
, bool is_signed
);
273 RTLIL::Const
bitsAsConst(int width
= -1);
274 RTLIL::Const
bitsAsUnsizedConst(int width
);
275 RTLIL::Const
asAttrConst();
276 RTLIL::Const
asParaConst();
277 uint64_t asInt(bool is_signed
);
278 bool bits_only_01() const;
281 // helper functions for real valued const eval
282 int isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
283 double asReal(bool is_signed
);
284 RTLIL::Const
realAsConst(int width
);
287 // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
288 void process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast1
, bool dump_ast2
, bool no_dump_ptr
, bool dump_vlog1
, bool dump_vlog2
, bool dump_rtlil
, bool nolatches
, bool nomeminit
,
289 bool nomem2reg
, bool mem2reg
, bool noblackbox
, bool lib
, bool nowb
, bool noopt
, bool icells
, bool pwires
, bool nooverwrite
, bool overwrite
, bool defer
, bool autowire
);
291 // parametric modules are supported directly by the AST library
292 // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
293 struct AstModule
: RTLIL::Module
{
295 bool nolatches
, nomeminit
, nomem2reg
, mem2reg
, noblackbox
, lib
, nowb
, noopt
, icells
, pwires
, autowire
;
296 ~AstModule() YS_OVERRIDE
;
297 RTLIL::IdString
derive(RTLIL::Design
*design
, dict
<RTLIL::IdString
, RTLIL::Const
> parameters
, bool mayfail
) YS_OVERRIDE
;
298 RTLIL::IdString
derive(RTLIL::Design
*design
, dict
<RTLIL::IdString
, RTLIL::Const
> parameters
, dict
<RTLIL::IdString
, RTLIL::Module
*> interfaces
, dict
<RTLIL::IdString
, RTLIL::IdString
> modports
, bool mayfail
) YS_OVERRIDE
;
299 std::string
derive_common(RTLIL::Design
*design
, dict
<RTLIL::IdString
, RTLIL::Const
> parameters
, AstNode
**new_ast_out
, bool mayfail
);
300 void reprocess_module(RTLIL::Design
*design
, dict
<RTLIL::IdString
, RTLIL::Module
*> local_interfaces
) YS_OVERRIDE
;
301 RTLIL::Module
*clone() const YS_OVERRIDE
;
302 void loadconfig() const;
305 // this must be set by the language frontend before parsing the sources
306 // the AstNode constructor then uses current_filename and get_line_num()
307 // to initialize the filename and linenum properties of new nodes
308 extern std::string current_filename
;
309 extern void (*set_line_num
)(int);
310 extern int (*get_line_num
)();
312 // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
313 // to control the filename and linenum properties of new nodes not generated by a frontend parser)
314 void use_internal_line_num();
316 // call a DPI function
317 AstNode
*dpi_call(const std::string
&rtype
, const std::string
&fname
, const std::vector
<std::string
> &argtypes
, const std::vector
<AstNode
*> &args
);
319 // Helper functions related to handling SystemVerilog interfaces
320 std::pair
<std::string
,std::string
> split_modport_from_type(std::string name_type
);
321 AstNode
* find_modport(AstNode
*intf
, std::string name
);
322 void explode_interface_port(AstNode
*module_ast
, RTLIL::Module
* intfmodule
, std::string intfname
, AstNode
*modport
);
325 namespace AST_INTERNAL
327 // internal state variables
328 extern bool flag_dump_ast1
, flag_dump_ast2
, flag_no_dump_ptr
, flag_dump_rtlil
, flag_nolatches
, flag_nomeminit
;
329 extern bool flag_nomem2reg
, flag_mem2reg
, flag_lib
, flag_noopt
, flag_icells
, flag_pwires
, flag_autowire
;
330 extern AST::AstNode
*current_ast
, *current_ast_mod
;
331 extern std::map
<std::string
, AST::AstNode
*> current_scope
;
332 extern const dict
<RTLIL::SigBit
, RTLIL::SigBit
> *genRTLIL_subst_ptr
;
333 extern RTLIL::SigSpec ignoreThisSignalsInInitial
;
334 extern AST::AstNode
*current_always
, *current_top_block
, *current_block
, *current_block_child
;
335 extern AST::AstModule
*current_module
;
336 extern bool current_always_clocked
;
337 struct ProcessGenerator
;