2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
32 #include "kernel/rtlil.h"
40 // all node types, type2str() must be extended
41 // whenever a new node type is added here
150 AST_INTERFACEPORTTYPE
,
159 struct AstSrcLocType
{
160 unsigned int first_line
, last_line
;
161 unsigned int first_column
, last_column
;
162 AstSrcLocType() : first_line(0), last_line(0), first_column(0), last_column(0) {}
163 AstSrcLocType(int _first_line
, int _first_column
, int _last_line
, int _last_column
) : first_line(_first_line
), last_line(_last_line
), first_column(_first_column
), last_column(_last_column
) {}
166 // convert an node type to a string (e.g. for debug output)
167 std::string
type2str(AstNodeType type
);
169 // The AST is built using instances of this struct
172 // for dict<> and pool<>
173 unsigned int hashidx_
;
174 unsigned int hash() const { return hashidx_
; }
179 // the list of child nodes for this node
180 std::vector
<AstNode
*> children
;
182 // the list of attributes assigned to this node
183 std::map
<RTLIL::IdString
, AstNode
*> attributes
;
184 bool get_bool_attribute(RTLIL::IdString id
);
186 // node content - most of it is unused in most node types
188 std::vector
<RTLIL::State
> bits
;
189 bool is_input
, is_output
, is_reg
, is_logic
, is_signed
, is_string
, is_wand
, is_wor
, range_valid
, range_swapped
, was_checked
, is_unsized
, is_custom_type
;
190 int port_id
, range_left
, range_right
;
193 // set for IDs typed to an enumeration, not used
196 // if this is a multirange memory then this vector contains offset and length of each dimension
197 std::vector
<int> multirange_dimensions
;
199 // this is set by simplify and used during RTLIL generation
202 // this is used by simplify to detect if basic analysis has been performed already on the node
205 // this is the original sourcecode location that resulted in this AST node
206 // it is automatically set by the constructor using AST::current_filename and
207 // the AST::get_line_num() callback function.
208 std::string filename
;
209 AstSrcLocType location
;
211 // creating and deleting nodes
212 AstNode(AstNodeType type
= AST_NONE
, AstNode
*child1
= NULL
, AstNode
*child2
= NULL
, AstNode
*child3
= NULL
);
213 AstNode
*clone() const;
214 void cloneInto(AstNode
*other
) const;
215 void delete_children();
221 MEM2REG_FL_ALL
= 0x00000001,
222 MEM2REG_FL_ASYNC
= 0x00000002,
223 MEM2REG_FL_INIT
= 0x00000004,
225 /* candidate flags */
226 MEM2REG_FL_FORCED
= 0x00000100,
227 MEM2REG_FL_SET_INIT
= 0x00000200,
228 MEM2REG_FL_SET_ELSE
= 0x00000400,
229 MEM2REG_FL_SET_ASYNC
= 0x00000800,
230 MEM2REG_FL_EQ2
= 0x00001000,
231 MEM2REG_FL_CMPLX_LHS
= 0x00002000,
232 MEM2REG_FL_CONST_LHS
= 0x00004000,
233 MEM2REG_FL_VAR_LHS
= 0x00008000,
236 MEM2REG_FL_EQ1
= 0x01000000,
239 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
240 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
241 bool simplify(bool const_fold
, bool at_zero
, bool in_lvalue
, int stage
, int width_hint
, bool sign_hint
, bool in_param
);
242 AstNode
*readmem(bool is_readmemh
, std::string mem_filename
, AstNode
*memory
, int start_addr
, int finish_addr
, bool unconditional_init
);
243 void expand_genblock(std::string index_var
, std::string prefix
, std::map
<std::string
, std::string
> &name_map
);
244 void replace_ids(const std::string
&prefix
, const std::map
<std::string
, std::string
> &rules
);
245 void mem2reg_as_needed_pass1(dict
<AstNode
*, pool
<std::string
>> &mem2reg_places
,
246 dict
<AstNode
*, uint32_t> &mem2reg_flags
, dict
<AstNode
*, uint32_t> &proc_flags
, uint32_t &status_flags
);
247 bool mem2reg_as_needed_pass2(pool
<AstNode
*> &mem2reg_set
, AstNode
*mod
, AstNode
*block
, AstNode
*&async_block
);
248 bool mem2reg_check(pool
<AstNode
*> &mem2reg_set
);
249 void mem2reg_remove(pool
<AstNode
*> &mem2reg_set
, vector
<AstNode
*> &delnodes
);
250 void meminfo(int &mem_width
, int &mem_size
, int &addr_bits
);
252 // additional functionality for evaluating constant functions
253 struct varinfo_t
{ RTLIL::Const val
; int offset
; bool is_signed
; };
254 bool has_const_only_constructs(bool &recommend_const_eval
);
255 void replace_variables(std::map
<std::string
, varinfo_t
> &variables
, AstNode
*fcall
);
256 AstNode
*eval_const_function(AstNode
*fcall
);
257 bool is_simple_const_expr();
258 std::string
process_format_str(const std::string
&sformat
, int next_arg
, int stage
, int width_hint
, bool sign_hint
);
260 // create a human-readable text representation of the AST (for debugging)
261 void dumpAst(FILE *f
, std::string indent
) const;
262 void dumpVlog(FILE *f
, std::string indent
) const;
264 // used by genRTLIL() for detecting expression width and sign
265 void detectSignWidthWorker(int &width_hint
, bool &sign_hint
, bool *found_real
= NULL
);
266 void detectSignWidth(int &width_hint
, bool &sign_hint
, bool *found_real
= NULL
);
268 // create RTLIL code for this AST node
269 // for expressions the resulting signal vector is returned
270 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
271 RTLIL::SigSpec
genRTLIL(int width_hint
= -1, bool sign_hint
= false);
272 RTLIL::SigSpec
genWidthRTLIL(int width
, const dict
<RTLIL::SigBit
, RTLIL::SigBit
> *new_subst_ptr
= NULL
);
275 bool operator==(const AstNode
&other
) const;
276 bool operator!=(const AstNode
&other
) const;
277 bool contains(const AstNode
*other
) const;
279 // helper functions for creating AST nodes for constants
280 static AstNode
*mkconst_int(uint32_t v
, bool is_signed
, int width
= 32);
281 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
, bool is_unsized
);
282 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
);
283 static AstNode
*mkconst_str(const std::vector
<RTLIL::State
> &v
);
284 static AstNode
*mkconst_str(const std::string
&str
);
286 // helper function for creating sign-extended const objects
287 RTLIL::Const
bitsAsConst(int width
, bool is_signed
);
288 RTLIL::Const
bitsAsConst(int width
= -1);
289 RTLIL::Const
bitsAsUnsizedConst(int width
);
290 RTLIL::Const
asAttrConst();
291 RTLIL::Const
asParaConst();
292 uint64_t asInt(bool is_signed
);
293 bool bits_only_01() const;
296 // helper functions for real valued const eval
297 int isConst() const; // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
298 double asReal(bool is_signed
);
299 RTLIL::Const
realAsConst(int width
);
302 void allocateDefaultEnumValues();
305 // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
306 void process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast1
, bool dump_ast2
, bool no_dump_ptr
, bool dump_vlog1
, bool dump_vlog2
, bool dump_rtlil
, bool nolatches
, bool nomeminit
,
307 bool nomem2reg
, bool mem2reg
, bool noblackbox
, bool lib
, bool nowb
, bool noopt
, bool icells
, bool pwires
, bool nooverwrite
, bool overwrite
, bool defer
, bool autowire
);
309 // parametric modules are supported directly by the AST library
310 // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
311 struct AstModule
: RTLIL::Module
{
313 bool nolatches
, nomeminit
, nomem2reg
, mem2reg
, noblackbox
, lib
, nowb
, noopt
, icells
, pwires
, autowire
;
314 ~AstModule() YS_OVERRIDE
;
315 RTLIL::IdString
derive(RTLIL::Design
*design
, const dict
<RTLIL::IdString
, RTLIL::Const
> ¶meters
, bool mayfail
) YS_OVERRIDE
;
316 RTLIL::IdString
derive(RTLIL::Design
*design
, const dict
<RTLIL::IdString
, RTLIL::Const
> ¶meters
, const dict
<RTLIL::IdString
, RTLIL::Module
*> &interfaces
, const dict
<RTLIL::IdString
, RTLIL::IdString
> &modports
, bool mayfail
) YS_OVERRIDE
;
317 std::string
derive_common(RTLIL::Design
*design
, const dict
<RTLIL::IdString
, RTLIL::Const
> ¶meters
, AstNode
**new_ast_out
, bool quiet
= false);
318 void reprocess_module(RTLIL::Design
*design
, const dict
<RTLIL::IdString
, RTLIL::Module
*> &local_interfaces
) YS_OVERRIDE
;
319 RTLIL::Module
*clone() const YS_OVERRIDE
;
320 void loadconfig() const;
323 // this must be set by the language frontend before parsing the sources
324 // the AstNode constructor then uses current_filename and get_line_num()
325 // to initialize the filename and linenum properties of new nodes
326 extern std::string current_filename
;
327 extern void (*set_line_num
)(int);
328 extern int (*get_line_num
)();
330 // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
331 // to control the filename and linenum properties of new nodes not generated by a frontend parser)
332 void use_internal_line_num();
334 // call a DPI function
335 AstNode
*dpi_call(const std::string
&rtype
, const std::string
&fname
, const std::vector
<std::string
> &argtypes
, const std::vector
<AstNode
*> &args
);
337 // Helper functions related to handling SystemVerilog interfaces
338 std::pair
<std::string
,std::string
> split_modport_from_type(std::string name_type
);
339 AstNode
* find_modport(AstNode
*intf
, std::string name
);
340 void explode_interface_port(AstNode
*module_ast
, RTLIL::Module
* intfmodule
, std::string intfname
, AstNode
*modport
);
343 namespace AST_INTERNAL
345 // internal state variables
346 extern bool flag_dump_ast1
, flag_dump_ast2
, flag_no_dump_ptr
, flag_dump_rtlil
, flag_nolatches
, flag_nomeminit
;
347 extern bool flag_nomem2reg
, flag_mem2reg
, flag_lib
, flag_noopt
, flag_icells
, flag_pwires
, flag_autowire
;
348 extern AST::AstNode
*current_ast
, *current_ast_mod
;
349 extern std::map
<std::string
, AST::AstNode
*> current_scope
;
350 extern const dict
<RTLIL::SigBit
, RTLIL::SigBit
> *genRTLIL_subst_ptr
;
351 extern RTLIL::SigSpec ignoreThisSignalsInInitial
;
352 extern AST::AstNode
*current_always
, *current_top_block
, *current_block
, *current_block_child
;
353 extern AST::AstModule
*current_module
;
354 extern bool current_always_clocked
;
355 struct ProcessGenerator
;