frontends/ast/ast.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  This is the AST frontend library.
  21  *
  22  *  The AST frontend library is not a frontend on it's own but provides a
  23  *  generic abstract syntax tree (AST) abstraction for HDL code and can be
  24  *  used by HDL frontends. See "ast.h" for an overview of the API and the
  25  *  Verilog frontend for an usage example.
  26  *
  27  */
  28
  29 #ifndef AST_H
  30 #define AST_H
  31
  32 #include "kernel/rtlil.h"
  33 #include <stdint.h>
  34 #include <set>
  35
  36 YOSYS_NAMESPACE_BEGIN
  37
  38 namespace AST
  39 {
  40         // all node types, type2str() must be extended
  41         // whenever a new node type is added here
  42         enum AstNodeType
  43         {
  44                 AST_NONE,
  45                 AST_DESIGN,
  46                 AST_MODULE,
  47                 AST_TASK,
  48                 AST_FUNCTION,
  49                 AST_DPI_FUNCTION,
  50
  51                 AST_WIRE,
  52                 AST_MEMORY,
  53                 AST_AUTOWIRE,
  54                 AST_PARAMETER,
  55                 AST_LOCALPARAM,
  56                 AST_DEFPARAM,
  57                 AST_PARASET,
  58                 AST_ARGUMENT,
  59                 AST_RANGE,
  60                 AST_MULTIRANGE,
  61                 AST_CONSTANT,
  62                 AST_REALVALUE,
  63                 AST_CELLTYPE,
  64                 AST_IDENTIFIER,
  65                 AST_PREFIX,
  66                 AST_ASSERT,
  67                 AST_ASSUME,
  68
  69                 AST_FCALL,
  70                 AST_TO_BITS,
  71                 AST_TO_SIGNED,
  72                 AST_TO_UNSIGNED,
  73                 AST_CONCAT,
  74                 AST_REPLICATE,
  75                 AST_BIT_NOT,
  76                 AST_BIT_AND,
  77                 AST_BIT_OR,
  78                 AST_BIT_XOR,
  79                 AST_BIT_XNOR,
  80                 AST_REDUCE_AND,
  81                 AST_REDUCE_OR,
  82                 AST_REDUCE_XOR,
  83                 AST_REDUCE_XNOR,
  84                 AST_REDUCE_BOOL,
  85                 AST_SHIFT_LEFT,
  86                 AST_SHIFT_RIGHT,
  87                 AST_SHIFT_SLEFT,
  88                 AST_SHIFT_SRIGHT,
  89                 AST_LT,
  90                 AST_LE,
  91                 AST_EQ,
  92                 AST_NE,
  93                 AST_EQX,
  94                 AST_NEX,
  95                 AST_GE,
  96                 AST_GT,
  97                 AST_ADD,
  98                 AST_SUB,
  99                 AST_MUL,
 100                 AST_DIV,
 101                 AST_MOD,
 102                 AST_POW,
 103                 AST_POS,
 104                 AST_NEG,
 105                 AST_LOGIC_AND,
 106                 AST_LOGIC_OR,
 107                 AST_LOGIC_NOT,
 108                 AST_TERNARY,
 109                 AST_MEMRD,
 110                 AST_MEMWR,
 111                 AST_MEMINIT,
 112
 113                 AST_TCALL,
 114                 AST_ASSIGN,
 115                 AST_CELL,
 116                 AST_PRIMITIVE,
 117                 AST_CELLARRAY,
 118                 AST_ALWAYS,
 119                 AST_INITIAL,
 120                 AST_BLOCK,
 121                 AST_ASSIGN_EQ,
 122                 AST_ASSIGN_LE,
 123                 AST_CASE,
 124                 AST_COND,
 125                 AST_CONDX,
 126                 AST_CONDZ,
 127                 AST_DEFAULT,
 128                 AST_FOR,
 129                 AST_WHILE,
 130                 AST_REPEAT,
 131
 132                 AST_GENVAR,
 133                 AST_GENFOR,
 134                 AST_GENIF,
 135                 AST_GENCASE,
 136                 AST_GENBLOCK,
 137
 138                 AST_POSEDGE,
 139                 AST_NEGEDGE,
 140                 AST_EDGE
 141         };
 142
 143         // convert an node type to a string (e.g. for debug output)
 144         std::string type2str(AstNodeType type);
 145
 146         // The AST is built using instances of this struct
 147         struct AstNode
 148         {
 149                 // for dict<> and pool<>
 150                 unsigned int hashidx_;
 151                 unsigned int hash() const { return hashidx_; }
 152
 153                 // this nodes type
 154                 AstNodeType type;
 155
 156                 // the list of child nodes for this node
 157                 std::vector<AstNode*> children;
 158
 159                 // the list of attributes assigned to this node
 160                 std::map<RTLIL::IdString, AstNode*> attributes;
 161                 bool get_bool_attribute(RTLIL::IdString id);
 162
 163                 // node content - most of it is unused in most node types
 164                 std::string str;
 165                 std::vector<RTLIL::State> bits;
 166                 bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped;
 167                 int port_id, range_left, range_right;
 168                 uint32_t integer;
 169                 double realvalue;
 170
 171                 // if this is a multirange memory then this vector contains offset and length of each dimension
 172                 std::vector<int> multirange_dimensions;
 173
 174                 // this is set by simplify and used during RTLIL generation
 175                 AstNode *id2ast;
 176
 177                 // this is used by simplify to detect if basic analysis has been performed already on the node
 178                 bool basic_prep;
 179
 180                 // this is the original sourcecode location that resulted in this AST node
 181                 // it is automatically set by the constructor using AST::current_filename and
 182                 // the AST::get_line_num() callback function.
 183                 std::string filename;
 184                 int linenum;
 185
 186                 // creating and deleting nodes
 187                 AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
 188                 AstNode *clone();
 189                 void cloneInto(AstNode *other);
 190                 void delete_children();
 191                 ~AstNode();
 192
 193                 enum mem2reg_flags
 194                 {
 195                         /* status flags */
 196                         MEM2REG_FL_ALL       = 0x00000001,
 197                         MEM2REG_FL_ASYNC     = 0x00000002,
 198                         MEM2REG_FL_INIT      = 0x00000004,
 199
 200                         /* candidate flags */
 201                         MEM2REG_FL_FORCED    = 0x00000100,
 202                         MEM2REG_FL_SET_INIT  = 0x00000200,
 203                         MEM2REG_FL_SET_ELSE  = 0x00000400,
 204                         MEM2REG_FL_SET_ASYNC = 0x00000800,
 205                         MEM2REG_FL_EQ2       = 0x00001000,
 206                         MEM2REG_FL_CMPLX_LHS = 0x00002000,
 207
 208                         /* proc flags */
 209                         MEM2REG_FL_EQ1       = 0x01000000,
 210                 };
 211
 212                 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
 213                 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
 214                 bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param);
 215                 AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init);
 216                 void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
 217                 void replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules);
 218                 void mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg_places,
 219                                 dict<AstNode*, uint32_t> &mem2reg_flags, dict<AstNode*, uint32_t> &proc_flags, uint32_t &status_flags);
 220                 bool mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block);
 221                 bool mem2reg_check(pool<AstNode*> &mem2reg_set);
 222                 void meminfo(int &mem_width, int &mem_size, int &addr_bits);
 223
 224                 // additional functionality for evaluating constant functions
 225                 struct varinfo_t { RTLIL::Const val; int offset; bool is_signed; };
 226                 bool has_const_only_constructs(bool &recommend_const_eval);
 227                 void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
 228                 AstNode *eval_const_function(AstNode *fcall);
 229
 230                 // create a human-readable text representation of the AST (for debugging)
 231                 void dumpAst(FILE *f, std::string indent);
 232                 void dumpVlog(FILE *f, std::string indent);
 233
 234                 // used by genRTLIL() for detecting expression width and sign
 235                 void detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real = NULL);
 236                 void detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real = NULL);
 237
 238                 // create RTLIL code for this AST node
 239                 // for expressions the resulting signal vector is returned
 240                 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
 241                 RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
 242                 RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
 243
 244                 // compare AST nodes
 245                 bool operator==(const AstNode &other) const;
 246                 bool operator!=(const AstNode &other) const;
 247                 bool contains(const AstNode *other) const;
 248
 249                 // helper functions for creating AST nodes for constants
 250                 static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
 251                 static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
 252                 static AstNode *mkconst_str(const std::vector<RTLIL::State> &v);
 253                 static AstNode *mkconst_str(const std::string &str);
 254
 255                 // helper function for creating sign-extended const objects
 256                 RTLIL::Const bitsAsConst(int width, bool is_signed);
 257                 RTLIL::Const bitsAsConst(int width = -1);
 258                 RTLIL::Const asAttrConst();
 259                 RTLIL::Const asParaConst();
 260                 uint64_t asInt(bool is_signed);
 261                 bool bits_only_01();
 262                 bool asBool();
 263
 264                 // helper functions for real valued const eval
 265                 int isConst(); // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
 266                 double asReal(bool is_signed);
 267                 RTLIL::Const realAsConst(int width);
 268         };
 269
 270         // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
 271         void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 272
 273         // parametric modules are supported directly by the AST library
 274         // therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
 275         struct AstModule : RTLIL::Module {
 276                 AstNode *ast;
 277                 bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 278                 virtual ~AstModule();
 279                 virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters);
 280                 virtual RTLIL::Module *clone() const;
 281         };
 282
 283         // this must be set by the language frontend before parsing the sources
 284         // the AstNode constructor then uses current_filename and get_line_num()
 285         // to initialize the filename and linenum properties of new nodes
 286         extern std::string current_filename;
 287         extern void (*set_line_num)(int);
 288         extern int (*get_line_num)();
 289
 290         // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
 291         // to control the filename and linenum properties of new nodes not generated by a frontend parser)
 292         void use_internal_line_num();
 293
 294         // call a DPI function
 295         AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);
 296 }
 297
 298 namespace AST_INTERNAL
 299 {
 300         // internal state variables
 301         extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 302         extern AST::AstNode *current_ast, *current_ast_mod;
 303         extern std::map<std::string, AST::AstNode*> current_scope;
 304         extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
 305         extern RTLIL::SigSpec ignoreThisSignalsInInitial;
 306         extern AST::AstNode *current_always, *current_top_block, *current_block, *current_block_child;
 307         extern AST::AstModule *current_module;
 308         struct ProcessGenerator;
 309 }
 310
 311 YOSYS_NAMESPACE_END
 312
 313 #endif