2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
32 #include "kernel/rtlil.h"
38 // all node types, type2str() must be extended
39 // whenever a new node type is added here
126 // convert an node type to a string (e.g. for debug output)
127 std::string
type2str(AstNodeType type
);
129 // The AST is built using instances of this struct
135 // the list of child nodes for this node
136 std::vector
<AstNode
*> children
;
138 // the list of attributes assigned to this node
139 std::map
<RTLIL::IdString
, AstNode
*> attributes
;
140 bool get_bool_attribute(RTLIL::IdString id
);
142 // node content - most of it is unused in most node types
144 std::vector
<RTLIL::State
> bits
;
145 bool is_input
, is_output
, is_reg
, is_signed
, range_valid
;
146 int port_id
, range_left
, range_right
;
149 // this is set by simplify and used during RTLIL generation
152 // this is the original sourcecode location that resulted in this AST node
153 // it is automatically set by the constructor using AST::current_filename and
154 // the AST::get_line_num() callback function.
155 std::string filename
;
158 // creating and deleting nodes
159 AstNode(AstNodeType type
= AST_NONE
, AstNode
*child1
= NULL
, AstNode
*child2
= NULL
);
161 void cloneInto(AstNode
*other
);
162 void delete_children();
168 MEM2REG_FL_ALL
= 0x00000001,
169 MEM2REG_FL_ASYNC
= 0x00000002,
170 MEM2REG_FL_INIT
= 0x00000004,
172 /* candidate flags */
173 MEM2REG_FL_FORCED
= 0x00000100,
174 MEM2REG_FL_SET_INIT
= 0x00000200,
175 MEM2REG_FL_SET_ELSE
= 0x00000400,
176 MEM2REG_FL_SET_ASYNC
= 0x00000800,
177 MEM2REG_FL_EQ2
= 0x00001000,
180 MEM2REG_FL_EQ1
= 0x01000000,
183 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
184 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
185 bool simplify(bool const_fold
, bool at_zero
, bool in_lvalue
, int stage
, int width_hint
, bool sign_hint
);
186 void expand_genblock(std::string index_var
, std::string prefix
, std::map
<std::string
, std::string
> &name_map
);
187 void replace_ids(std::map
<std::string
, std::string
> &rules
);
188 void mem2reg_as_needed_pass1(std::map
<AstNode
*, std::set
<std::string
>> &mem2reg_places
,
189 std::map
<AstNode
*, uint32_t> &mem2reg_flags
, std::map
<AstNode
*, uint32_t> &proc_flags
, uint32_t &status_flags
);
190 void mem2reg_as_needed_pass2(std::set
<AstNode
*> &mem2reg_set
, AstNode
*mod
, AstNode
*block
);
191 void meminfo(int &mem_width
, int &mem_size
, int &addr_bits
);
193 // create a human-readable text representation of the AST (for debugging)
194 void dumpAst(FILE *f
, std::string indent
);
195 void dumpVlog(FILE *f
, std::string indent
);
197 // used by genRTLIL() for detecting expression width and sign
198 void detectSignWidthWorker(int &width_hint
, bool &sign_hint
);
199 void detectSignWidth(int &width_hint
, bool &sign_hint
);
201 // create RTLIL code for this AST node
202 // for expressions the resulting signal vector is returned
203 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
204 RTLIL::SigSpec
genRTLIL(int width_hint
= -1, bool sign_hint
= false);
205 RTLIL::SigSpec
genWidthRTLIL(int width
, RTLIL::SigSpec
*subst_from
= NULL
, RTLIL::SigSpec
*subst_to
= NULL
);
208 bool operator==(const AstNode
&other
) const;
209 bool operator!=(const AstNode
&other
) const;
210 bool contains(const AstNode
*other
) const;
212 // helper functions for creating AST nodes for constants
213 static AstNode
*mkconst_int(uint32_t v
, bool is_signed
, int width
= 32);
214 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
);
216 // helper function for creating sign-extended const objects
217 RTLIL::Const
bitsAsConst(int width
, bool is_signed
);
218 RTLIL::Const
bitsAsConst(int width
= -1);
221 // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
222 void process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast1
= false, bool dump_ast2
= false, bool dump_vlog
= false, bool nolatches
= false, bool nomem2reg
= false, bool mem2reg
= false, bool lib
= false, bool noopt
= false, bool ignore_redef
= false);
224 // parametric modules are supported directly by the AST library
225 // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
226 struct AstModule
: RTLIL::Module
{
228 bool nolatches
, nomem2reg
, mem2reg
, lib
, noopt
;
229 virtual ~AstModule();
230 virtual RTLIL::IdString
derive(RTLIL::Design
*design
, std::map
<RTLIL::IdString
, RTLIL::Const
> parameters
, std::set
<RTLIL::IdString
> signed_parameters
);
231 virtual RTLIL::Module
*clone() const;
234 // this must be set by the language frontend before parsing the sources
235 // the AstNode constructor then uses current_filename and get_line_num()
236 // to initialize the filename and linenum properties of new nodes
237 extern std::string current_filename
;
238 extern void (*set_line_num
)(int);
239 extern int (*get_line_num
)();
241 // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive
242 // to control the filename and linenum properties of new nodes not generated by a frontend parser)
243 void use_internal_line_num();
246 namespace AST_INTERNAL
248 // internal state variables
249 extern bool flag_dump_ast1
, flag_dump_ast2
, flag_nolatches
, flag_nomem2reg
, flag_mem2reg
, flag_lib
, flag_noopt
;
250 extern AST::AstNode
*current_ast
, *current_ast_mod
;
251 extern std::map
<std::string
, AST::AstNode
*> current_scope
;
252 extern RTLIL::SigSpec
*genRTLIL_subst_from
, *genRTLIL_subst_to
, ignoreThisSignalsInInitial
;
253 extern AST::AstNode
*current_top_block
, *current_block
, *current_block_child
;
254 extern AST::AstModule
*current_module
;
255 struct ProcessGenerator
;