Now only use value from "initial" when no matching "always" block is found
[yosys.git] / frontends / ast / ast.h
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #ifndef AST_H
30 #define AST_H
31
32 #include "kernel/rtlil.h"
33 #include <stdint.h>
34 #include <set>
35
36 namespace AST
37 {
38 // all node types, type2str() must be extended
39 // whenever a new node type is added here
40 enum AstNodeType
41 {
42 AST_NONE,
43 AST_DESIGN,
44 AST_MODULE,
45 AST_TASK,
46 AST_FUNCTION,
47
48 AST_WIRE,
49 AST_MEMORY,
50 AST_AUTOWIRE,
51 AST_PARAMETER,
52 AST_LOCALPARAM,
53 AST_PARASET,
54 AST_ARGUMENT,
55 AST_RANGE,
56 AST_CONSTANT,
57 AST_CELLTYPE,
58 AST_IDENTIFIER,
59 AST_PREFIX,
60
61 AST_FCALL,
62 AST_TO_SIGNED,
63 AST_TO_UNSIGNED,
64 AST_CONCAT,
65 AST_REPLICATE,
66 AST_BIT_NOT,
67 AST_BIT_AND,
68 AST_BIT_OR,
69 AST_BIT_XOR,
70 AST_BIT_XNOR,
71 AST_REDUCE_AND,
72 AST_REDUCE_OR,
73 AST_REDUCE_XOR,
74 AST_REDUCE_XNOR,
75 AST_REDUCE_BOOL,
76 AST_SHIFT_LEFT,
77 AST_SHIFT_RIGHT,
78 AST_SHIFT_SLEFT,
79 AST_SHIFT_SRIGHT,
80 AST_LT,
81 AST_LE,
82 AST_EQ,
83 AST_NE,
84 AST_GE,
85 AST_GT,
86 AST_ADD,
87 AST_SUB,
88 AST_MUL,
89 AST_DIV,
90 AST_MOD,
91 AST_POW,
92 AST_POS,
93 AST_NEG,
94 AST_LOGIC_AND,
95 AST_LOGIC_OR,
96 AST_LOGIC_NOT,
97 AST_TERNARY,
98 AST_MEMRD,
99 AST_MEMWR,
100
101 AST_TCALL,
102 AST_ASSIGN,
103 AST_CELL,
104 AST_PRIMITIVE,
105 AST_ALWAYS,
106 AST_INITIAL,
107 AST_BLOCK,
108 AST_ASSIGN_EQ,
109 AST_ASSIGN_LE,
110 AST_CASE,
111 AST_COND,
112 AST_DEFAULT,
113 AST_FOR,
114
115 AST_GENVAR,
116 AST_GENFOR,
117 AST_GENIF,
118 AST_GENBLOCK,
119
120 AST_POSEDGE,
121 AST_NEGEDGE,
122 AST_EDGE
123 };
124
125 // convert an node type to a string (e.g. for debug output)
126 std::string type2str(AstNodeType type);
127
128 // The AST is built using instances of this struct
129 struct AstNode
130 {
131 // this nodes type
132 AstNodeType type;
133
134 // the list of child nodes for this node
135 std::vector<AstNode*> children;
136
137 // the list of attributes assigned to this node
138 std::map<RTLIL::IdString, AstNode*> attributes;
139
140 // node content - most of it is unused in most node types
141 std::string str;
142 std::vector<RTLIL::State> bits;
143 bool is_input, is_output, is_reg, is_signed, range_valid;
144 int port_id, range_left, range_right;
145 uint32_t integer;
146
147 // this is set by simplify and used during RTLIL generation
148 AstNode *id2ast;
149
150 // this is the original sourcecode location that resulted in this AST node
151 // it is automatically set by the constructor using AST::current_filename and
152 // the AST::get_line_num() callback function.
153 std::string filename;
154 int linenum;
155
156 // creating and deleting nodes
157 AstNode(AstNodeType type = AST_NONE, AstNode *child1 = NULL, AstNode *child2 = NULL);
158 AstNode *clone();
159 void cloneInto(AstNode *other);
160 void delete_children();
161 ~AstNode();
162
163 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
164 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
165 bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage);
166 void expand_genblock(std::string index_var, std::string prefix, std::map<std::string, std::string> &name_map);
167 void replace_ids(std::map<std::string, std::string> &rules);
168 void mem2reg_as_needed_pass1(std::set<AstNode*> &mem2reg_set, std::set<AstNode*> &mem2reg_candidates, bool sync_proc, bool async_proc, bool force_mem2reg);
169 void mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *mod, AstNode *block);
170 void meminfo(int &mem_width, int &mem_size, int &addr_bits);
171
172 // create a human-readable text representation of the AST (for debugging)
173 void dumpAst(FILE *f, std::string indent, AstNode *other = NULL);
174 void dumpVlog(FILE *f, std::string indent);
175
176 // create RTLIL code for this AST node
177 // for expressions the resulting signal vector is returned
178 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
179 RTLIL::SigSpec genRTLIL(int width_hint = -1);
180 RTLIL::SigSpec genWidthRTLIL(int width, RTLIL::SigSpec *subst_from = NULL, RTLIL::SigSpec *subst_to = NULL);
181
182 // compare AST nodes
183 bool operator==(const AstNode &other) const;
184 bool operator!=(const AstNode &other) const;
185 bool contains(const AstNode *other) const;
186
187 // helper functions for creating AST nodes for constants
188 static AstNode *mkconst_int(uint32_t v, bool is_signed, int width = 32);
189 static AstNode *mkconst_bits(const std::vector<RTLIL::State> &v, bool is_signed);
190 };
191
192 // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
193 void process(RTLIL::Design *design, AstNode *ast, bool dump_ast = false, bool dump_ast_diff = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false);
194
195 // parametric modules are supported directly by the AST library
196 // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
197 struct AstModule : RTLIL::Module {
198 AstNode *ast;
199 bool nolatches, nomem2reg, mem2reg, lib;
200 virtual ~AstModule();
201 virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
202 virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes);
203 };
204
205 // this must be set by the language frontend before parsing the sources
206 // the AstNode constructor then uses current_filename and get_line_num()
207 // to initialize the filename and linenum properties of new nodes
208 extern std::string current_filename;
209 extern void (*set_line_num)(int);
210 extern int (*get_line_num)();
211
212 // set set_line_num and get_line_num to internal dummy functions
213 // (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control
214 // the filename and linenum properties of new nodes not generated by a frontend parser)
215 void use_internal_line_num();
216 }
217
218 namespace AST_INTERNAL
219 {
220 // internal state variables
221 extern bool flag_dump_ast, flag_dump_ast_diff, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib;
222 extern AST::AstNode *current_ast, *current_ast_mod;
223 extern std::map<std::string, AST::AstNode*> current_scope;
224 extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;
225 extern AST::AstNode *current_top_block, *current_block, *current_block_child;
226 extern AST::AstModule *current_module;
227 struct ProcessGenerator;
228 }
229
230 #endif