2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
32 #include "kernel/rtlil.h"
38 // all node types, type2str() must be extended
39 // whenever a new node type is added here
125 // convert an node type to a string (e.g. for debug output)
126 std::string
type2str(AstNodeType type
);
128 // The AST is built using instances of this struct
134 // the list of child nodes for this node
135 std::vector
<AstNode
*> children
;
137 // the list of attributes assigned to this node
138 std::map
<RTLIL::IdString
, AstNode
*> attributes
;
140 // node content - most of it is unused in most node types
142 std::vector
<RTLIL::State
> bits
;
143 bool is_input
, is_output
, is_reg
, is_signed
, range_valid
;
144 int port_id
, range_left
, range_right
;
147 // this is set by simplify and used during RTLIL generation
150 // this is the original sourcecode location that resulted in this AST node
151 // it is automatically set by the constructor using AST::current_filename and
152 // the AST::get_line_num() callback function.
153 std::string filename
;
156 // creating and deleting nodes
157 AstNode(AstNodeType type
= AST_NONE
, AstNode
*child1
= NULL
, AstNode
*child2
= NULL
);
159 void cloneInto(AstNode
*other
);
160 void delete_children();
163 // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc.
164 // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL()
165 bool simplify(bool const_fold
, bool at_zero
, bool in_lvalue
, int stage
);
166 void expand_genblock(std::string index_var
, std::string prefix
, std::map
<std::string
, std::string
> &name_map
);
167 void replace_ids(std::map
<std::string
, std::string
> &rules
);
168 void mem2reg_as_needed_pass1(std::set
<AstNode
*> &mem2reg_set
, std::set
<AstNode
*> &mem2reg_candidates
, bool sync_proc
, bool async_proc
, bool force_mem2reg
);
169 void mem2reg_as_needed_pass2(std::set
<AstNode
*> &mem2reg_set
, AstNode
*mod
, AstNode
*block
);
170 void meminfo(int &mem_width
, int &mem_size
, int &addr_bits
);
172 // create a human-readable text representation of the AST (for debugging)
173 void dumpAst(FILE *f
, std::string indent
, AstNode
*other
= NULL
);
174 void dumpVlog(FILE *f
, std::string indent
);
176 // create RTLIL code for this AST node
177 // for expressions the resulting signal vector is returned
178 // all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
179 RTLIL::SigSpec
genRTLIL(int width_hint
= -1);
180 RTLIL::SigSpec
genWidthRTLIL(int width
, RTLIL::SigSpec
*subst_from
= NULL
, RTLIL::SigSpec
*subst_to
= NULL
);
183 bool operator==(const AstNode
&other
) const;
184 bool operator!=(const AstNode
&other
) const;
185 bool contains(const AstNode
*other
) const;
187 // helper functions for creating AST nodes for constants
188 static AstNode
*mkconst_int(uint32_t v
, bool is_signed
, int width
= 32);
189 static AstNode
*mkconst_bits(const std::vector
<RTLIL::State
> &v
, bool is_signed
);
192 // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
193 void process(RTLIL::Design
*design
, AstNode
*ast
, bool dump_ast
= false, bool dump_ast_diff
= false, bool dump_vlog
= false, bool nolatches
= false, bool nomem2reg
= false, bool mem2reg
= false, bool lib
= false);
195 // parametric modules are supported directly by the AST library
196 // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
197 struct AstModule
: RTLIL::Module
{
199 bool nolatches
, nomem2reg
, mem2reg
, lib
;
200 virtual ~AstModule();
201 virtual RTLIL::IdString
derive(RTLIL::Design
*design
, std::map
<RTLIL::IdString
, RTLIL::Const
> parameters
);
202 virtual void update_auto_wires(std::map
<RTLIL::IdString
, int> auto_sizes
);
205 // this must be set by the language frontend before parsing the sources
206 // the AstNode constructor then uses current_filename and get_line_num()
207 // to initialize the filename and linenum properties of new nodes
208 extern std::string current_filename
;
209 extern void (*set_line_num
)(int);
210 extern int (*get_line_num
)();
212 // set set_line_num and get_line_num to internal dummy functions
213 // (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control
214 // the filename and linenum properties of new nodes not generated by a frontend parser)
215 void use_internal_line_num();
218 namespace AST_INTERNAL
220 // internal state variables
221 extern bool flag_dump_ast
, flag_dump_ast_diff
, flag_nolatches
, flag_nomem2reg
, flag_mem2reg
, flag_lib
;
222 extern AST::AstNode
*current_ast
, *current_ast_mod
;
223 extern std::map
<std::string
, AST::AstNode
*> current_scope
;
224 extern RTLIL::SigSpec
*genRTLIL_subst_from
, *genRTLIL_subst_to
, ignoreThisSignalsInInitial
;
225 extern AST::AstNode
*current_top_block
, *current_block
, *current_block_child
;
226 extern AST::AstModule
*current_module
;
227 struct ProcessGenerator
;