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[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "kernel/utils.h"
31 #include "libs/sha1/sha1.h"
32 #include "ast.h"
33
34 #include <sstream>
35 #include <stdarg.h>
36 #include <algorithm>
37
38 YOSYS_NAMESPACE_BEGIN
39
40 using namespace AST;
41 using namespace AST_INTERNAL;
42
43 // helper function for creating RTLIL code for unary operations
44 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
45 {
46 std::stringstream sstr;
47 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
48
49 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
51
52 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
54
55 if (gen_attributes)
56 for (auto &attr : that->attributes) {
57 if (attr.second->type != AST_CONSTANT)
58 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
59 cell->attributes[attr.first] = attr.second->asAttrConst();
60 }
61
62 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
63 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
64 cell->setPort("\\A", arg);
65
66 cell->parameters["\\Y_WIDTH"] = result_width;
67 cell->setPort("\\Y", wire);
68 return wire;
69 }
70
71 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
72 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
73 {
74 if (width <= sig.size()) {
75 sig.extend_u0(width, is_signed);
76 return;
77 }
78
79 std::stringstream sstr;
80 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
81
82 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
83 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
84
85 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
86 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
87
88 if (that != NULL)
89 for (auto &attr : that->attributes) {
90 if (attr.second->type != AST_CONSTANT)
91 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
92 cell->attributes[attr.first] = attr.second->asAttrConst();
93 }
94
95 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
96 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
97 cell->setPort("\\A", sig);
98
99 cell->parameters["\\Y_WIDTH"] = width;
100 cell->setPort("\\Y", wire);
101 sig = wire;
102 }
103
104 // helper function for creating RTLIL code for binary operations
105 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
106 {
107 std::stringstream sstr;
108 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
109
110 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
111 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
112
113 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
114 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
115
116 for (auto &attr : that->attributes) {
117 if (attr.second->type != AST_CONSTANT)
118 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
119 cell->attributes[attr.first] = attr.second->asAttrConst();
120 }
121
122 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
123 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
124
125 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
126 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
127
128 cell->setPort("\\A", left);
129 cell->setPort("\\B", right);
130
131 cell->parameters["\\Y_WIDTH"] = result_width;
132 cell->setPort("\\Y", wire);
133 return wire;
134 }
135
136 // helper function for creating RTLIL code for multiplexers
137 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
138 {
139 log_assert(cond.size() == 1);
140
141 std::stringstream sstr;
142 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
143
144 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
145 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
146
147 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
148 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
149
150 for (auto &attr : that->attributes) {
151 if (attr.second->type != AST_CONSTANT)
152 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
153 cell->attributes[attr.first] = attr.second->asAttrConst();
154 }
155
156 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
157
158 cell->setPort("\\A", right);
159 cell->setPort("\\B", left);
160 cell->setPort("\\S", cond);
161 cell->setPort("\\Y", wire);
162
163 return wire;
164 }
165
166 // helper class for converting AST always nodes to RTLIL processes
167 struct AST_INTERNAL::ProcessGenerator
168 {
169 // input and output structures
170 AstNode *always;
171 RTLIL::SigSpec initSyncSignals;
172 RTLIL::Process *proc;
173 RTLIL::SigSpec outputSignals;
174
175 // This always points to the RTLIL::CaseRule being filled at the moment
176 RTLIL::CaseRule *current_case;
177
178 // This map contains the replacement pattern to be used in the right hand side
179 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
180 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
181 // the value assigned in the first assignment. So when the first assignment is processed
182 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
183 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
184
185 // This map contains the replacement pattern to be used in the left hand side
186 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
187 // should not be connected to the signal foo. Instead it must be connected to the temporary
188 // signal that is used as input for the register that drives the signal foo.
189 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
190
191 // The code here generates a number of temporary signal for each output register. This
192 // map helps generating nice numbered names for all this temporary signals.
193 std::map<RTLIL::Wire*, int> new_temp_count;
194
195 // Buffer for generating the init action
196 RTLIL::SigSpec init_lvalue, init_rvalue;
197
198 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
199 {
200 // generate process and simple root case
201 proc = new RTLIL::Process;
202 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
203 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
204 for (auto &attr : always->attributes) {
205 if (attr.second->type != AST_CONSTANT)
206 log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
207 attr.first.c_str());
208 proc->attributes[attr.first] = attr.second->asAttrConst();
209 }
210 current_module->processes[proc->name] = proc;
211 current_case = &proc->root_case;
212
213 // create initial temporary signal for all output registers
214 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
215 collect_lvalues(subst_lvalue_from, always, true, true);
216 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
217 subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
218
219 bool found_global_syncs = false;
220 bool found_anyedge_syncs = false;
221 for (auto child : always->children)
222 {
223 if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
224 child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
225 found_global_syncs = true;
226 }
227 if (child->type == AST_EDGE) {
228 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock")
229 found_global_syncs = true;
230 else
231 found_anyedge_syncs = true;
232 }
233 }
234
235 if (found_anyedge_syncs) {
236 if (found_global_syncs)
237 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
238 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
239 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
240 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
241 }
242
243 // create syncs for the process
244 bool found_clocked_sync = false;
245 for (auto child : always->children)
246 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
247 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
248 child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
249 continue;
250 found_clocked_sync = true;
251 if (found_global_syncs || found_anyedge_syncs)
252 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
253 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
254 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
255 syncrule->signal = child->children[0]->genRTLIL();
256 if (GetSize(syncrule->signal) != 1)
257 log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
258 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
259 proc->syncs.push_back(syncrule);
260 }
261 if (proc->syncs.empty()) {
262 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
263 syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
264 syncrule->signal = RTLIL::SigSpec();
265 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
266 proc->syncs.push_back(syncrule);
267 }
268
269 // create initial assignments for the temporary signals
270 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
271 subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
272 } else {
273 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
274 }
275
276 // process the AST
277 for (auto child : always->children)
278 if (child->type == AST_BLOCK)
279 processAst(child);
280
281 if (initSyncSignals.size() > 0)
282 {
283 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
284 sync->type = RTLIL::SyncType::STi;
285 proc->syncs.push_back(sync);
286
287 log_assert(init_lvalue.size() == init_rvalue.size());
288
289 int offset = 0;
290 for (auto &init_lvalue_c : init_lvalue.chunks()) {
291 RTLIL::SigSpec lhs = init_lvalue_c;
292 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
293 remove_unwanted_lvalue_bits(lhs, rhs);
294 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
295 offset += lhs.size();
296 }
297 }
298
299 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
300 }
301
302 void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
303 {
304 RTLIL::SigSpec new_lhs, new_rhs;
305
306 log_assert(GetSize(lhs) == GetSize(rhs));
307 for (int i = 0; i < GetSize(lhs); i++) {
308 if (lhs[i].wire == nullptr)
309 continue;
310 new_lhs.append(lhs[i]);
311 new_rhs.append(rhs[i]);
312 }
313
314 lhs = new_lhs;
315 rhs = new_rhs;
316 }
317
318 // create new temporary signals
319 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
320 {
321 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
322
323 for (int i = 0; i < GetSize(chunks); i++)
324 {
325 RTLIL::SigChunk &chunk = chunks[i];
326 if (chunk.wire == NULL)
327 continue;
328
329 std::string wire_name;
330 do {
331 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
332 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
333 if (chunk.wire->name.str().find('$') != std::string::npos)
334 wire_name += stringf("$%d", autoidx++);
335 } while (current_module->wires_.count(wire_name) > 0);
336
337 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
338 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
339
340 chunk.wire = wire;
341 chunk.offset = 0;
342 }
343
344 return chunks;
345 }
346
347 // recursively traverse the AST an collect all assigned signals
348 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
349 {
350 switch (ast->type)
351 {
352 case AST_CASE:
353 for (auto child : ast->children)
354 if (child != ast->children[0]) {
355 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
356 collect_lvalues(reg, child, type_eq, type_le, false);
357 }
358 break;
359
360 case AST_COND:
361 case AST_CONDX:
362 case AST_CONDZ:
363 case AST_ALWAYS:
364 case AST_INITIAL:
365 for (auto child : ast->children)
366 if (child->type == AST_BLOCK)
367 collect_lvalues(reg, child, type_eq, type_le, false);
368 break;
369
370 case AST_BLOCK:
371 for (auto child : ast->children) {
372 if (child->type == AST_ASSIGN_EQ && type_eq)
373 reg.append(child->children[0]->genRTLIL());
374 if (child->type == AST_ASSIGN_LE && type_le)
375 reg.append(child->children[0]->genRTLIL());
376 if (child->type == AST_CASE || child->type == AST_BLOCK)
377 collect_lvalues(reg, child, type_eq, type_le, false);
378 }
379 break;
380
381 default:
382 log_abort();
383 }
384
385 if (run_sort_and_unify) {
386 std::set<RTLIL::SigBit> sorted_reg;
387 for (auto bit : reg)
388 if (bit.wire)
389 sorted_reg.insert(bit);
390 reg = RTLIL::SigSpec(sorted_reg);
391 }
392 }
393
394 // remove all assignments to the given signal pattern in a case and all its children.
395 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
396 // function is called to clean up the first two assignments as they are overwritten by
397 // the third assignment.
398 void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
399 {
400 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
401 it->first.remove2(pattern, &it->second);
402
403 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
404 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
405 removeSignalFromCaseTree(pattern, *it2);
406 }
407
408 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
409 // are avoided and the generated $mux cells have a more "natural" size.
410 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
411 {
412 if (inSyncRule && initSyncSignals.size() > 0) {
413 init_lvalue.append(lvalue.extract(initSyncSignals));
414 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
415 lvalue.remove2(initSyncSignals, &rvalue);
416 }
417 log_assert(lvalue.size() == rvalue.size());
418
419 int offset = 0;
420 for (auto &lvalue_c : lvalue.chunks()) {
421 RTLIL::SigSpec lhs = lvalue_c;
422 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
423 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
424 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
425 remove_unwanted_lvalue_bits(lhs, rhs);
426 actions.push_back(RTLIL::SigSig(lhs, rhs));
427 offset += lhs.size();
428 }
429 }
430
431 // recursively process the AST and fill the RTLIL::Process
432 void processAst(AstNode *ast)
433 {
434 switch (ast->type)
435 {
436 case AST_BLOCK:
437 for (auto child : ast->children)
438 processAst(child);
439 break;
440
441 case AST_ASSIGN_EQ:
442 case AST_ASSIGN_LE:
443 {
444 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
445 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
446
447 pool<SigBit> lvalue_sigbits;
448 for (int i = 0; i < GetSize(lvalue); i++) {
449 if (lvalue_sigbits.count(lvalue[i]) > 0) {
450 unmapped_lvalue.remove(i);
451 lvalue.remove(i);
452 rvalue.remove(i--);
453 } else
454 lvalue_sigbits.insert(lvalue[i]);
455 }
456
457 lvalue.replace(subst_lvalue_map.stdmap());
458
459 if (ast->type == AST_ASSIGN_EQ) {
460 for (int i = 0; i < GetSize(unmapped_lvalue); i++)
461 subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
462 }
463
464 removeSignalFromCaseTree(lvalue, current_case);
465 remove_unwanted_lvalue_bits(lvalue, rvalue);
466 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
467 }
468 break;
469
470 case AST_CASE:
471 {
472 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
473 sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
474 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
475 current_case->switches.push_back(sw);
476
477 for (auto &attr : ast->attributes) {
478 if (attr.second->type != AST_CONSTANT)
479 log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
480 sw->attributes[attr.first] = attr.second->asAttrConst();
481 }
482
483 RTLIL::SigSpec this_case_eq_lvalue;
484 collect_lvalues(this_case_eq_lvalue, ast, true, false);
485
486 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
487
488 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
489 this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
490
491 RTLIL::CaseRule *default_case = NULL;
492 RTLIL::CaseRule *last_generated_case = NULL;
493 for (auto child : ast->children)
494 {
495 if (child == ast->children[0])
496 continue;
497 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
498
499 subst_lvalue_map.save();
500 subst_rvalue_map.save();
501
502 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
503 subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
504
505 RTLIL::CaseRule *backup_case = current_case;
506 current_case = new RTLIL::CaseRule;
507 last_generated_case = current_case;
508 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
509 for (auto node : child->children) {
510 if (node->type == AST_DEFAULT)
511 default_case = current_case;
512 else if (node->type == AST_BLOCK)
513 processAst(node);
514 else
515 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
516 }
517 if (default_case != current_case)
518 sw->cases.push_back(current_case);
519 else
520 log_assert(current_case->compare.size() == 0);
521 current_case = backup_case;
522
523 subst_lvalue_map.restore();
524 subst_rvalue_map.restore();
525 }
526
527 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
528 #if 0
529 // this is a valid transformation, but as optimization it is premature.
530 // better: add a default case that assigns 'x' to everything, and let later
531 // optimizations take care of the rest
532 last_generated_case->compare.clear();
533 #else
534 default_case = new RTLIL::CaseRule;
535 addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
536 sw->cases.push_back(default_case);
537 #endif
538 } else {
539 if (default_case == NULL) {
540 default_case = new RTLIL::CaseRule;
541 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
542 }
543 sw->cases.push_back(default_case);
544 }
545
546 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
547 subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
548
549 this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
550 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
551 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
552 }
553 break;
554
555 case AST_WIRE:
556 log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
557 break;
558
559 case AST_ASSIGN:
560 log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
561 break;
562
563 case AST_PARAMETER:
564 case AST_LOCALPARAM:
565 log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
566 break;
567
568 case AST_NONE:
569 case AST_TCALL:
570 case AST_FOR:
571 break;
572
573 default:
574 // ast->dumpAst(NULL, "ast> ");
575 // current_ast_mod->dumpAst(NULL, "mod> ");
576 log_abort();
577 }
578 }
579 };
580
581 // detect sign and width of an expression
582 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
583 {
584 std::string type_name;
585 bool sub_sign_hint = true;
586 int sub_width_hint = -1;
587 int this_width = 0;
588 AstNode *range = NULL;
589 AstNode *id_ast = NULL;
590
591 bool local_found_real = false;
592 if (found_real == NULL)
593 found_real = &local_found_real;
594
595 switch (type)
596 {
597 case AST_CONSTANT:
598 width_hint = max(width_hint, int(bits.size()));
599 if (!is_signed)
600 sign_hint = false;
601 break;
602
603 case AST_REALVALUE:
604 *found_real = true;
605 width_hint = max(width_hint, 32);
606 break;
607
608 case AST_IDENTIFIER:
609 id_ast = id2ast;
610 if (id_ast == NULL && current_scope.count(str))
611 id_ast = current_scope.at(str);
612 if (!id_ast)
613 log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
614 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
615 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
616 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
617 } else
618 if (id_ast->children[0]->type != AST_CONSTANT)
619 while (id_ast->simplify(true, false, false, 1, -1, false, true)) { }
620 if (id_ast->children[0]->type == AST_CONSTANT)
621 this_width = id_ast->children[0]->bits.size();
622 else
623 log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
624 if (children.size() != 0)
625 range = children[0];
626 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
627 if (!id_ast->range_valid) {
628 if (id_ast->type == AST_AUTOWIRE)
629 this_width = 1;
630 else {
631 // current_ast_mod->dumpAst(NULL, "mod> ");
632 // log("---\n");
633 // id_ast->dumpAst(NULL, "decl> ");
634 // dumpAst(NULL, "ref> ");
635 log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
636 }
637 } else {
638 this_width = id_ast->range_left - id_ast->range_right + 1;
639 if (children.size() != 0)
640 range = children[0];
641 }
642 } else if (id_ast->type == AST_GENVAR) {
643 this_width = 32;
644 } else if (id_ast->type == AST_MEMORY) {
645 if (!id_ast->children[0]->range_valid)
646 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
647 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
648 if (children.size() > 1)
649 range = children[1];
650 } else
651 log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
652 if (range) {
653 if (range->children.size() == 1)
654 this_width = 1;
655 else if (!range->range_valid) {
656 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
657 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
658 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
659 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
660 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
661 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
662 this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
663 delete left_at_zero_ast;
664 delete right_at_zero_ast;
665 } else
666 this_width = range->range_left - range->range_right + 1;
667 sign_hint = false;
668 }
669 width_hint = max(width_hint, this_width);
670 if (!id_ast->is_signed)
671 sign_hint = false;
672 break;
673
674 case AST_TO_BITS:
675 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
676 if (children[0]->type != AST_CONSTANT)
677 log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
678 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
679 width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
680 break;
681
682 case AST_TO_SIGNED:
683 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
684 break;
685
686 case AST_TO_UNSIGNED:
687 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
688 sign_hint = false;
689 break;
690
691 case AST_CONCAT:
692 for (auto child : children) {
693 sub_width_hint = 0;
694 sub_sign_hint = true;
695 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
696 this_width += sub_width_hint;
697 }
698 width_hint = max(width_hint, this_width);
699 sign_hint = false;
700 break;
701
702 case AST_REPLICATE:
703 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
704 if (children[0]->type != AST_CONSTANT)
705 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
706 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
707 width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
708 sign_hint = false;
709 break;
710
711 case AST_NEG:
712 case AST_BIT_NOT:
713 case AST_POS:
714 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
715 break;
716
717 case AST_BIT_AND:
718 case AST_BIT_OR:
719 case AST_BIT_XOR:
720 case AST_BIT_XNOR:
721 for (auto child : children)
722 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
723 break;
724
725 case AST_REDUCE_AND:
726 case AST_REDUCE_OR:
727 case AST_REDUCE_XOR:
728 case AST_REDUCE_XNOR:
729 case AST_REDUCE_BOOL:
730 width_hint = max(width_hint, 1);
731 sign_hint = false;
732 break;
733
734 case AST_SHIFT_LEFT:
735 case AST_SHIFT_RIGHT:
736 case AST_SHIFT_SLEFT:
737 case AST_SHIFT_SRIGHT:
738 case AST_POW:
739 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
740 break;
741
742 case AST_LT:
743 case AST_LE:
744 case AST_EQ:
745 case AST_NE:
746 case AST_EQX:
747 case AST_NEX:
748 case AST_GE:
749 case AST_GT:
750 width_hint = max(width_hint, 1);
751 sign_hint = false;
752 break;
753
754 case AST_ADD:
755 case AST_SUB:
756 case AST_MUL:
757 case AST_DIV:
758 case AST_MOD:
759 for (auto child : children)
760 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
761 break;
762
763 case AST_LOGIC_AND:
764 case AST_LOGIC_OR:
765 case AST_LOGIC_NOT:
766 width_hint = max(width_hint, 1);
767 sign_hint = false;
768 break;
769
770 case AST_TERNARY:
771 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
772 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
773 break;
774
775 case AST_MEMRD:
776 if (!id2ast->is_signed)
777 sign_hint = false;
778 if (!id2ast->children[0]->range_valid)
779 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
780 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
781 width_hint = max(width_hint, this_width);
782 break;
783
784 case AST_FCALL:
785 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
786 if (GetSize(children) == 1) {
787 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
788 if (children[0]->type != AST_CONSTANT)
789 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
790 RTLIL::unescape_id(str).c_str());
791 width_hint = max(width_hint, int(children[0]->asInt(true)));
792 }
793 break;
794 }
795 if (str == "\\$past") {
796 if (GetSize(children) > 0) {
797 sub_width_hint = 0;
798 sub_sign_hint = true;
799 children.at(0)->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
800 width_hint = max(width_hint, sub_width_hint);
801 sign_hint = false;
802 }
803 break;
804 }
805 /* fall through */
806
807 // everything should have been handled above -> print error if not.
808 default:
809 for (auto f : log_files)
810 current_ast_mod->dumpAst(f, "verilog-ast> ");
811 log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
812 }
813
814 if (*found_real)
815 sign_hint = true;
816 }
817
818 // detect sign and width of an expression
819 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
820 {
821 width_hint = -1;
822 sign_hint = true;
823 if (found_real)
824 *found_real = false;
825 detectSignWidthWorker(width_hint, sign_hint, found_real);
826 }
827
828 // create RTLIL from an AST node
829 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
830 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
831 //
832 // note that this function is influenced by a number of global variables that might be set when
833 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
834 // larger expressions into a netlist of cells.
835 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
836 {
837 // in the following big switch() statement there are some uses of
838 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
839 // cases this variable is used to hold the type of the cell that should
840 // be instantiated for this type of AST node.
841 std::string type_name;
842
843 current_filename = filename;
844 set_line_num(linenum);
845
846 switch (type)
847 {
848 // simply ignore this nodes.
849 // they are either leftovers from simplify() or are referenced by other nodes
850 // and are only accessed here thru this references
851 case AST_NONE:
852 case AST_TASK:
853 case AST_FUNCTION:
854 case AST_DPI_FUNCTION:
855 case AST_AUTOWIRE:
856 case AST_LOCALPARAM:
857 case AST_DEFPARAM:
858 case AST_GENVAR:
859 case AST_GENFOR:
860 case AST_GENBLOCK:
861 case AST_GENIF:
862 case AST_GENCASE:
863 case AST_PACKAGE:
864 case AST_MODPORT:
865 case AST_MODPORTMEMBER:
866 break;
867 case AST_INTERFACEPORT: {
868 // If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
869 // This is used by the hierarchy pass to know when it can replace interface connection with the individual
870 // signals.
871 RTLIL::Wire *wire = current_module->addWire(str, 1);
872 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
873 wire->start_offset = 0;
874 wire->port_id = port_id;
875 wire->port_input = true;
876 wire->port_output = true;
877 wire->set_bool_attribute("\\is_interface");
878 if (children.size() > 0) {
879 for(size_t i=0; i<children.size();i++) {
880 if(children[i]->type == AST_INTERFACEPORTTYPE) {
881 std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
882 wire->attributes["\\interface_type"] = res.first;
883 if (res.second != "")
884 wire->attributes["\\interface_modport"] = res.second;
885 break;
886 }
887 }
888 }
889 wire->upto = 0;
890 }
891 break;
892 case AST_INTERFACEPORTTYPE:
893 break;
894
895 // remember the parameter, needed for example in techmap
896 case AST_PARAMETER:
897 current_module->avail_parameters.insert(str);
898 break;
899
900 // create an RTLIL::Wire for an AST_WIRE node
901 case AST_WIRE: {
902 if (current_module->wires_.count(str) != 0)
903 log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str());
904 if (!range_valid)
905 log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
906
907 log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
908
909 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
910 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
911 wire->start_offset = range_right;
912 wire->port_id = port_id;
913 wire->port_input = is_input;
914 wire->port_output = is_output;
915 wire->upto = range_swapped;
916
917 for (auto &attr : attributes) {
918 if (attr.second->type != AST_CONSTANT)
919 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
920 wire->attributes[attr.first] = attr.second->asAttrConst();
921 }
922 }
923 break;
924
925 // create an RTLIL::Memory for an AST_MEMORY node
926 case AST_MEMORY: {
927 if (current_module->memories.count(str) != 0)
928 log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str());
929
930 log_assert(children.size() >= 2);
931 log_assert(children[0]->type == AST_RANGE);
932 log_assert(children[1]->type == AST_RANGE);
933
934 if (!children[0]->range_valid || !children[1]->range_valid)
935 log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str());
936
937 RTLIL::Memory *memory = new RTLIL::Memory;
938 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
939 memory->name = str;
940 memory->width = children[0]->range_left - children[0]->range_right + 1;
941 if (children[1]->range_right < children[1]->range_left) {
942 memory->start_offset = children[1]->range_right;
943 memory->size = children[1]->range_left - children[1]->range_right + 1;
944 } else {
945 memory->start_offset = children[1]->range_left;
946 memory->size = children[1]->range_right - children[1]->range_left + 1;
947 }
948 current_module->memories[memory->name] = memory;
949
950 for (auto &attr : attributes) {
951 if (attr.second->type != AST_CONSTANT)
952 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
953 memory->attributes[attr.first] = attr.second->asAttrConst();
954 }
955 }
956 break;
957
958 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
959 case AST_CONSTANT:
960 case AST_REALVALUE:
961 {
962 if (width_hint < 0)
963 detectSignWidth(width_hint, sign_hint);
964 is_signed = sign_hint;
965
966 if (type == AST_CONSTANT)
967 return RTLIL::SigSpec(bitsAsConst());
968
969 RTLIL::SigSpec sig = realAsConst(width_hint);
970 log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
971 return sig;
972 }
973
974 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
975 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
976 // shifter cell is created and the output signal of this cell is returned
977 case AST_IDENTIFIER:
978 {
979 RTLIL::Wire *wire = NULL;
980 RTLIL::SigChunk chunk;
981 bool is_interface = false;
982
983 int add_undef_bits_msb = 0;
984 int add_undef_bits_lsb = 0;
985
986 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
987 RTLIL::Wire *wire = current_module->addWire(str);
988 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
989 wire->name = str;
990 if (flag_autowire)
991 log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
992 else
993 log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
994 }
995 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
996 if (id2ast->children[0]->type != AST_CONSTANT)
997 log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str());
998 chunk = RTLIL::Const(id2ast->children[0]->bits);
999 goto use_const_chunk;
1000 }
1001 else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
1002 RTLIL::Wire *current_wire = current_module->wire(str);
1003 if (current_wire->get_bool_attribute("\\is_interface"))
1004 is_interface = true;
1005 // Ignore
1006 }
1007 // If an identifier is found that is not already known, assume that it is an interface:
1008 else if (1) { // FIXME: Check if sv_mode first?
1009 is_interface = true;
1010 }
1011 else {
1012 log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
1013 }
1014
1015 if (id2ast->type == AST_MEMORY)
1016 log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
1017
1018 // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
1019 // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
1020 // with the individual signals:
1021 if (is_interface) {
1022 RTLIL::Wire *dummy_wire;
1023 std::string dummy_wire_name = "$dummywireforinterface" + str;
1024 if (current_module->wires_.count(dummy_wire_name))
1025 dummy_wire = current_module->wires_[dummy_wire_name];
1026 else {
1027 dummy_wire = current_module->addWire(dummy_wire_name);
1028 dummy_wire->set_bool_attribute("\\is_interface");
1029 }
1030 RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
1031 return tmp;
1032 }
1033
1034 wire = current_module->wires_[str];
1035 chunk.wire = wire;
1036 chunk.width = wire->width;
1037 chunk.offset = 0;
1038
1039 use_const_chunk:
1040 if (children.size() != 0) {
1041 if (children[0]->type != AST_RANGE)
1042 log_file_error(filename, linenum, "Single range expected.\n");
1043 int source_width = id2ast->range_left - id2ast->range_right + 1;
1044 int source_offset = id2ast->range_right;
1045 if (!children[0]->range_valid) {
1046 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
1047 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
1048 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1049 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1050 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
1051 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
1052 int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
1053 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
1054 children[0]->children[1]->clone() : children[0]->children[0]->clone());
1055 fake_ast->children[0]->delete_children();
1056 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
1057 if (id2ast->range_right != 0) {
1058 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
1059 fake_ast->children[1]->is_signed = true;
1060 }
1061 if (id2ast->range_swapped) {
1062 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
1063 fake_ast->children[1]->is_signed = true;
1064 }
1065 if (GetSize(shift_val) >= 32)
1066 fake_ast->children[1]->is_signed = true;
1067 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
1068 delete left_at_zero_ast;
1069 delete right_at_zero_ast;
1070 delete fake_ast;
1071 return sig;
1072 } else {
1073 chunk.width = children[0]->range_left - children[0]->range_right + 1;
1074 chunk.offset = children[0]->range_right - source_offset;
1075 if (id2ast->range_swapped)
1076 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
1077 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
1078 if (chunk.width == 1)
1079 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
1080 str.c_str());
1081 else
1082 log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
1083 children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
1084 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
1085 } else {
1086 if (chunk.width + chunk.offset > source_width) {
1087 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
1088 chunk.width -= add_undef_bits_msb;
1089 }
1090 if (chunk.offset < 0) {
1091 add_undef_bits_lsb = -chunk.offset;
1092 chunk.width -= add_undef_bits_lsb;
1093 chunk.offset += add_undef_bits_lsb;
1094 }
1095 if (add_undef_bits_lsb)
1096 log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
1097 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
1098 if (add_undef_bits_msb)
1099 log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
1100 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
1101 }
1102 }
1103 }
1104
1105 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
1106
1107 if (genRTLIL_subst_ptr)
1108 sig.replace(*genRTLIL_subst_ptr);
1109
1110 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
1111 return sig;
1112 }
1113
1114 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
1115 case AST_TO_SIGNED:
1116 case AST_TO_UNSIGNED: {
1117 RTLIL::SigSpec sig = children[0]->genRTLIL();
1118 if (sig.size() < width_hint)
1119 sig.extend_u0(width_hint, sign_hint);
1120 is_signed = sign_hint;
1121 return sig;
1122 }
1123
1124 // concatenation of signals can be done directly using RTLIL::SigSpec
1125 case AST_CONCAT: {
1126 RTLIL::SigSpec sig;
1127 for (auto it = children.begin(); it != children.end(); it++)
1128 sig.append((*it)->genRTLIL());
1129 if (sig.size() < width_hint)
1130 sig.extend_u0(width_hint, false);
1131 return sig;
1132 }
1133
1134 // replication of signals can be done directly using RTLIL::SigSpec
1135 case AST_REPLICATE: {
1136 RTLIL::SigSpec left = children[0]->genRTLIL();
1137 RTLIL::SigSpec right = children[1]->genRTLIL();
1138 if (!left.is_fully_const())
1139 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
1140 int count = left.as_int();
1141 RTLIL::SigSpec sig;
1142 for (int i = 0; i < count; i++)
1143 sig.append(right);
1144 if (sig.size() < width_hint)
1145 sig.extend_u0(width_hint, false);
1146 is_signed = false;
1147 return sig;
1148 }
1149
1150 // generate cells for unary operations: $not, $pos, $neg
1151 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1152 if (0) { case AST_POS: type_name = "$pos"; }
1153 if (0) { case AST_NEG: type_name = "$neg"; }
1154 {
1155 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1156 is_signed = children[0]->is_signed;
1157 int width = arg.size();
1158 if (width_hint > 0) {
1159 width = width_hint;
1160 widthExtend(this, arg, width, is_signed);
1161 }
1162 return uniop2rtlil(this, type_name, width, arg);
1163 }
1164
1165 // generate cells for binary operations: $and, $or, $xor, $xnor
1166 if (0) { case AST_BIT_AND: type_name = "$and"; }
1167 if (0) { case AST_BIT_OR: type_name = "$or"; }
1168 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1169 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1170 {
1171 if (width_hint < 0)
1172 detectSignWidth(width_hint, sign_hint);
1173 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1174 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1175 int width = max(left.size(), right.size());
1176 if (width_hint > 0)
1177 width = width_hint;
1178 is_signed = children[0]->is_signed && children[1]->is_signed;
1179 return binop2rtlil(this, type_name, width, left, right);
1180 }
1181
1182 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1183 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1184 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1185 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1186 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1187 {
1188 RTLIL::SigSpec arg = children[0]->genRTLIL();
1189 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
1190 return sig;
1191 }
1192
1193 // generate cells for unary operations: $reduce_bool
1194 // (this is actually just an $reduce_or, but for clarity a different cell type is used)
1195 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1196 {
1197 RTLIL::SigSpec arg = children[0]->genRTLIL();
1198 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
1199 return sig;
1200 }
1201
1202 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1203 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1204 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1205 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1206 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1207 {
1208 if (width_hint < 0)
1209 detectSignWidth(width_hint, sign_hint);
1210 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1211 RTLIL::SigSpec right = children[1]->genRTLIL();
1212 int width = width_hint > 0 ? width_hint : left.size();
1213 is_signed = children[0]->is_signed;
1214 return binop2rtlil(this, type_name, width, left, right);
1215 }
1216
1217 // generate cells for binary operations: $pow
1218 case AST_POW:
1219 {
1220 int right_width;
1221 bool right_signed;
1222 children[1]->detectSignWidth(right_width, right_signed);
1223 if (width_hint < 0)
1224 detectSignWidth(width_hint, sign_hint);
1225 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1226 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1227 int width = width_hint > 0 ? width_hint : left.size();
1228 is_signed = children[0]->is_signed;
1229 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1230 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1231 return binop2rtlil(this, "$pow", width, left, right);
1232 }
1233
1234 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1235 if (0) { case AST_LT: type_name = "$lt"; }
1236 if (0) { case AST_LE: type_name = "$le"; }
1237 if (0) { case AST_EQ: type_name = "$eq"; }
1238 if (0) { case AST_NE: type_name = "$ne"; }
1239 if (0) { case AST_EQX: type_name = "$eqx"; }
1240 if (0) { case AST_NEX: type_name = "$nex"; }
1241 if (0) { case AST_GE: type_name = "$ge"; }
1242 if (0) { case AST_GT: type_name = "$gt"; }
1243 {
1244 int width = max(width_hint, 1);
1245 width_hint = -1, sign_hint = true;
1246 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1247 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1248 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1249 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1250 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1251 return sig;
1252 }
1253
1254 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1255 if (0) { case AST_ADD: type_name = "$add"; }
1256 if (0) { case AST_SUB: type_name = "$sub"; }
1257 if (0) { case AST_MUL: type_name = "$mul"; }
1258 if (0) { case AST_DIV: type_name = "$div"; }
1259 if (0) { case AST_MOD: type_name = "$mod"; }
1260 {
1261 if (width_hint < 0)
1262 detectSignWidth(width_hint, sign_hint);
1263 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1264 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1265 #if 0
1266 int width = max(left.size(), right.size());
1267 if (width > width_hint && width_hint > 0)
1268 width = width_hint;
1269 if (width < width_hint) {
1270 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1271 width++;
1272 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1273 width = width_hint;
1274 if (type == AST_MUL)
1275 width = min(left.size() + right.size(), width_hint);
1276 }
1277 #else
1278 int width = max(max(left.size(), right.size()), width_hint);
1279 #endif
1280 is_signed = children[0]->is_signed && children[1]->is_signed;
1281 return binop2rtlil(this, type_name, width, left, right);
1282 }
1283
1284 // generate cells for binary operations: $logic_and, $logic_or
1285 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1286 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1287 {
1288 RTLIL::SigSpec left = children[0]->genRTLIL();
1289 RTLIL::SigSpec right = children[1]->genRTLIL();
1290 return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
1291 }
1292
1293 // generate cells for unary operations: $logic_not
1294 case AST_LOGIC_NOT:
1295 {
1296 RTLIL::SigSpec arg = children[0]->genRTLIL();
1297 return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
1298 }
1299
1300 // generate multiplexer for ternary operator (aka ?:-operator)
1301 case AST_TERNARY:
1302 {
1303 if (width_hint < 0)
1304 detectSignWidth(width_hint, sign_hint);
1305
1306 RTLIL::SigSpec cond = children[0]->genRTLIL();
1307 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1308 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1309
1310 if (cond.size() > 1)
1311 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1312
1313 int width = max(val1.size(), val2.size());
1314 is_signed = children[1]->is_signed && children[2]->is_signed;
1315 widthExtend(this, val1, width, is_signed);
1316 widthExtend(this, val2, width, is_signed);
1317
1318 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1319
1320 if (sig.size() < width_hint)
1321 sig.extend_u0(width_hint, sign_hint);
1322 return sig;
1323 }
1324
1325 // generate $memrd cells for memory read ports
1326 case AST_MEMRD:
1327 {
1328 std::stringstream sstr;
1329 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1330
1331 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1332 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1333
1334 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1335 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1336
1337 int mem_width, mem_size, addr_bits;
1338 is_signed = id2ast->is_signed;
1339 id2ast->meminfo(mem_width, mem_size, addr_bits);
1340
1341 RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
1342
1343 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1344 cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1345 cell->setPort("\\ADDR", addr_sig);
1346 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1347
1348 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1349 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1350 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1351
1352 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1353 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1354 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1355
1356 if (!sign_hint)
1357 is_signed = false;
1358
1359 return RTLIL::SigSpec(wire);
1360 }
1361
1362 // generate $memwr cells for memory write ports
1363 case AST_MEMWR:
1364 case AST_MEMINIT:
1365 {
1366 std::stringstream sstr;
1367 sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1368
1369 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
1370 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1371
1372 int mem_width, mem_size, addr_bits;
1373 id2ast->meminfo(mem_width, mem_size, addr_bits);
1374
1375 int num_words = 1;
1376 if (type == AST_MEMINIT) {
1377 if (children[2]->type != AST_CONSTANT)
1378 log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
1379 num_words = int(children[2]->asInt(false));
1380 cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
1381 }
1382
1383 SigSpec addr_sig = children[0]->genRTLIL();
1384
1385 cell->setPort("\\ADDR", addr_sig);
1386 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
1387
1388 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1389 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1390 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1391
1392 if (type == AST_MEMWR) {
1393 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1394 cell->setPort("\\EN", children[2]->genRTLIL());
1395 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1396 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1397 }
1398
1399 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1400 }
1401 break;
1402
1403 // generate $assert cells
1404 case AST_ASSERT:
1405 case AST_ASSUME:
1406 case AST_LIVE:
1407 case AST_FAIR:
1408 case AST_COVER:
1409 {
1410 const char *celltype = nullptr;
1411 if (type == AST_ASSERT) celltype = "$assert";
1412 if (type == AST_ASSUME) celltype = "$assume";
1413 if (type == AST_LIVE) celltype = "$live";
1414 if (type == AST_FAIR) celltype = "$fair";
1415 if (type == AST_COVER) celltype = "$cover";
1416
1417 log_assert(children.size() == 2);
1418
1419 RTLIL::SigSpec check = children[0]->genRTLIL();
1420 if (GetSize(check) != 1)
1421 check = current_module->ReduceBool(NEW_ID, check);
1422
1423 RTLIL::SigSpec en = children[1]->genRTLIL();
1424 if (GetSize(en) != 1)
1425 en = current_module->ReduceBool(NEW_ID, en);
1426
1427 IdString cellname;
1428 if (str.empty()) {
1429 std::stringstream sstr;
1430 sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
1431 cellname = sstr.str();
1432 } else {
1433 cellname = str;
1434 }
1435
1436 RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
1437 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1438
1439 for (auto &attr : attributes) {
1440 if (attr.second->type != AST_CONSTANT)
1441 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
1442 cell->attributes[attr.first] = attr.second->asAttrConst();
1443 }
1444
1445 cell->setPort("\\A", check);
1446 cell->setPort("\\EN", en);
1447 }
1448 break;
1449
1450 // add entries to current_module->connections for assignments (outside of always blocks)
1451 case AST_ASSIGN:
1452 {
1453 RTLIL::SigSpec left = children[0]->genRTLIL();
1454 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1455 if (left.has_const()) {
1456 RTLIL::SigSpec new_left, new_right;
1457 for (int i = 0; i < GetSize(left); i++)
1458 if (left[i].wire) {
1459 new_left.append(left[i]);
1460 new_right.append(right[i]);
1461 }
1462 log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
1463 " old assignment: %s = %s\n new assignment: %s = %s.\n",
1464 log_signal(left), log_signal(right),
1465 log_signal(new_left), log_signal(new_right));
1466 left = new_left;
1467 right = new_right;
1468 }
1469 current_module->connect(RTLIL::SigSig(left, right));
1470 }
1471 break;
1472
1473 // create an RTLIL::Cell for an AST_CELL
1474 case AST_CELL:
1475 {
1476 int port_counter = 0, para_counter = 0;
1477
1478 if (current_module->count_id(str) != 0)
1479 log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
1480
1481 RTLIL::Cell *cell = current_module->addCell(str, "");
1482 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1483 // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
1484 cell->set_bool_attribute("\\module_not_derived");
1485
1486 for (auto it = children.begin(); it != children.end(); it++) {
1487 AstNode *child = *it;
1488 if (child->type == AST_CELLTYPE) {
1489 cell->type = child->str;
1490 if (flag_icells && cell->type.substr(0, 2) == "\\$")
1491 cell->type = cell->type.substr(1);
1492 continue;
1493 }
1494 if (child->type == AST_PARASET) {
1495 int extra_const_flags = 0;
1496 IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
1497 if (child->children[0]->type == AST_REALVALUE) {
1498 log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
1499 log_id(cell), log_id(paraname), child->children[0]->realvalue);
1500 extra_const_flags = RTLIL::CONST_FLAG_REAL;
1501 auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
1502 strnode->cloneInto(child->children[0]);
1503 delete strnode;
1504 }
1505 if (child->children[0]->type != AST_CONSTANT)
1506 log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
1507 log_id(cell), log_id(paraname));
1508 cell->parameters[paraname] = child->children[0]->asParaConst();
1509 cell->parameters[paraname].flags |= extra_const_flags;
1510 continue;
1511 }
1512 if (child->type == AST_ARGUMENT) {
1513 RTLIL::SigSpec sig;
1514 if (child->children.size() > 0)
1515 sig = child->children[0]->genRTLIL();
1516 if (child->str.size() == 0) {
1517 char buf[100];
1518 snprintf(buf, 100, "$%d", ++port_counter);
1519 cell->setPort(buf, sig);
1520 } else {
1521 cell->setPort(child->str, sig);
1522 }
1523 continue;
1524 }
1525 log_abort();
1526 }
1527 for (auto &attr : attributes) {
1528 if (attr.second->type != AST_CONSTANT)
1529 log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
1530 cell->attributes[attr.first] = attr.second->asAttrConst();
1531 }
1532 if (cell->type.in("$specify2", "$specify3")) {
1533 int src_width = GetSize(cell->getPort("\\SRC"));
1534 int dst_width = GetSize(cell->getPort("\\DST"));
1535 bool full = cell->getParam("\\FULL").as_bool();
1536 if (!full && src_width != dst_width)
1537 log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
1538 if (cell->type == "$specify3") {
1539 int dat_width = GetSize(cell->getPort("\\DAT"));
1540 if (dat_width != dst_width)
1541 log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
1542 }
1543 cell->setParam("\\SRC_WIDTH", Const(src_width));
1544 cell->setParam("\\DST_WIDTH", Const(dst_width));
1545 }
1546 if (cell->type == "$specrule") {
1547 int src_width = GetSize(cell->getPort("\\SRC"));
1548 int dst_width = GetSize(cell->getPort("\\DST"));
1549 cell->setParam("\\SRC_WIDTH", Const(src_width));
1550 cell->setParam("\\DST_WIDTH", Const(dst_width));
1551 }
1552 }
1553 break;
1554
1555 // use ProcessGenerator for always blocks
1556 case AST_ALWAYS: {
1557 AstNode *always = this->clone();
1558 ProcessGenerator generator(always);
1559 ignoreThisSignalsInInitial.append(generator.outputSignals);
1560 delete always;
1561 } break;
1562
1563 case AST_INITIAL: {
1564 AstNode *always = this->clone();
1565 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1566 delete always;
1567 } break;
1568
1569 case AST_FCALL: {
1570 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
1571 {
1572 string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
1573 int width = width_hint;
1574
1575 if (GetSize(children) > 1)
1576 log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
1577 RTLIL::unescape_id(str).c_str(), GetSize(children));
1578
1579 if (GetSize(children) == 1) {
1580 if (children[0]->type != AST_CONSTANT)
1581 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
1582 RTLIL::unescape_id(str).c_str());
1583 width = children[0]->asInt(true);
1584 }
1585
1586 if (width <= 0)
1587 log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
1588
1589 Cell *cell = current_module->addCell(myid, str.substr(1));
1590 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1591 cell->parameters["\\WIDTH"] = width;
1592
1593 if (attributes.count("\\reg")) {
1594 auto &attr = attributes.at("\\reg");
1595 if (attr->type != AST_CONSTANT)
1596 log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
1597 cell->attributes["\\reg"] = attr->asAttrConst();
1598 }
1599
1600 Wire *wire = current_module->addWire(myid + "_wire", width);
1601 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1602 cell->setPort("\\Y", wire);
1603
1604 is_signed = sign_hint;
1605 return SigSpec(wire);
1606 }
1607 } /* fall through */
1608
1609 // everything should have been handled above -> print error if not.
1610 default:
1611 for (auto f : log_files)
1612 current_ast_mod->dumpAst(f, "verilog-ast> ");
1613 type_name = type2str(type);
1614 log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
1615 }
1616
1617 return RTLIL::SigSpec();
1618 }
1619
1620 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1621 // signals must be substituted before being used as input values (used by ProcessGenerator)
1622 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1623 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1624 {
1625 const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1626
1627 if (new_subst_ptr)
1628 genRTLIL_subst_ptr = new_subst_ptr;
1629
1630 bool sign_hint = true;
1631 int width_hint = width;
1632 detectSignWidthWorker(width_hint, sign_hint);
1633 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1634
1635 genRTLIL_subst_ptr = backup_subst_ptr;
1636
1637 if (width >= 0)
1638 sig.extend_u0(width, is_signed);
1639
1640 return sig;
1641 }
1642
1643 YOSYS_NAMESPACE_END