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Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "kernel/utils.h"
31 #include "libs/sha1/sha1.h"
32 #include "ast.h"
33
34 #include <sstream>
35 #include <stdarg.h>
36 #include <algorithm>
37
38 YOSYS_NAMESPACE_BEGIN
39
40 using namespace AST;
41 using namespace AST_INTERNAL;
42
43 // helper function for creating RTLIL code for unary operations
44 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
45 {
46 std::stringstream sstr;
47 sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
48
49 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
51
52 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
54
55 if (gen_attributes)
56 for (auto &attr : that->attributes) {
57 if (attr.second->type != AST_CONSTANT)
58 log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
59 cell->attributes[attr.first] = attr.second->asAttrConst();
60 }
61
62 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
63 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
64 cell->setPort("\\A", arg);
65
66 cell->parameters["\\Y_WIDTH"] = result_width;
67 cell->setPort("\\Y", wire);
68 return wire;
69 }
70
71 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
72 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
73 {
74 if (width <= sig.size()) {
75 sig.extend_u0(width, is_signed);
76 return;
77 }
78
79 std::stringstream sstr;
80 sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
81
82 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
83 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
84
85 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
86 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
87
88 if (that != NULL)
89 for (auto &attr : that->attributes) {
90 if (attr.second->type != AST_CONSTANT)
91 log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
92 cell->attributes[attr.first] = attr.second->asAttrConst();
93 }
94
95 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
96 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
97 cell->setPort("\\A", sig);
98
99 cell->parameters["\\Y_WIDTH"] = width;
100 cell->setPort("\\Y", wire);
101 sig = wire;
102 }
103
104 // helper function for creating RTLIL code for binary operations
105 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
106 {
107 std::stringstream sstr;
108 sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
109
110 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
111 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
112
113 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
114 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
115
116 for (auto &attr : that->attributes) {
117 if (attr.second->type != AST_CONSTANT)
118 log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
119 cell->attributes[attr.first] = attr.second->asAttrConst();
120 }
121
122 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
123 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
124
125 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
126 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
127
128 cell->setPort("\\A", left);
129 cell->setPort("\\B", right);
130
131 cell->parameters["\\Y_WIDTH"] = result_width;
132 cell->setPort("\\Y", wire);
133 return wire;
134 }
135
136 // helper function for creating RTLIL code for multiplexers
137 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
138 {
139 log_assert(cond.size() == 1);
140
141 std::stringstream sstr;
142 sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
143
144 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
145 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
146
147 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
148 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
149
150 for (auto &attr : that->attributes) {
151 if (attr.second->type != AST_CONSTANT)
152 log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
153 cell->attributes[attr.first] = attr.second->asAttrConst();
154 }
155
156 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
157
158 cell->setPort("\\A", right);
159 cell->setPort("\\B", left);
160 cell->setPort("\\S", cond);
161 cell->setPort("\\Y", wire);
162
163 return wire;
164 }
165
166 // helper class for converting AST always nodes to RTLIL processes
167 struct AST_INTERNAL::ProcessGenerator
168 {
169 // input and output structures
170 AstNode *always;
171 RTLIL::SigSpec initSyncSignals;
172 RTLIL::Process *proc;
173 RTLIL::SigSpec outputSignals;
174
175 // This always points to the RTLIL::CaseRule being filled at the moment
176 RTLIL::CaseRule *current_case;
177
178 // This map contains the replacement pattern to be used in the right hand side
179 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
180 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
181 // the value assigned in the first assignment. So when the first assignment is processed
182 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
183 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
184
185 // This map contains the replacement pattern to be used in the left hand side
186 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
187 // should not be connected to the signal foo. Instead it must be connected to the temporary
188 // signal that is used as input for the register that drives the signal foo.
189 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
190
191 // The code here generates a number of temporary signal for each output register. This
192 // map helps generating nice numbered names for all this temporary signals.
193 std::map<RTLIL::Wire*, int> new_temp_count;
194
195 // Buffer for generating the init action
196 RTLIL::SigSpec init_lvalue, init_rvalue;
197
198 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
199 {
200 // generate process and simple root case
201 proc = new RTLIL::Process;
202 proc->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
203 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->location.first_line, autoidx++);
204 for (auto &attr : always->attributes) {
205 if (attr.second->type != AST_CONSTANT)
206 log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n",
207 attr.first.c_str());
208 proc->attributes[attr.first] = attr.second->asAttrConst();
209 }
210 current_module->processes[proc->name] = proc;
211 current_case = &proc->root_case;
212
213 // create initial temporary signal for all output registers
214 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
215 collect_lvalues(subst_lvalue_from, always, true, true);
216 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
217 subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
218
219 bool found_global_syncs = false;
220 bool found_anyedge_syncs = false;
221 for (auto child : always->children)
222 {
223 if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
224 child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
225 found_global_syncs = true;
226 }
227 if (child->type == AST_EDGE) {
228 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock")
229 found_global_syncs = true;
230 else
231 found_anyedge_syncs = true;
232 }
233 }
234
235 if (found_anyedge_syncs) {
236 if (found_global_syncs)
237 log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
238 log("Note: Assuming pure combinatorial block at %s:%d.%d-%d.%d in\n", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
239 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
240 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
241 }
242
243 // create syncs for the process
244 bool found_clocked_sync = false;
245 for (auto child : always->children)
246 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
247 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
248 child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
249 continue;
250 found_clocked_sync = true;
251 if (found_global_syncs || found_anyedge_syncs)
252 log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n");
253 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
254 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
255 syncrule->signal = child->children[0]->genRTLIL();
256 if (GetSize(syncrule->signal) != 1)
257 log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
258 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
259 proc->syncs.push_back(syncrule);
260 }
261 if (proc->syncs.empty()) {
262 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
263 syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
264 syncrule->signal = RTLIL::SigSpec();
265 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
266 proc->syncs.push_back(syncrule);
267 }
268
269 // create initial assignments for the temporary signals
270 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
271 subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
272 } else {
273 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
274 }
275
276 // process the AST
277 for (auto child : always->children)
278 if (child->type == AST_BLOCK)
279 processAst(child);
280
281 if (initSyncSignals.size() > 0)
282 {
283 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
284 sync->type = RTLIL::SyncType::STi;
285 proc->syncs.push_back(sync);
286
287 log_assert(init_lvalue.size() == init_rvalue.size());
288
289 int offset = 0;
290 for (auto &init_lvalue_c : init_lvalue.chunks()) {
291 RTLIL::SigSpec lhs = init_lvalue_c;
292 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
293 remove_unwanted_lvalue_bits(lhs, rhs);
294 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
295 offset += lhs.size();
296 }
297 }
298
299 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
300 }
301
302 void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
303 {
304 RTLIL::SigSpec new_lhs, new_rhs;
305
306 log_assert(GetSize(lhs) == GetSize(rhs));
307 for (int i = 0; i < GetSize(lhs); i++) {
308 if (lhs[i].wire == nullptr)
309 continue;
310 new_lhs.append(lhs[i]);
311 new_rhs.append(rhs[i]);
312 }
313
314 lhs = new_lhs;
315 rhs = new_rhs;
316 }
317
318 // create new temporary signals
319 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
320 {
321 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
322
323 for (int i = 0; i < GetSize(chunks); i++)
324 {
325 RTLIL::SigChunk &chunk = chunks[i];
326 if (chunk.wire == NULL)
327 continue;
328
329 std::string wire_name;
330 do {
331 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
332 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
333 if (chunk.wire->name.str().find('$') != std::string::npos)
334 wire_name += stringf("$%d", autoidx++);
335 } while (current_module->wires_.count(wire_name) > 0);
336
337 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
338 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", always->filename.c_str(), always->location.first_line, always->location.first_column, always->location.last_line, always->location.last_column);
339
340 chunk.wire = wire;
341 chunk.offset = 0;
342 }
343
344 return chunks;
345 }
346
347 // recursively traverse the AST an collect all assigned signals
348 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
349 {
350 switch (ast->type)
351 {
352 case AST_CASE:
353 for (auto child : ast->children)
354 if (child != ast->children[0]) {
355 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
356 collect_lvalues(reg, child, type_eq, type_le, false);
357 }
358 break;
359
360 case AST_COND:
361 case AST_CONDX:
362 case AST_CONDZ:
363 case AST_ALWAYS:
364 case AST_INITIAL:
365 for (auto child : ast->children)
366 if (child->type == AST_BLOCK)
367 collect_lvalues(reg, child, type_eq, type_le, false);
368 break;
369
370 case AST_BLOCK:
371 for (auto child : ast->children) {
372 if (child->type == AST_ASSIGN_EQ && type_eq)
373 reg.append(child->children[0]->genRTLIL());
374 if (child->type == AST_ASSIGN_LE && type_le)
375 reg.append(child->children[0]->genRTLIL());
376 if (child->type == AST_CASE || child->type == AST_BLOCK)
377 collect_lvalues(reg, child, type_eq, type_le, false);
378 }
379 break;
380
381 default:
382 log_abort();
383 }
384
385 if (run_sort_and_unify) {
386 std::set<RTLIL::SigBit> sorted_reg;
387 for (auto bit : reg)
388 if (bit.wire)
389 sorted_reg.insert(bit);
390 reg = RTLIL::SigSpec(sorted_reg);
391 }
392 }
393
394 // remove all assignments to the given signal pattern in a case and all its children.
395 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
396 // function is called to clean up the first two assignments as they are overwritten by
397 // the third assignment.
398 void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
399 {
400 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
401 it->first.remove2(pattern, &it->second);
402
403 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
404 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
405 removeSignalFromCaseTree(pattern, *it2);
406 }
407
408 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
409 // are avoided and the generated $mux cells have a more "natural" size.
410 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
411 {
412 if (inSyncRule && initSyncSignals.size() > 0) {
413 init_lvalue.append(lvalue.extract(initSyncSignals));
414 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
415 lvalue.remove2(initSyncSignals, &rvalue);
416 }
417 log_assert(lvalue.size() == rvalue.size());
418
419 int offset = 0;
420 for (auto &lvalue_c : lvalue.chunks()) {
421 RTLIL::SigSpec lhs = lvalue_c;
422 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
423 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
424 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
425 remove_unwanted_lvalue_bits(lhs, rhs);
426 actions.push_back(RTLIL::SigSig(lhs, rhs));
427 offset += lhs.size();
428 }
429 }
430
431 // recursively process the AST and fill the RTLIL::Process
432 void processAst(AstNode *ast)
433 {
434 switch (ast->type)
435 {
436 case AST_BLOCK:
437 for (auto child : ast->children)
438 processAst(child);
439 break;
440
441 case AST_ASSIGN_EQ:
442 case AST_ASSIGN_LE:
443 {
444 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
445 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
446
447 pool<SigBit> lvalue_sigbits;
448 for (int i = 0; i < GetSize(lvalue); i++) {
449 if (lvalue_sigbits.count(lvalue[i]) > 0) {
450 unmapped_lvalue.remove(i);
451 lvalue.remove(i);
452 rvalue.remove(i--);
453 } else
454 lvalue_sigbits.insert(lvalue[i]);
455 }
456
457 lvalue.replace(subst_lvalue_map.stdmap());
458
459 if (ast->type == AST_ASSIGN_EQ) {
460 for (int i = 0; i < GetSize(unmapped_lvalue); i++)
461 subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
462 }
463
464 removeSignalFromCaseTree(lvalue, current_case);
465 remove_unwanted_lvalue_bits(lvalue, rvalue);
466 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
467 }
468 break;
469
470 case AST_CASE:
471 {
472 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
473 sw->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, ast->location.first_column, ast->location.last_line, ast->location.last_column);
474 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
475 current_case->switches.push_back(sw);
476
477 for (auto &attr : ast->attributes) {
478 if (attr.second->type != AST_CONSTANT)
479 log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
480 sw->attributes[attr.first] = attr.second->asAttrConst();
481 }
482
483 RTLIL::SigSpec this_case_eq_lvalue;
484 collect_lvalues(this_case_eq_lvalue, ast, true, false);
485
486 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
487
488 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
489 this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
490
491 RTLIL::CaseRule *default_case = NULL;
492 RTLIL::CaseRule *last_generated_case = NULL;
493 for (auto child : ast->children)
494 {
495 if (child == ast->children[0])
496 continue;
497 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
498
499 subst_lvalue_map.save();
500 subst_rvalue_map.save();
501
502 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
503 subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
504
505 RTLIL::CaseRule *backup_case = current_case;
506 current_case = new RTLIL::CaseRule;
507 current_case->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", child->filename.c_str(), child->location.first_line, child->location.first_column, child->location.last_line, child->location.last_column);
508 last_generated_case = current_case;
509 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
510 for (auto node : child->children) {
511 if (node->type == AST_DEFAULT)
512 default_case = current_case;
513 else if (node->type == AST_BLOCK)
514 processAst(node);
515 else
516 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
517 }
518 if (default_case != current_case)
519 sw->cases.push_back(current_case);
520 else
521 log_assert(current_case->compare.size() == 0);
522 current_case = backup_case;
523
524 subst_lvalue_map.restore();
525 subst_rvalue_map.restore();
526 }
527
528 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
529 #if 0
530 // this is a valid transformation, but as optimization it is premature.
531 // better: add a default case that assigns 'x' to everything, and let later
532 // optimizations take care of the rest
533 last_generated_case->compare.clear();
534 #else
535 default_case = new RTLIL::CaseRule;
536 addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
537 sw->cases.push_back(default_case);
538 #endif
539 } else {
540 if (default_case == NULL) {
541 default_case = new RTLIL::CaseRule;
542 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
543 }
544 sw->cases.push_back(default_case);
545 }
546
547 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
548 subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
549
550 this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
551 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
552 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
553 }
554 break;
555
556 case AST_WIRE:
557 log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n");
558 break;
559
560 case AST_ASSIGN:
561 log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n");
562 break;
563
564 case AST_PARAMETER:
565 case AST_LOCALPARAM:
566 log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n");
567 break;
568
569 case AST_NONE:
570 case AST_TCALL:
571 case AST_FOR:
572 break;
573
574 default:
575 // ast->dumpAst(NULL, "ast> ");
576 // current_ast_mod->dumpAst(NULL, "mod> ");
577 log_abort();
578 }
579 }
580 };
581
582 // detect sign and width of an expression
583 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
584 {
585 std::string type_name;
586 bool sub_sign_hint = true;
587 int sub_width_hint = -1;
588 int this_width = 0;
589 AstNode *range = NULL;
590 AstNode *id_ast = NULL;
591
592 bool local_found_real = false;
593 if (found_real == NULL)
594 found_real = &local_found_real;
595
596 switch (type)
597 {
598 case AST_NONE:
599 // unallocated enum, ignore
600 break;
601 case AST_CONSTANT:
602 width_hint = max(width_hint, int(bits.size()));
603 if (!is_signed)
604 sign_hint = false;
605 break;
606
607 case AST_REALVALUE:
608 *found_real = true;
609 width_hint = max(width_hint, 32);
610 break;
611
612 case AST_IDENTIFIER:
613 id_ast = id2ast;
614 if (id_ast == NULL && current_scope.count(str))
615 id_ast = current_scope.at(str);
616 if (!id_ast)
617 log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str());
618 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) {
619 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
620 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
621 } else
622 if (id_ast->children[0]->type != AST_CONSTANT)
623 while (id_ast->simplify(true, false, false, 1, -1, false, true)) { }
624 if (id_ast->children[0]->type == AST_CONSTANT)
625 this_width = id_ast->children[0]->bits.size();
626 else
627 log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str());
628 if (children.size() != 0)
629 range = children[0];
630 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
631 if (!id_ast->range_valid) {
632 if (id_ast->type == AST_AUTOWIRE)
633 this_width = 1;
634 else {
635 // current_ast_mod->dumpAst(NULL, "mod> ");
636 // log("---\n");
637 // id_ast->dumpAst(NULL, "decl> ");
638 // dumpAst(NULL, "ref> ");
639 log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str());
640 }
641 } else {
642 this_width = id_ast->range_left - id_ast->range_right + 1;
643 if (children.size() != 0)
644 range = children[0];
645 }
646 } else if (id_ast->type == AST_GENVAR) {
647 this_width = 32;
648 } else if (id_ast->type == AST_MEMORY) {
649 if (!id_ast->children[0]->range_valid)
650 log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
651 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
652 if (children.size() > 1)
653 range = children[1];
654 } else
655 log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str());
656 if (range) {
657 if (range->children.size() == 1)
658 this_width = 1;
659 else if (!range->range_valid) {
660 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
661 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
662 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
663 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
664 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
665 log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
666 this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
667 delete left_at_zero_ast;
668 delete right_at_zero_ast;
669 } else
670 this_width = range->range_left - range->range_right + 1;
671 sign_hint = false;
672 }
673 width_hint = max(width_hint, this_width);
674 if (!id_ast->is_signed)
675 sign_hint = false;
676 break;
677
678 case AST_TO_BITS:
679 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
680 if (children[0]->type != AST_CONSTANT)
681 log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n");
682 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
683 width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
684 break;
685
686 case AST_TO_SIGNED:
687 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
688 break;
689
690 case AST_TO_UNSIGNED:
691 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
692 sign_hint = false;
693 break;
694
695 case AST_CONCAT:
696 for (auto child : children) {
697 sub_width_hint = 0;
698 sub_sign_hint = true;
699 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
700 this_width += sub_width_hint;
701 }
702 width_hint = max(width_hint, this_width);
703 sign_hint = false;
704 break;
705
706 case AST_REPLICATE:
707 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
708 if (children[0]->type != AST_CONSTANT)
709 log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
710 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
711 width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
712 sign_hint = false;
713 break;
714
715 case AST_NEG:
716 case AST_BIT_NOT:
717 case AST_POS:
718 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
719 break;
720
721 case AST_BIT_AND:
722 case AST_BIT_OR:
723 case AST_BIT_XOR:
724 case AST_BIT_XNOR:
725 for (auto child : children)
726 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
727 break;
728
729 case AST_REDUCE_AND:
730 case AST_REDUCE_OR:
731 case AST_REDUCE_XOR:
732 case AST_REDUCE_XNOR:
733 case AST_REDUCE_BOOL:
734 width_hint = max(width_hint, 1);
735 sign_hint = false;
736 break;
737
738 case AST_SHIFT_LEFT:
739 case AST_SHIFT_RIGHT:
740 case AST_SHIFT_SLEFT:
741 case AST_SHIFT_SRIGHT:
742 case AST_POW:
743 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
744 break;
745
746 case AST_LT:
747 case AST_LE:
748 case AST_EQ:
749 case AST_NE:
750 case AST_EQX:
751 case AST_NEX:
752 case AST_GE:
753 case AST_GT:
754 width_hint = max(width_hint, 1);
755 sign_hint = false;
756 break;
757
758 case AST_ADD:
759 case AST_SUB:
760 case AST_MUL:
761 case AST_DIV:
762 case AST_MOD:
763 for (auto child : children)
764 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
765 break;
766
767 case AST_LOGIC_AND:
768 case AST_LOGIC_OR:
769 case AST_LOGIC_NOT:
770 width_hint = max(width_hint, 1);
771 sign_hint = false;
772 break;
773
774 case AST_TERNARY:
775 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
776 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
777 break;
778
779 case AST_MEMRD:
780 if (!id2ast->is_signed)
781 sign_hint = false;
782 if (!id2ast->children[0]->range_valid)
783 log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str());
784 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
785 width_hint = max(width_hint, this_width);
786 break;
787
788 case AST_FCALL:
789 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
790 if (GetSize(children) == 1) {
791 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
792 if (children[0]->type != AST_CONSTANT)
793 log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
794 RTLIL::unescape_id(str).c_str());
795 width_hint = max(width_hint, int(children[0]->asInt(true)));
796 }
797 break;
798 }
799 if (str == "\\$past") {
800 if (GetSize(children) > 0) {
801 sub_width_hint = 0;
802 sub_sign_hint = true;
803 children.at(0)->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
804 width_hint = max(width_hint, sub_width_hint);
805 sign_hint = false;
806 }
807 break;
808 }
809 /* fall through */
810
811 // everything should have been handled above -> print error if not.
812 default:
813 for (auto f : log_files)
814 current_ast_mod->dumpAst(f, "verilog-ast> ");
815 log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
816 }
817
818 if (*found_real)
819 sign_hint = true;
820 }
821
822 // detect sign and width of an expression
823 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
824 {
825 width_hint = -1;
826 sign_hint = true;
827 if (found_real)
828 *found_real = false;
829 detectSignWidthWorker(width_hint, sign_hint, found_real);
830 }
831
832 // create RTLIL from an AST node
833 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
834 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
835 //
836 // note that this function is influenced by a number of global variables that might be set when
837 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
838 // larger expressions into a netlist of cells.
839 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
840 {
841 // in the following big switch() statement there are some uses of
842 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
843 // cases this variable is used to hold the type of the cell that should
844 // be instantiated for this type of AST node.
845 std::string type_name;
846
847 current_filename = filename;
848
849 switch (type)
850 {
851 // simply ignore this nodes.
852 // they are either leftovers from simplify() or are referenced by other nodes
853 // and are only accessed here thru this references
854 case AST_NONE:
855 case AST_TASK:
856 case AST_FUNCTION:
857 case AST_DPI_FUNCTION:
858 case AST_AUTOWIRE:
859 case AST_DEFPARAM:
860 case AST_GENVAR:
861 case AST_GENFOR:
862 case AST_GENBLOCK:
863 case AST_GENIF:
864 case AST_GENCASE:
865 case AST_PACKAGE:
866 case AST_ENUM:
867 case AST_MODPORT:
868 case AST_MODPORTMEMBER:
869 case AST_TYPEDEF:
870 break;
871 case AST_INTERFACEPORT: {
872 // If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
873 // This is used by the hierarchy pass to know when it can replace interface connection with the individual
874 // signals.
875 RTLIL::Wire *wire = current_module->addWire(str, 1);
876 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
877 wire->start_offset = 0;
878 wire->port_id = port_id;
879 wire->port_input = true;
880 wire->port_output = true;
881 wire->set_bool_attribute("\\is_interface");
882 if (children.size() > 0) {
883 for(size_t i=0; i<children.size();i++) {
884 if(children[i]->type == AST_INTERFACEPORTTYPE) {
885 std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
886 wire->attributes["\\interface_type"] = res.first;
887 if (res.second != "")
888 wire->attributes["\\interface_modport"] = res.second;
889 break;
890 }
891 }
892 }
893 wire->upto = 0;
894 }
895 break;
896 case AST_INTERFACEPORTTYPE:
897 break;
898
899 // remember the parameter, needed for example in techmap
900 case AST_PARAMETER:
901 current_module->avail_parameters.insert(str);
902 /* fall through */
903 case AST_LOCALPARAM:
904 if (flag_pwires)
905 {
906 if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT)
907 log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str());
908
909 RTLIL::Const val = children[0]->bitsAsConst();
910 RTLIL::Wire *wire = current_module->addWire(str, GetSize(val));
911 current_module->connect(wire, val);
912
913 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
914 wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1;
915
916 for (auto &attr : attributes) {
917 if (attr.second->type != AST_CONSTANT)
918 log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
919 wire->attributes[attr.first] = attr.second->asAttrConst();
920 }
921 }
922 break;
923
924 // create an RTLIL::Wire for an AST_WIRE node
925 case AST_WIRE: {
926 if (current_module->wires_.count(str) != 0)
927 log_file_error(filename, location.first_line, "Re-definition of signal `%s'!\n", str.c_str());
928 if (!range_valid)
929 log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str());
930
931 if (!(range_left >= range_right || (range_left == -1 && range_right == 0)))
932 log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1);
933
934 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
935 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
936 wire->start_offset = range_right;
937 wire->port_id = port_id;
938 wire->port_input = is_input;
939 wire->port_output = is_output;
940 wire->upto = range_swapped;
941
942 for (auto &attr : attributes) {
943 if (attr.second->type != AST_CONSTANT)
944 log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
945 wire->attributes[attr.first] = attr.second->asAttrConst();
946 }
947
948 if (is_wand) wire->set_bool_attribute("\\wand");
949 if (is_wor) wire->set_bool_attribute("\\wor");
950 }
951 break;
952
953 // create an RTLIL::Memory for an AST_MEMORY node
954 case AST_MEMORY: {
955 if (current_module->memories.count(str) != 0)
956 log_file_error(filename, location.first_line, "Re-definition of memory `%s'!\n", str.c_str());
957
958 log_assert(children.size() >= 2);
959 log_assert(children[0]->type == AST_RANGE);
960 log_assert(children[1]->type == AST_RANGE);
961
962 if (!children[0]->range_valid || !children[1]->range_valid)
963 log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str());
964
965 RTLIL::Memory *memory = new RTLIL::Memory;
966 memory->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
967 memory->name = str;
968 memory->width = children[0]->range_left - children[0]->range_right + 1;
969 if (children[1]->range_right < children[1]->range_left) {
970 memory->start_offset = children[1]->range_right;
971 memory->size = children[1]->range_left - children[1]->range_right + 1;
972 } else {
973 memory->start_offset = children[1]->range_left;
974 memory->size = children[1]->range_right - children[1]->range_left + 1;
975 }
976 current_module->memories[memory->name] = memory;
977
978 for (auto &attr : attributes) {
979 if (attr.second->type != AST_CONSTANT)
980 log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
981 memory->attributes[attr.first] = attr.second->asAttrConst();
982 }
983 }
984 break;
985
986 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
987 case AST_CONSTANT:
988 case AST_REALVALUE:
989 {
990 if (width_hint < 0)
991 detectSignWidth(width_hint, sign_hint);
992 is_signed = sign_hint;
993
994 if (type == AST_CONSTANT) {
995 if (is_unsized) {
996 return RTLIL::SigSpec(bitsAsUnsizedConst(width_hint));
997 } else {
998 return RTLIL::SigSpec(bitsAsConst());
999 }
1000 }
1001
1002 RTLIL::SigSpec sig = realAsConst(width_hint);
1003 log_file_warning(filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
1004 return sig;
1005 }
1006
1007 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
1008 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
1009 // shifter cell is created and the output signal of this cell is returned
1010 case AST_IDENTIFIER:
1011 {
1012 RTLIL::Wire *wire = NULL;
1013 RTLIL::SigChunk chunk;
1014 bool is_interface = false;
1015
1016 int add_undef_bits_msb = 0;
1017 int add_undef_bits_lsb = 0;
1018
1019 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
1020 RTLIL::Wire *wire = current_module->addWire(str);
1021 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1022 wire->name = str;
1023 if (flag_autowire)
1024 log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
1025 else
1026 log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
1027 }
1028 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) {
1029 if (id2ast->children[0]->type != AST_CONSTANT)
1030 log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str());
1031 chunk = RTLIL::Const(id2ast->children[0]->bits);
1032 goto use_const_chunk;
1033 }
1034 else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
1035 RTLIL::Wire *current_wire = current_module->wire(str);
1036 if (current_wire->get_bool_attribute("\\is_interface"))
1037 is_interface = true;
1038 // Ignore
1039 }
1040 // If an identifier is found that is not already known, assume that it is an interface:
1041 else if (1) { // FIXME: Check if sv_mode first?
1042 is_interface = true;
1043 }
1044 else {
1045 log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
1046 }
1047
1048 if (id2ast->type == AST_MEMORY)
1049 log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
1050
1051 // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
1052 // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
1053 // with the individual signals:
1054 if (is_interface) {
1055 RTLIL::Wire *dummy_wire;
1056 std::string dummy_wire_name = "$dummywireforinterface" + str;
1057 if (current_module->wires_.count(dummy_wire_name))
1058 dummy_wire = current_module->wires_[dummy_wire_name];
1059 else {
1060 dummy_wire = current_module->addWire(dummy_wire_name);
1061 dummy_wire->set_bool_attribute("\\is_interface");
1062 }
1063 RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
1064 return tmp;
1065 }
1066
1067 wire = current_module->wires_[str];
1068 chunk.wire = wire;
1069 chunk.width = wire->width;
1070 chunk.offset = 0;
1071
1072 use_const_chunk:
1073 if (children.size() != 0) {
1074 if (children[0]->type != AST_RANGE)
1075 log_file_error(filename, location.first_line, "Single range expected.\n");
1076 int source_width = id2ast->range_left - id2ast->range_right + 1;
1077 int source_offset = id2ast->range_right;
1078 if (!children[0]->range_valid) {
1079 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
1080 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
1081 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1082 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1083 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
1084 log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
1085 int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
1086 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
1087 children[0]->children[1]->clone() : children[0]->children[0]->clone());
1088 fake_ast->children[0]->delete_children();
1089 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
1090 if (id2ast->range_right != 0) {
1091 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
1092 fake_ast->children[1]->is_signed = true;
1093 }
1094 if (id2ast->range_swapped) {
1095 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
1096 fake_ast->children[1]->is_signed = true;
1097 }
1098 if (GetSize(shift_val) >= 32)
1099 fake_ast->children[1]->is_signed = true;
1100 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
1101 delete left_at_zero_ast;
1102 delete right_at_zero_ast;
1103 delete fake_ast;
1104 return sig;
1105 } else {
1106 chunk.width = children[0]->range_left - children[0]->range_right + 1;
1107 chunk.offset = children[0]->range_right - source_offset;
1108 if (id2ast->range_swapped)
1109 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
1110 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
1111 if (chunk.width == 1)
1112 log_file_warning(filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
1113 str.c_str());
1114 else
1115 log_file_warning(filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
1116 children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
1117 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
1118 } else {
1119 if (chunk.width + chunk.offset > source_width) {
1120 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
1121 chunk.width -= add_undef_bits_msb;
1122 }
1123 if (chunk.offset < 0) {
1124 add_undef_bits_lsb = -chunk.offset;
1125 chunk.width -= add_undef_bits_lsb;
1126 chunk.offset += add_undef_bits_lsb;
1127 }
1128 if (add_undef_bits_lsb)
1129 log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
1130 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
1131 if (add_undef_bits_msb)
1132 log_file_warning(filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
1133 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
1134 }
1135 }
1136 }
1137
1138 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
1139
1140 if (genRTLIL_subst_ptr)
1141 sig.replace(*genRTLIL_subst_ptr);
1142
1143 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
1144 return sig;
1145 }
1146
1147 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
1148 case AST_TO_SIGNED:
1149 case AST_TO_UNSIGNED: {
1150 RTLIL::SigSpec sig = children[0]->genRTLIL();
1151 if (sig.size() < width_hint)
1152 sig.extend_u0(width_hint, sign_hint);
1153 is_signed = sign_hint;
1154 return sig;
1155 }
1156
1157 // concatenation of signals can be done directly using RTLIL::SigSpec
1158 case AST_CONCAT: {
1159 RTLIL::SigSpec sig;
1160 for (auto it = children.begin(); it != children.end(); it++)
1161 sig.append((*it)->genRTLIL());
1162 if (sig.size() < width_hint)
1163 sig.extend_u0(width_hint, false);
1164 return sig;
1165 }
1166
1167 // replication of signals can be done directly using RTLIL::SigSpec
1168 case AST_REPLICATE: {
1169 RTLIL::SigSpec left = children[0]->genRTLIL();
1170 RTLIL::SigSpec right = children[1]->genRTLIL();
1171 if (!left.is_fully_const())
1172 log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n");
1173 int count = left.as_int();
1174 RTLIL::SigSpec sig;
1175 for (int i = 0; i < count; i++)
1176 sig.append(right);
1177 if (sig.size() < width_hint)
1178 sig.extend_u0(width_hint, false);
1179 is_signed = false;
1180 return sig;
1181 }
1182
1183 // generate cells for unary operations: $not, $pos, $neg
1184 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1185 if (0) { case AST_POS: type_name = "$pos"; }
1186 if (0) { case AST_NEG: type_name = "$neg"; }
1187 {
1188 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1189 is_signed = children[0]->is_signed;
1190 int width = arg.size();
1191 if (width_hint > 0) {
1192 width = width_hint;
1193 widthExtend(this, arg, width, is_signed);
1194 }
1195 return uniop2rtlil(this, type_name, width, arg);
1196 }
1197
1198 // generate cells for binary operations: $and, $or, $xor, $xnor
1199 if (0) { case AST_BIT_AND: type_name = "$and"; }
1200 if (0) { case AST_BIT_OR: type_name = "$or"; }
1201 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1202 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1203 {
1204 if (width_hint < 0)
1205 detectSignWidth(width_hint, sign_hint);
1206 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1207 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1208 int width = max(left.size(), right.size());
1209 if (width_hint > 0)
1210 width = width_hint;
1211 is_signed = children[0]->is_signed && children[1]->is_signed;
1212 return binop2rtlil(this, type_name, width, left, right);
1213 }
1214
1215 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1216 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1217 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1218 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1219 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1220 {
1221 RTLIL::SigSpec arg = children[0]->genRTLIL();
1222 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
1223 return sig;
1224 }
1225
1226 // generate cells for unary operations: $reduce_bool
1227 // (this is actually just an $reduce_or, but for clarity a different cell type is used)
1228 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1229 {
1230 RTLIL::SigSpec arg = children[0]->genRTLIL();
1231 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
1232 return sig;
1233 }
1234
1235 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1236 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1237 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1238 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1239 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1240 {
1241 if (width_hint < 0)
1242 detectSignWidth(width_hint, sign_hint);
1243 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1244 RTLIL::SigSpec right = children[1]->genRTLIL();
1245 int width = width_hint > 0 ? width_hint : left.size();
1246 is_signed = children[0]->is_signed;
1247 return binop2rtlil(this, type_name, width, left, right);
1248 }
1249
1250 // generate cells for binary operations: $pow
1251 case AST_POW:
1252 {
1253 int right_width;
1254 bool right_signed;
1255 children[1]->detectSignWidth(right_width, right_signed);
1256 if (width_hint < 0)
1257 detectSignWidth(width_hint, sign_hint);
1258 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1259 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1260 int width = width_hint > 0 ? width_hint : left.size();
1261 is_signed = children[0]->is_signed;
1262 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1263 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1264 return binop2rtlil(this, "$pow", width, left, right);
1265 }
1266
1267 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1268 if (0) { case AST_LT: type_name = "$lt"; }
1269 if (0) { case AST_LE: type_name = "$le"; }
1270 if (0) { case AST_EQ: type_name = "$eq"; }
1271 if (0) { case AST_NE: type_name = "$ne"; }
1272 if (0) { case AST_EQX: type_name = "$eqx"; }
1273 if (0) { case AST_NEX: type_name = "$nex"; }
1274 if (0) { case AST_GE: type_name = "$ge"; }
1275 if (0) { case AST_GT: type_name = "$gt"; }
1276 {
1277 int width = max(width_hint, 1);
1278 width_hint = -1, sign_hint = true;
1279 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1280 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1281 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1282 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1283 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1284 return sig;
1285 }
1286
1287 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1288 if (0) { case AST_ADD: type_name = "$add"; }
1289 if (0) { case AST_SUB: type_name = "$sub"; }
1290 if (0) { case AST_MUL: type_name = "$mul"; }
1291 if (0) { case AST_DIV: type_name = "$div"; }
1292 if (0) { case AST_MOD: type_name = "$mod"; }
1293 {
1294 if (width_hint < 0)
1295 detectSignWidth(width_hint, sign_hint);
1296 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1297 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1298 #if 0
1299 int width = max(left.size(), right.size());
1300 if (width > width_hint && width_hint > 0)
1301 width = width_hint;
1302 if (width < width_hint) {
1303 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1304 width++;
1305 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1306 width = width_hint;
1307 if (type == AST_MUL)
1308 width = min(left.size() + right.size(), width_hint);
1309 }
1310 #else
1311 int width = max(max(left.size(), right.size()), width_hint);
1312 #endif
1313 is_signed = children[0]->is_signed && children[1]->is_signed;
1314 return binop2rtlil(this, type_name, width, left, right);
1315 }
1316
1317 // generate cells for binary operations: $logic_and, $logic_or
1318 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1319 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1320 {
1321 RTLIL::SigSpec left = children[0]->genRTLIL();
1322 RTLIL::SigSpec right = children[1]->genRTLIL();
1323 return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
1324 }
1325
1326 // generate cells for unary operations: $logic_not
1327 case AST_LOGIC_NOT:
1328 {
1329 RTLIL::SigSpec arg = children[0]->genRTLIL();
1330 return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
1331 }
1332
1333 // generate multiplexer for ternary operator (aka ?:-operator)
1334 case AST_TERNARY:
1335 {
1336 if (width_hint < 0)
1337 detectSignWidth(width_hint, sign_hint);
1338
1339 RTLIL::SigSpec cond = children[0]->genRTLIL();
1340 RTLIL::SigSpec sig;
1341 if (cond.is_fully_const()) {
1342 if (cond.as_bool()) {
1343 sig = children[1]->genRTLIL(width_hint, sign_hint);
1344 widthExtend(this, sig, sig.size(), children[1]->is_signed);
1345 }
1346 else {
1347 sig = children[2]->genRTLIL(width_hint, sign_hint);
1348 widthExtend(this, sig, sig.size(), children[2]->is_signed);
1349 }
1350 }
1351 else {
1352 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1353 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1354
1355 if (cond.size() > 1)
1356 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1357
1358 int width = max(val1.size(), val2.size());
1359 is_signed = children[1]->is_signed && children[2]->is_signed;
1360 widthExtend(this, val1, width, is_signed);
1361 widthExtend(this, val2, width, is_signed);
1362
1363 sig = mux2rtlil(this, cond, val1, val2);
1364 }
1365
1366 if (sig.size() < width_hint)
1367 sig.extend_u0(width_hint, sign_hint);
1368 return sig;
1369 }
1370
1371 // generate $memrd cells for memory read ports
1372 case AST_MEMRD:
1373 {
1374 std::stringstream sstr;
1375 sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
1376
1377 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1378 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
1379
1380 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1381 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), location.first_line);
1382
1383 int mem_width, mem_size, addr_bits;
1384 is_signed = id2ast->is_signed;
1385 id2ast->meminfo(mem_width, mem_size, addr_bits);
1386
1387 RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
1388
1389 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1390 cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1391 cell->setPort("\\ADDR", addr_sig);
1392 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1393
1394 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1395 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1396 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1397
1398 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1399 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1400 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1401
1402 if (!sign_hint)
1403 is_signed = false;
1404
1405 return RTLIL::SigSpec(wire);
1406 }
1407
1408 // generate $memwr cells for memory write ports
1409 case AST_MEMWR:
1410 case AST_MEMINIT:
1411 {
1412 std::stringstream sstr;
1413 sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
1414
1415 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
1416 cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1417
1418 int mem_width, mem_size, addr_bits;
1419 id2ast->meminfo(mem_width, mem_size, addr_bits);
1420
1421 int num_words = 1;
1422 if (type == AST_MEMINIT) {
1423 if (children[2]->type != AST_CONSTANT)
1424 log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
1425 num_words = int(children[2]->asInt(false));
1426 cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
1427 }
1428
1429 SigSpec addr_sig = children[0]->genRTLIL();
1430
1431 cell->setPort("\\ADDR", addr_sig);
1432 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
1433
1434 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1435 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1436 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1437
1438 if (type == AST_MEMWR) {
1439 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1440 cell->setPort("\\EN", children[2]->genRTLIL());
1441 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1442 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1443 }
1444
1445 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1446 }
1447 break;
1448
1449 // generate $assert cells
1450 case AST_ASSERT:
1451 case AST_ASSUME:
1452 case AST_LIVE:
1453 case AST_FAIR:
1454 case AST_COVER:
1455 {
1456 const char *celltype = nullptr;
1457 if (type == AST_ASSERT) celltype = "$assert";
1458 if (type == AST_ASSUME) celltype = "$assume";
1459 if (type == AST_LIVE) celltype = "$live";
1460 if (type == AST_FAIR) celltype = "$fair";
1461 if (type == AST_COVER) celltype = "$cover";
1462
1463 log_assert(children.size() == 2);
1464
1465 RTLIL::SigSpec check = children[0]->genRTLIL();
1466 if (GetSize(check) != 1)
1467 check = current_module->ReduceBool(NEW_ID, check);
1468
1469 RTLIL::SigSpec en = children[1]->genRTLIL();
1470 if (GetSize(en) != 1)
1471 en = current_module->ReduceBool(NEW_ID, en);
1472
1473 IdString cellname;
1474 if (str.empty()) {
1475 std::stringstream sstr;
1476 sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
1477 cellname = sstr.str();
1478 } else {
1479 cellname = str;
1480 }
1481
1482 RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
1483 cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1484
1485 for (auto &attr : attributes) {
1486 if (attr.second->type != AST_CONSTANT)
1487 log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
1488 cell->attributes[attr.first] = attr.second->asAttrConst();
1489 }
1490
1491 cell->setPort("\\A", check);
1492 cell->setPort("\\EN", en);
1493 }
1494 break;
1495
1496 // add entries to current_module->connections for assignments (outside of always blocks)
1497 case AST_ASSIGN:
1498 {
1499 RTLIL::SigSpec left = children[0]->genRTLIL();
1500 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1501 if (left.has_const()) {
1502 RTLIL::SigSpec new_left, new_right;
1503 for (int i = 0; i < GetSize(left); i++)
1504 if (left[i].wire) {
1505 new_left.append(left[i]);
1506 new_right.append(right[i]);
1507 }
1508 log_file_warning(filename, location.first_line, "Ignoring assignment to constant bits:\n"
1509 " old assignment: %s = %s\n new assignment: %s = %s.\n",
1510 log_signal(left), log_signal(right),
1511 log_signal(new_left), log_signal(new_right));
1512 left = new_left;
1513 right = new_right;
1514 }
1515 current_module->connect(RTLIL::SigSig(left, right));
1516 }
1517 break;
1518
1519 // create an RTLIL::Cell for an AST_CELL
1520 case AST_CELL:
1521 {
1522 int port_counter = 0, para_counter = 0;
1523
1524 if (current_module->count_id(str) != 0)
1525 log_file_error(filename, location.first_line, "Re-definition of cell `%s'!\n", str.c_str());
1526
1527 RTLIL::Cell *cell = current_module->addCell(str, "");
1528 cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1529 // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
1530 cell->set_bool_attribute("\\module_not_derived");
1531
1532 for (auto it = children.begin(); it != children.end(); it++) {
1533 AstNode *child = *it;
1534 if (child->type == AST_CELLTYPE) {
1535 cell->type = child->str;
1536 if (flag_icells && cell->type.begins_with("\\$"))
1537 cell->type = cell->type.substr(1);
1538 continue;
1539 }
1540 if (child->type == AST_PARASET) {
1541 int extra_const_flags = 0;
1542 IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
1543 if (child->children[0]->type == AST_REALVALUE) {
1544 log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
1545 log_id(cell), log_id(paraname), child->children[0]->realvalue);
1546 extra_const_flags = RTLIL::CONST_FLAG_REAL;
1547 auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
1548 strnode->cloneInto(child->children[0]);
1549 delete strnode;
1550 }
1551 if (child->children[0]->type != AST_CONSTANT)
1552 log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n",
1553 log_id(cell), log_id(paraname));
1554 cell->parameters[paraname] = child->children[0]->asParaConst();
1555 cell->parameters[paraname].flags |= extra_const_flags;
1556 continue;
1557 }
1558 if (child->type == AST_ARGUMENT) {
1559 RTLIL::SigSpec sig;
1560 if (child->children.size() > 0)
1561 sig = child->children[0]->genRTLIL();
1562 if (child->str.size() == 0) {
1563 char buf[100];
1564 snprintf(buf, 100, "$%d", ++port_counter);
1565 cell->setPort(buf, sig);
1566 } else {
1567 cell->setPort(child->str, sig);
1568 }
1569 continue;
1570 }
1571 log_abort();
1572 }
1573 for (auto &attr : attributes) {
1574 if (attr.second->type != AST_CONSTANT)
1575 log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
1576 cell->attributes[attr.first] = attr.second->asAttrConst();
1577 }
1578 if (cell->type == "$specify2") {
1579 int src_width = GetSize(cell->getPort("\\SRC"));
1580 int dst_width = GetSize(cell->getPort("\\DST"));
1581 bool full = cell->getParam("\\FULL").as_bool();
1582 if (!full && src_width != dst_width)
1583 log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
1584 cell->setParam("\\SRC_WIDTH", Const(src_width));
1585 cell->setParam("\\DST_WIDTH", Const(dst_width));
1586 }
1587 else if (cell->type == "$specify3") {
1588 int dat_width = GetSize(cell->getPort("\\DAT"));
1589 int dst_width = GetSize(cell->getPort("\\DST"));
1590 if (dat_width != dst_width)
1591 log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
1592 int src_width = GetSize(cell->getPort("\\SRC"));
1593 cell->setParam("\\SRC_WIDTH", Const(src_width));
1594 cell->setParam("\\DST_WIDTH", Const(dst_width));
1595 }
1596 else if (cell->type == "$specrule") {
1597 int src_width = GetSize(cell->getPort("\\SRC"));
1598 int dst_width = GetSize(cell->getPort("\\DST"));
1599 cell->setParam("\\SRC_WIDTH", Const(src_width));
1600 cell->setParam("\\DST_WIDTH", Const(dst_width));
1601 }
1602 }
1603 break;
1604
1605 // use ProcessGenerator for always blocks
1606 case AST_ALWAYS: {
1607 AstNode *always = this->clone();
1608 ProcessGenerator generator(always);
1609 ignoreThisSignalsInInitial.append(generator.outputSignals);
1610 delete always;
1611 } break;
1612
1613 case AST_INITIAL: {
1614 AstNode *always = this->clone();
1615 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1616 delete always;
1617 } break;
1618
1619 case AST_TECALL: {
1620 int sz = children.size();
1621 if (str == "$info") {
1622 if (sz > 0)
1623 log_file_info(filename, location.first_line, "%s.\n", children[0]->str.c_str());
1624 else
1625 log_file_info(filename, location.first_line, "\n");
1626 } else if (str == "$warning") {
1627 if (sz > 0)
1628 log_file_warning(filename, location.first_line, "%s.\n", children[0]->str.c_str());
1629 else
1630 log_file_warning(filename, location.first_line, "\n");
1631 } else if (str == "$error") {
1632 if (sz > 0)
1633 log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str());
1634 else
1635 log_file_error(filename, location.first_line, "\n");
1636 } else if (str == "$fatal") {
1637 // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish()
1638 // if no parameter is given, default value is 1
1639 // dollar_finish(sz ? children[0] : 1);
1640 // perhaps create & use log_file_fatal()
1641 if (sz > 0)
1642 log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str());
1643 else
1644 log_file_error(filename, location.first_line, "FATAL.\n");
1645 } else {
1646 log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str());
1647 }
1648 } break;
1649
1650 case AST_FCALL: {
1651 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
1652 {
1653 string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
1654 int width = width_hint;
1655
1656 if (GetSize(children) > 1)
1657 log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n",
1658 RTLIL::unescape_id(str).c_str(), GetSize(children));
1659
1660 if (GetSize(children) == 1) {
1661 if (children[0]->type != AST_CONSTANT)
1662 log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n",
1663 RTLIL::unescape_id(str).c_str());
1664 width = children[0]->asInt(true);
1665 }
1666
1667 if (width <= 0)
1668 log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
1669
1670 Cell *cell = current_module->addCell(myid, str.substr(1));
1671 cell->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1672 cell->parameters["\\WIDTH"] = width;
1673
1674 if (attributes.count("\\reg")) {
1675 auto &attr = attributes.at("\\reg");
1676 if (attr->type != AST_CONSTANT)
1677 log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
1678 cell->attributes["\\reg"] = attr->asAttrConst();
1679 }
1680
1681 Wire *wire = current_module->addWire(myid + "_wire", width);
1682 wire->attributes["\\src"] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
1683 cell->setPort("\\Y", wire);
1684
1685 is_signed = sign_hint;
1686 return SigSpec(wire);
1687 }
1688 } /* fall through */
1689
1690 // everything should have been handled above -> print error if not.
1691 default:
1692 for (auto f : log_files)
1693 current_ast_mod->dumpAst(f, "verilog-ast> ");
1694 type_name = type2str(type);
1695 log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
1696 }
1697
1698 return RTLIL::SigSpec();
1699 }
1700
1701 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1702 // signals must be substituted before being used as input values (used by ProcessGenerator)
1703 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1704 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1705 {
1706 const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1707
1708 if (new_subst_ptr)
1709 genRTLIL_subst_ptr = new_subst_ptr;
1710
1711 bool sign_hint = true;
1712 int width_hint = width;
1713 detectSignWidthWorker(width_hint, sign_hint);
1714 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1715
1716 genRTLIL_subst_ptr = backup_subst_ptr;
1717
1718 if (width >= 0)
1719 sig.extend_u0(width, is_signed);
1720
1721 return sig;
1722 }
1723
1724 YOSYS_NAMESPACE_END