projects / yosys.git / blob
? search:


791ee986761aeea34eb7ee4b9543a50e93e0171f
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
31 #include "ast.h"
32
33 #include <sstream>
34 #include <stdarg.h>
35 #include <assert.h>
36 #include <algorithm>
37
38 using namespace AST;
39 using namespace AST_INTERNAL;
40
41 // helper function for creating RTLIL code for unary operations
42 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
43 {
44 std::stringstream sstr;
45 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
46
47 RTLIL::Cell *cell = new RTLIL::Cell;
48 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
49 cell->name = sstr.str();
50 cell->type = type;
51 current_module->cells[cell->name] = cell;
52
53 RTLIL::Wire *wire = new RTLIL::Wire;
54 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
55 wire->name = cell->name + "_Y";
56 wire->width = result_width;
57 current_module->wires[wire->name] = wire;
58
59 RTLIL::SigChunk chunk;
60 chunk.wire = wire;
61 chunk.width = wire->width;
62 chunk.offset = 0;
63
64 RTLIL::SigSpec sig;
65 sig.chunks.push_back(chunk);
66 sig.width = chunk.width;
67
68 if (gen_attributes)
69 for (auto &attr : that->attributes) {
70 if (attr.second->type != AST_CONSTANT)
71 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
72 attr.first.c_str(), that->filename.c_str(), that->linenum);
73 cell->attributes[attr.first].str = attr.second->str;
74 cell->attributes[attr.first].bits = attr.second->bits;
75 }
76
77 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
78 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.width);
79 cell->connections["\\A"] = arg;
80
81 cell->parameters["\\Y_WIDTH"] = result_width;
82 cell->connections["\\Y"] = sig;
83 return sig;
84 }
85
86 // helper function for creating RTLIL code for binary operations
87 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
88 {
89 std::stringstream sstr;
90 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
91
92 RTLIL::Cell *cell = new RTLIL::Cell;
93 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
94 cell->name = sstr.str();
95 cell->type = type;
96 current_module->cells[cell->name] = cell;
97
98 RTLIL::Wire *wire = new RTLIL::Wire;
99 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
100 wire->name = cell->name + "_Y";
101 wire->width = result_width;
102 current_module->wires[wire->name] = wire;
103
104 RTLIL::SigChunk chunk;
105 chunk.wire = wire;
106 chunk.width = wire->width;
107 chunk.offset = 0;
108
109 RTLIL::SigSpec sig;
110 sig.chunks.push_back(chunk);
111 sig.width = chunk.width;
112
113 for (auto &attr : that->attributes) {
114 if (attr.second->type != AST_CONSTANT)
115 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
116 attr.first.c_str(), that->filename.c_str(), that->linenum);
117 cell->attributes[attr.first].str = attr.second->str;
118 cell->attributes[attr.first].bits = attr.second->bits;
119 }
120
121 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
122 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
123
124 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.width);
125 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.width);
126
127 cell->connections["\\A"] = left;
128 cell->connections["\\B"] = right;
129
130 cell->parameters["\\Y_WIDTH"] = result_width;
131 cell->connections["\\Y"] = sig;
132 return sig;
133 }
134
135 // helper function for creating RTLIL code for multiplexers
136 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
137 {
138 assert(cond.width == 1);
139
140 std::stringstream sstr;
141 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
142
143 RTLIL::Cell *cell = new RTLIL::Cell;
144 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
145 cell->name = sstr.str();
146 cell->type = "$mux";
147 current_module->cells[cell->name] = cell;
148
149 RTLIL::Wire *wire = new RTLIL::Wire;
150 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
151 wire->name = cell->name + "_Y";
152 wire->width = left.width;
153 current_module->wires[wire->name] = wire;
154
155 RTLIL::SigChunk chunk;
156 chunk.wire = wire;
157 chunk.width = wire->width;
158 chunk.offset = 0;
159
160 RTLIL::SigSpec sig;
161 sig.chunks.push_back(chunk);
162 sig.width = chunk.width;
163
164 for (auto &attr : that->attributes) {
165 if (attr.second->type != AST_CONSTANT)
166 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
167 attr.first.c_str(), that->filename.c_str(), that->linenum);
168 cell->attributes[attr.first].str = attr.second->str;
169 cell->attributes[attr.first].bits = attr.second->bits;
170 }
171
172 cell->parameters["\\WIDTH"] = RTLIL::Const(left.width);
173
174 cell->connections["\\A"] = right;
175 cell->connections["\\B"] = left;
176 cell->connections["\\S"] = cond;
177 cell->connections["\\Y"] = sig;
178
179 return sig;
180 }
181
182 // helper class for converting AST always nodes to RTLIL processes
183 struct AST_INTERNAL::ProcessGenerator
184 {
185 // input and output structures
186 AstNode *always;
187 RTLIL::SigSpec skipSyncSignals;
188 RTLIL::Process *proc;
189 const RTLIL::SigSpec &outputSignals;
190
191 // This always points to the RTLIL::CaseRule beeing filled at the moment
192 RTLIL::CaseRule *current_case;
193
194 // This two variables contain the replacement pattern to be used in the right hand side
195 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
196 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
197 // the value assigned in the first assignment. So when the first assignement is processed
198 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
199 RTLIL::SigSpec subst_rvalue_from, subst_rvalue_to;
200
201 // This two variables contain the replacement pattern to be used in the left hand side
202 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
203 // should not be connected to the signal foo. Instead it must be connected to the temporary
204 // signal that is used as input for the register that drives the signal foo.
205 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
206
207 // The code here generates a number of temprorary signal for each output register. This
208 // map helps generating nice numbered names for all this temporary signals.
209 std::map<RTLIL::Wire*, int> new_temp_count;
210
211 ProcessGenerator(AstNode *always, RTLIL::SigSpec skipSyncSignalsArg = RTLIL::SigSpec()) : always(always), skipSyncSignals(skipSyncSignalsArg), outputSignals(subst_lvalue_from)
212 {
213 // generate process and simple root case
214 proc = new RTLIL::Process;
215 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, RTLIL::autoidx++);
216 for (auto &attr : always->attributes) {
217 if (attr.second->type != AST_CONSTANT)
218 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
219 attr.first.c_str(), always->filename.c_str(), always->linenum);
220 proc->attributes[attr.first].str = attr.second->str;
221 proc->attributes[attr.first].bits = attr.second->bits;
222 }
223 current_module->processes[proc->name] = proc;
224 current_case = &proc->root_case;
225
226 // create initial temporary signal for all output registers
227 collect_lvalues(subst_lvalue_from, always, true, true);
228 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
229
230 bool found_anyedge_syncs = false;
231 for (auto child : always->children)
232 if (child->type == AST_EDGE)
233 found_anyedge_syncs = true;
234
235 if (found_anyedge_syncs) {
236 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
237 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
238 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
239 }
240
241 // create syncs for the process
242 bool found_clocked_sync = false;
243 for (auto child : always->children)
244 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
245 found_clocked_sync = true;
246 if (found_anyedge_syncs)
247 log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
248 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
249 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
250 syncrule->signal = child->children[0]->genRTLIL();
251 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
252 proc->syncs.push_back(syncrule);
253 }
254 if (proc->syncs.empty()) {
255 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
256 syncrule->type = RTLIL::STa;
257 syncrule->signal = RTLIL::SigSpec();
258 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
259 proc->syncs.push_back(syncrule);
260 }
261
262 // create initial assignments for the temporary signals
263 if ((flag_nolatches || always->attributes.count("\\nolatches") > 0 || current_module->attributes.count("\\nolatches")) && !found_clocked_sync) {
264 subst_rvalue_from = subst_lvalue_from;
265 subst_rvalue_to = RTLIL::SigSpec(RTLIL::State::Sx, subst_rvalue_from.width);
266 } else {
267 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
268 }
269
270 // process the AST
271 for (auto child : always->children)
272 if (child->type == AST_BLOCK)
273 processAst(child);
274 }
275
276 // create new temporary signals
277 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
278 {
279 sig.optimize();
280 for (size_t i = 0; i < sig.chunks.size(); i++)
281 {
282 RTLIL::SigChunk &chunk = sig.chunks[i];
283 if (chunk.wire == NULL)
284 continue;
285
286 RTLIL::Wire *wire = new RTLIL::Wire;
287 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
288 do {
289 wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
290 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
291 } while (current_module->wires.count(wire->name) > 0);
292 wire->width = chunk.width;
293 current_module->wires[wire->name] = wire;
294
295 chunk.wire = wire;
296 chunk.offset = 0;
297 }
298 return sig;
299 }
300
301 // recursively traverse the AST an collect all assigned signals
302 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
303 {
304 switch (ast->type)
305 {
306 case AST_CASE:
307 for (auto child : ast->children)
308 if (child != ast->children[0]) {
309 assert(child->type == AST_COND);
310 collect_lvalues(reg, child, type_eq, type_le, false);
311 }
312 break;
313
314 case AST_COND:
315 case AST_ALWAYS:
316 case AST_INITIAL:
317 for (auto child : ast->children)
318 if (child->type == AST_BLOCK)
319 collect_lvalues(reg, child, type_eq, type_le, false);
320 break;
321
322 case AST_BLOCK:
323 for (auto child : ast->children) {
324 if (child->type == AST_ASSIGN_EQ && type_eq)
325 reg.append(child->children[0]->genRTLIL());
326 if (child->type == AST_ASSIGN_LE && type_le)
327 reg.append(child->children[0]->genRTLIL());
328 if (child->type == AST_CASE || child->type == AST_BLOCK)
329 collect_lvalues(reg, child, type_eq, type_le, false);
330 }
331 break;
332
333 default:
334 assert(0);
335 }
336
337 if (run_sort_and_unify)
338 reg.sort_and_unify();
339 }
340
341 // remove all assignments to the given signal pattern in a case and all its children.
342 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
343 // function is called to clean up the first two assignments as they are overwritten by
344 // the third assignment.
345 void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
346 {
347 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
348 it->first.remove2(pattern, &it->second);
349
350 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
351 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
352 removeSignalFromCaseTree(pattern, *it2);
353 }
354
355 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
356 // are avoided and the generated $mux cells have a more "natural" size.
357 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
358 {
359 if (inSyncRule)
360 lvalue.remove2(skipSyncSignals, &rvalue);
361 assert(lvalue.width == rvalue.width);
362 lvalue.optimize();
363 rvalue.optimize();
364
365 int offset = 0;
366 for (size_t i = 0; i < lvalue.chunks.size(); i++) {
367 RTLIL::SigSpec lhs = lvalue.chunks[i];
368 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue.chunks[i].width);
369 if (inSyncRule && lvalue.chunks[i].wire && lvalue.chunks[i].wire->attributes.count("\\nosync"))
370 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.width);
371 actions.push_back(RTLIL::SigSig(lhs, rhs));
372 offset += lhs.width;
373 }
374 }
375
376 // recursively process the AST and fill the RTLIL::Process
377 void processAst(AstNode *ast)
378 {
379 switch (ast->type)
380 {
381 case AST_BLOCK:
382 for (auto child : ast->children)
383 processAst(child);
384 break;
385
386 case AST_ASSIGN_EQ:
387 case AST_ASSIGN_LE:
388 {
389 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
390 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.width, &subst_rvalue_from, &subst_rvalue_to);
391 lvalue.replace(subst_lvalue_from, subst_lvalue_to);
392
393 if (ast->type == AST_ASSIGN_EQ) {
394 subst_rvalue_from.remove2(unmapped_lvalue, &subst_rvalue_to);
395 subst_rvalue_from.append(unmapped_lvalue);
396 subst_rvalue_from.optimize();
397 subst_rvalue_to.append(rvalue);
398 subst_rvalue_to.optimize();
399 }
400
401 removeSignalFromCaseTree(lvalue, current_case);
402 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
403 }
404 break;
405
406 case AST_CASE:
407 {
408 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
409 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_from, &subst_rvalue_to);
410 current_case->switches.push_back(sw);
411
412 for (auto &attr : ast->attributes) {
413 if (attr.second->type != AST_CONSTANT)
414 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
415 attr.first.c_str(), ast->filename.c_str(), ast->linenum);
416 sw->attributes[attr.first].str = attr.second->str;
417 sw->attributes[attr.first].bits = attr.second->bits;
418 }
419
420 RTLIL::SigSpec this_case_eq_lvalue;
421 collect_lvalues(this_case_eq_lvalue, ast, true, false);
422
423 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
424
425 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
426 this_case_eq_rvalue.replace(subst_rvalue_from, subst_rvalue_to);
427
428 RTLIL::SigSpec backup_subst_lvalue_from = subst_lvalue_from;
429 RTLIL::SigSpec backup_subst_lvalue_to = subst_lvalue_to;
430
431 RTLIL::SigSpec backup_subst_rvalue_from = subst_rvalue_from;
432 RTLIL::SigSpec backup_subst_rvalue_to = subst_rvalue_to;
433
434 bool generated_default_case = false;
435 RTLIL::CaseRule *last_generated_case = NULL;
436 for (auto child : ast->children)
437 {
438 if (child == ast->children[0] || generated_default_case)
439 continue;
440 assert(child->type == AST_COND);
441
442 subst_lvalue_from = backup_subst_lvalue_from;
443 subst_lvalue_to = backup_subst_lvalue_to;
444
445 subst_rvalue_from = backup_subst_rvalue_from;
446 subst_rvalue_to = backup_subst_rvalue_to;
447
448 subst_lvalue_from.remove2(this_case_eq_lvalue, &subst_lvalue_to);
449 subst_lvalue_from.append(this_case_eq_lvalue);
450 subst_lvalue_from.optimize();
451 subst_lvalue_to.append(this_case_eq_ltemp);
452 subst_lvalue_to.optimize();
453
454 RTLIL::CaseRule *backup_case = current_case;
455 current_case = new RTLIL::CaseRule;
456 last_generated_case = current_case;
457 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
458 for (auto node : child->children) {
459 if (node->type == AST_DEFAULT) {
460 generated_default_case = true;
461 current_case->compare.clear();
462 } else if (node->type == AST_BLOCK) {
463 processAst(node);
464 } else if (!generated_default_case)
465 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width, &subst_rvalue_from, &subst_rvalue_to));
466 }
467 sw->cases.push_back(current_case);
468 current_case = backup_case;
469 }
470
471 if (last_generated_case != NULL && ast->attributes.count("\\full_case") > 0) {
472 last_generated_case->compare.clear();
473 } else if (!generated_default_case) {
474 RTLIL::CaseRule *default_case = new RTLIL::CaseRule;
475 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
476 sw->cases.push_back(default_case);
477 }
478
479 subst_lvalue_from = backup_subst_lvalue_from;
480 subst_lvalue_to = backup_subst_lvalue_to;
481
482 subst_rvalue_from = backup_subst_rvalue_from;
483 subst_rvalue_to = backup_subst_rvalue_to;
484
485 subst_rvalue_from.remove2(this_case_eq_lvalue, &subst_rvalue_to);
486 subst_rvalue_from.append(this_case_eq_lvalue);
487 subst_rvalue_from.optimize();
488 subst_rvalue_to.append(this_case_eq_ltemp);
489 subst_rvalue_to.optimize();
490
491 this_case_eq_lvalue.replace(subst_lvalue_from, subst_lvalue_to);
492 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
493 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
494 }
495 break;
496
497 case AST_TCALL:
498 case AST_FOR:
499 break;
500
501 default:
502 assert(0);
503 }
504 }
505 };
506
507 // detect sign and width of an expression
508 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
509 {
510 std::string type_name;
511 bool dummy_sign_hint = true;
512 // int dummy_width_hint = -1;
513
514 switch (type)
515 {
516 case AST_CONSTANT:
517 width_hint = std::max(width_hint, int(bits.size()));
518 if (!is_signed)
519 sign_hint = false;
520 break;
521
522 case AST_IDENTIFIER:
523 if ((id2ast && !id2ast->is_signed) || children.size() > 0)
524 sign_hint = false;
525 width_hint = std::max(width_hint, genRTLIL().width);
526 break;
527
528 case AST_TO_SIGNED:
529 children.at(0)->detectSignWidthWorker(width_hint, dummy_sign_hint);
530 break;
531
532 case AST_TO_UNSIGNED:
533 children.at(0)->detectSignWidthWorker(width_hint, dummy_sign_hint);
534 sign_hint = false;
535 break;
536
537 case AST_CONCAT:
538 case AST_REPLICATE:
539 width_hint = std::max(width_hint, genRTLIL().width);
540 sign_hint = false;
541 break;
542
543 case AST_NEG:
544 case AST_BIT_NOT:
545 case AST_POS:
546 children[0]->detectSignWidthWorker(width_hint, sign_hint);
547 break;
548
549 case AST_BIT_AND:
550 case AST_BIT_OR:
551 case AST_BIT_XOR:
552 case AST_BIT_XNOR:
553 for (auto child : children)
554 child->detectSignWidthWorker(width_hint, sign_hint);
555 break;
556
557 case AST_REDUCE_AND:
558 case AST_REDUCE_OR:
559 case AST_REDUCE_XOR:
560 case AST_REDUCE_XNOR:
561 case AST_REDUCE_BOOL:
562 width_hint = std::max(width_hint, 1);
563 sign_hint = false;
564 break;
565
566 case AST_SHIFT_LEFT:
567 case AST_SHIFT_RIGHT:
568 case AST_SHIFT_SLEFT:
569 case AST_SHIFT_SRIGHT:
570 children[0]->detectSignWidthWorker(width_hint, sign_hint);
571 break;
572
573 case AST_LT:
574 case AST_LE:
575 case AST_EQ:
576 case AST_NE:
577 case AST_GE:
578 case AST_GT:
579 width_hint = std::max(width_hint, 1);
580 sign_hint = false;
581 break;
582
583 case AST_ADD:
584 case AST_SUB:
585 case AST_MUL:
586 case AST_DIV:
587 case AST_MOD:
588 case AST_POW:
589 for (auto child : children)
590 child->detectSignWidthWorker(width_hint, sign_hint);
591 break;
592
593 case AST_LOGIC_AND:
594 case AST_LOGIC_OR:
595 case AST_LOGIC_NOT:
596 width_hint = std::max(width_hint, 1);
597 sign_hint = false;
598 break;
599
600 case AST_TERNARY:
601 children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
602 children.at(2)->detectSignWidthWorker(width_hint, sign_hint);
603 break;
604
605 case AST_MEMRD:
606 if (!is_signed)
607 sign_hint = false;
608 width_hint = std::max(width_hint, current_module->memories.at(str)->width);
609 break;
610
611 // everything should have been handled above -> print error if not.
612 default:
613 for (auto f : log_files)
614 current_ast->dumpAst(f, "verilog-ast> ");
615 log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
616 type2str(type).c_str(), filename.c_str(), linenum);
617 }
618 }
619
620 // detect sign and width of an expression
621 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint)
622 {
623 width_hint = -1, sign_hint = true;
624 detectSignWidthWorker(width_hint, sign_hint);
625 }
626
627 // create RTLIL from an AST node
628 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
629 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
630 //
631 // note that this function is influenced by a number of global variables that might be set when
632 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
633 // larger expressions into a netlist of cells.
634 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
635 {
636 // in the following big switch() statement there are some uses of
637 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
638 // cases this variable is used to hold the type of the cell that should
639 // be instanciated for this type of AST node.
640 std::string type_name;
641
642 current_filename = filename;
643 set_line_num(linenum);
644
645 switch (type)
646 {
647 // simply ignore this nodes.
648 // they are eighter leftovers from simplify() or are referenced by other nodes
649 // and are only accessed here thru this references
650 case AST_TASK:
651 case AST_FUNCTION:
652 case AST_AUTOWIRE:
653 case AST_PARAMETER:
654 case AST_LOCALPARAM:
655 case AST_DEFPARAM:
656 case AST_GENVAR:
657 case AST_GENFOR:
658 case AST_GENBLOCK:
659 case AST_GENIF:
660 break;
661
662 // create an RTLIL::Wire for an AST_WIRE node
663 case AST_WIRE: {
664 if (current_module->wires.count(str) != 0)
665 log_error("Re-definition of signal `%s' at %s:%d!\n",
666 str.c_str(), filename.c_str(), linenum);
667 if (!range_valid)
668 log_error("Signal `%s' with non-constant width at %s:%d!\n",
669 str.c_str(), filename.c_str(), linenum);
670
671 if (range_left < range_right && (range_left != -1 || range_right != 0)) {
672 int tmp = range_left;
673 range_left = range_right;
674 range_right = tmp;
675 }
676
677 RTLIL::Wire *wire = new RTLIL::Wire;
678 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
679 wire->name = str;
680 wire->width = range_left - range_right + 1;
681 wire->start_offset = range_right;
682 wire->port_id = port_id;
683 wire->port_input = is_input;
684 wire->port_output = is_output;
685 current_module->wires[wire->name] = wire;
686
687 for (auto &attr : attributes) {
688 if (attr.second->type != AST_CONSTANT)
689 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
690 attr.first.c_str(), filename.c_str(), linenum);
691 wire->attributes[attr.first].str = attr.second->str;
692 wire->attributes[attr.first].bits = attr.second->bits;
693 }
694 }
695 break;
696
697 // create an RTLIL::Memory for an AST_MEMORY node
698 case AST_MEMORY: {
699 if (current_module->memories.count(str) != 0)
700 log_error("Re-definition of memory `%s' at %s:%d!\n",
701 str.c_str(), filename.c_str(), linenum);
702
703 assert(children.size() >= 2);
704 assert(children[0]->type == AST_RANGE);
705 assert(children[1]->type == AST_RANGE);
706
707 if (!children[0]->range_valid || !children[1]->range_valid)
708 log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
709 str.c_str(), filename.c_str(), linenum);
710
711 RTLIL::Memory *memory = new RTLIL::Memory;
712 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
713 memory->name = str;
714 memory->width = children[0]->range_left - children[0]->range_right + 1;
715 memory->start_offset = children[0]->range_right;
716 memory->size = children[1]->range_left - children[1]->range_right;
717 current_module->memories[memory->name] = memory;
718
719 if (memory->size < 0)
720 memory->size *= -1;
721 memory->size += std::min(children[1]->range_left, children[1]->range_right) + 1;
722
723 for (auto &attr : attributes) {
724 if (attr.second->type != AST_CONSTANT)
725 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
726 attr.first.c_str(), filename.c_str(), linenum);
727 memory->attributes[attr.first].str = attr.second->str;
728 memory->attributes[attr.first].bits = attr.second->bits;
729 }
730 }
731 break;
732
733 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
734 case AST_CONSTANT:
735 {
736 if (width_hint < 0)
737 detectSignWidth(width_hint, sign_hint);
738
739 RTLIL::SigChunk chunk;
740 chunk.wire = NULL;
741 chunk.data.bits = bits;
742 chunk.width = bits.size();
743 chunk.offset = 0;
744
745 RTLIL::SigSpec sig;
746 sig.chunks.push_back(chunk);
747 sig.width = chunk.width;
748
749 is_signed = sign_hint;
750 return sig;
751 }
752
753 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
754 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
755 // shifter cell is created and the output signal of this cell is returned
756 case AST_IDENTIFIER:
757 {
758 RTLIL::Wire *wire = NULL;
759 RTLIL::SigChunk chunk;
760
761 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) {
762 RTLIL::Wire *wire = new RTLIL::Wire;
763 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
764 wire->name = str;
765 if (width_hint >= 0) {
766 wire->width = width_hint;
767 log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n",
768 str.c_str(), width_hint, filename.c_str(), linenum);
769 } else {
770 log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n",
771 str.c_str(), filename.c_str(), linenum);
772 }
773 wire->auto_width = true;
774 current_module->wires[str] = wire;
775 }
776 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
777 chunk = RTLIL::Const(id2ast->children[0]->bits);
778 goto use_const_chunk;
779 }
780 else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
781 id2ast->type != AST_MEMORY) || current_module->wires.count(str) == 0)
782 log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
783 str.c_str(), filename.c_str(), linenum);
784
785 if (id2ast->type == AST_MEMORY)
786 log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
787 str.c_str(), filename.c_str(), linenum);
788
789 wire = current_module->wires[str];
790 chunk.wire = wire;
791 chunk.width = wire->width;
792 chunk.offset = 0;
793
794 use_const_chunk:
795 if (children.size() != 0) {
796 assert(children[0]->type == AST_RANGE);
797 if (!children[0]->range_valid) {
798 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
799 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
800 while (left_at_zero_ast->simplify(true, true, false, 1)) { }
801 while (right_at_zero_ast->simplify(true, true, false, 1)) { }
802 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
803 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
804 str.c_str(), filename.c_str(), linenum);
805 int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
806 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
807 children[0]->children[1]->clone() : children[0]->children[0]->clone());
808 fake_ast->children[0]->delete_children();
809 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width,
810 fake_ast->children[0]->genRTLIL(), fake_ast->children[1]->genRTLIL());
811 delete left_at_zero_ast;
812 delete right_at_zero_ast;
813 delete fake_ast;
814 return sig;
815 } else {
816 chunk.offset = children[0]->range_right - id2ast->range_right;
817 chunk.width = children[0]->range_left - children[0]->range_right + 1;
818 if (children[0]->range_left > id2ast->range_left || id2ast->range_right > children[0]->range_right)
819 log_error("Range select out of bounds on signal `%s' at %s:%d!\n",
820 str.c_str(), filename.c_str(), linenum);
821 }
822 }
823
824 RTLIL::SigSpec sig;
825 sig.chunks.push_back(chunk);
826 sig.width = chunk.width;
827
828 if (genRTLIL_subst_from && genRTLIL_subst_to)
829 sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
830
831 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
832 return sig;
833 }
834
835 // just pass thru the signal. the parent will evaluated the is_signed property and inperpret the SigSpec accordingly
836 case AST_TO_SIGNED:
837 case AST_TO_UNSIGNED: {
838 RTLIL::SigSpec sig = children[0]->genRTLIL();
839 is_signed = sign_hint;
840 return sig;
841 }
842
843 // concatenation of signals can be done directly using RTLIL::SigSpec
844 case AST_CONCAT: {
845 RTLIL::SigSpec sig;
846 sig.width = 0;
847 for (auto it = children.begin(); it != children.end(); it++) {
848 RTLIL::SigSpec s = (*it)->genRTLIL();
849 for (size_t i = 0; i < s.chunks.size(); i++) {
850 sig.chunks.push_back(s.chunks[i]);
851 sig.width += s.chunks[i].width;
852 }
853 }
854 return sig;
855 }
856
857 // replication of signals can be done directly using RTLIL::SigSpec
858 case AST_REPLICATE: {
859 RTLIL::SigSpec left = children[0]->genRTLIL();
860 RTLIL::SigSpec right = children[1]->genRTLIL();
861 if (!left.is_fully_const())
862 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
863 int count = left.as_int();
864 RTLIL::SigSpec sig;
865 for (int i = 0; i < count; i++)
866 sig.append(right);
867 is_signed = false;
868 return sig;
869 }
870
871 // generate cells for unary operations: $not, $pos, $neg
872 if (0) { case AST_BIT_NOT: type_name = "$not"; }
873 if (0) { case AST_POS: type_name = "$pos"; }
874 if (0) { case AST_NEG: type_name = "$neg"; }
875 {
876 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
877 is_signed = children[0]->is_signed;
878 int width = arg.width;
879 if (width_hint > 0) {
880 width = width_hint;
881 arg.extend(width, is_signed);
882 }
883 return uniop2rtlil(this, type_name, width, arg);
884 }
885
886 // generate cells for binary operations: $and, $or, $xor, $xnor
887 if (0) { case AST_BIT_AND: type_name = "$and"; }
888 if (0) { case AST_BIT_OR: type_name = "$or"; }
889 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
890 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
891 {
892 if (width_hint < 0)
893 detectSignWidth(width_hint, sign_hint);
894 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
895 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
896 int width = std::max(left.width, right.width);
897 if (width_hint > 0)
898 width = width_hint;
899 is_signed = children[0]->is_signed && children[1]->is_signed;
900 return binop2rtlil(this, type_name, width, left, right);
901 }
902
903 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
904 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
905 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
906 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
907 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
908 {
909 RTLIL::SigSpec arg = children[0]->genRTLIL();
910 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, 1, arg);
911 return sig;
912 }
913
914 // generate cells for unary operations: $reduce_bool
915 // (this is actually just an $reduce_or, but for clearity a different cell type is used)
916 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
917 {
918 RTLIL::SigSpec arg = children[0]->genRTLIL();
919 RTLIL::SigSpec sig = arg.width > 1 ? uniop2rtlil(this, type_name, 1, arg) : arg;
920 return sig;
921 }
922
923 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
924 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
925 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
926 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
927 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
928 {
929 if (width_hint < 0)
930 detectSignWidth(width_hint, sign_hint);
931 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
932 RTLIL::SigSpec right = children[1]->genRTLIL();
933 int width = width_hint > 0 ? width_hint : left.width;
934 is_signed = children[0]->is_signed;
935 return binop2rtlil(this, type_name, width, left, right);
936 }
937
938 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
939 if (0) { case AST_LT: type_name = "$lt"; }
940 if (0) { case AST_LE: type_name = "$le"; }
941 if (0) { case AST_EQ: type_name = "$eq"; }
942 if (0) { case AST_NE: type_name = "$ne"; }
943 if (0) { case AST_GE: type_name = "$ge"; }
944 if (0) { case AST_GT: type_name = "$gt"; }
945 {
946 width_hint = -1, sign_hint = true;
947 children[0]->detectSignWidthWorker(width_hint, sign_hint);
948 children[1]->detectSignWidthWorker(width_hint, sign_hint);
949 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
950 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
951 RTLIL::SigSpec sig = binop2rtlil(this, type_name, 1, left, right);
952 return sig;
953 }
954
955 // generate cells for binary operations: $add, $sub, $mul, $div, $mod, $pow
956 if (0) { case AST_ADD: type_name = "$add"; }
957 if (0) { case AST_SUB: type_name = "$sub"; }
958 if (0) { case AST_MUL: type_name = "$mul"; }
959 if (0) { case AST_DIV: type_name = "$div"; }
960 if (0) { case AST_MOD: type_name = "$mod"; }
961 if (0) { case AST_POW: type_name = "$pow"; }
962 {
963 if (width_hint < 0)
964 detectSignWidth(width_hint, sign_hint);
965 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
966 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
967 int width = std::max(left.width, right.width);
968 if (width > width_hint && width_hint > 0)
969 width = width_hint;
970 if (width < width_hint) {
971 if (type == AST_ADD || type == AST_SUB)
972 width++;
973 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
974 width = width_hint;
975 if (type == AST_MUL)
976 width = std::min(left.width + right.width, width_hint);
977 }
978 is_signed = children[0]->is_signed && children[1]->is_signed;
979 return binop2rtlil(this, type_name, width, left, right);
980 }
981
982 // generate cells for binary operations: $logic_and, $logic_or
983 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
984 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
985 {
986 RTLIL::SigSpec left = children[0]->genRTLIL();
987 RTLIL::SigSpec right = children[1]->genRTLIL();
988 return binop2rtlil(this, type_name, 1, left, right);
989 }
990
991 // generate cells for unary operations: $logic_not
992 case AST_LOGIC_NOT:
993 {
994 RTLIL::SigSpec arg = children[0]->genRTLIL();
995 return uniop2rtlil(this, "$logic_not", 1, arg);
996 }
997
998 // generate multiplexer for ternary operator (aka ?:-operator)
999 case AST_TERNARY:
1000 {
1001 RTLIL::SigSpec cond = children[0]->genRTLIL();
1002 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1003 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1004
1005 if (cond.width > 1)
1006 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1007
1008 int width = std::max(val1.width, val2.width);
1009 is_signed = children[1]->is_signed && children[2]->is_signed;
1010 val1.extend(width);
1011 val2.extend(width);
1012
1013 return mux2rtlil(this, cond, val1, val2);
1014 }
1015
1016 // generate $memrd cells for memory read ports
1017 case AST_MEMRD:
1018 {
1019 std::stringstream sstr;
1020 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
1021
1022 RTLIL::Cell *cell = new RTLIL::Cell;
1023 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1024 cell->name = sstr.str();
1025 cell->type = "$memrd";
1026 current_module->cells[cell->name] = cell;
1027
1028 RTLIL::Wire *wire = new RTLIL::Wire;
1029 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1030 wire->name = cell->name + "_DATA";
1031 wire->width = current_module->memories[str]->width;
1032 current_module->wires[wire->name] = wire;
1033
1034 int addr_bits = 1;
1035 while ((1 << addr_bits) < current_module->memories[str]->size)
1036 addr_bits++;
1037
1038 cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
1039 cell->connections["\\ADDR"] = children[0]->genRTLIL();
1040 cell->connections["\\DATA"] = RTLIL::SigSpec(wire);
1041
1042 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1043 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1044 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1045
1046 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1047 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1048
1049 return RTLIL::SigSpec(wire);
1050 }
1051
1052 // generate $memwr cells for memory write ports
1053 case AST_MEMWR:
1054 {
1055 std::stringstream sstr;
1056 sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
1057
1058 RTLIL::Cell *cell = new RTLIL::Cell;
1059 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1060 cell->name = sstr.str();
1061 cell->type = "$memwr";
1062 current_module->cells[cell->name] = cell;
1063
1064 int addr_bits = 1;
1065 while ((1 << addr_bits) < current_module->memories[str]->size)
1066 addr_bits++;
1067
1068 cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
1069 cell->connections["\\ADDR"] = children[0]->genRTLIL();
1070 cell->connections["\\DATA"] = children[1]->genRTLIL();
1071 cell->connections["\\EN"] = children[2]->genRTLIL();
1072
1073 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1074 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1075 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1076
1077 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1078 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1079 }
1080 break;
1081
1082 // add entries to current_module->connections for assignments (outside of always blocks)
1083 case AST_ASSIGN:
1084 {
1085 if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
1086 RTLIL::SigSpec right = children[1]->genRTLIL();
1087 RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.width);
1088 current_module->connections.push_back(RTLIL::SigSig(left, right));
1089 } else {
1090 RTLIL::SigSpec left = children[0]->genRTLIL();
1091 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.width);
1092 current_module->connections.push_back(RTLIL::SigSig(left, right));
1093 }
1094 }
1095 break;
1096
1097 // create an RTLIL::Cell for an AST_CELL
1098 case AST_CELL:
1099 {
1100 int port_counter = 0, para_counter = 0;
1101 RTLIL::Cell *cell = new RTLIL::Cell;
1102 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1103 cell->name = str;
1104 for (auto it = children.begin(); it != children.end(); it++) {
1105 AstNode *child = *it;
1106 if (child->type == AST_CELLTYPE) {
1107 cell->type = child->str;
1108 continue;
1109 }
1110 if (child->type == AST_PARASET) {
1111 if (child->children[0]->type != AST_CONSTANT)
1112 log_error("Parameter `%s' with non-constant value at %s:%d!\n",
1113 child->str.c_str(), filename.c_str(), linenum);
1114 if (child->str.size() == 0) {
1115 char buf[100];
1116 snprintf(buf, 100, "$%d", ++para_counter);
1117 cell->parameters[buf].str = child->children[0]->str;
1118 cell->parameters[buf].bits = child->children[0]->bits;
1119 } else {
1120 cell->parameters[child->str].str = child->children[0]->str;
1121 cell->parameters[child->str].bits = child->children[0]->bits;
1122 }
1123 continue;
1124 }
1125 if (child->type == AST_ARGUMENT) {
1126 RTLIL::SigSpec sig;
1127 if (child->children.size() > 0)
1128 sig = child->children[0]->genRTLIL();
1129 if (child->str.size() == 0) {
1130 char buf[100];
1131 snprintf(buf, 100, "$%d", ++port_counter);
1132 cell->connections[buf] = sig;
1133 } else {
1134 cell->connections[child->str] = sig;
1135 }
1136 continue;
1137 }
1138 assert(0);
1139 }
1140 for (auto &attr : attributes) {
1141 if (attr.second->type != AST_CONSTANT)
1142 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1143 attr.first.c_str(), filename.c_str(), linenum);
1144 cell->attributes[attr.first].str = attr.second->str;
1145 cell->attributes[attr.first].bits = attr.second->bits;
1146 }
1147 if (current_module->cells.count(cell->name) != 0)
1148 log_error("Re-definition of cell `%s' at %s:%d!\n",
1149 str.c_str(), filename.c_str(), linenum);
1150 current_module->cells[str] = cell;
1151 }
1152 break;
1153
1154 // use ProcessGenerator for always blocks
1155 case AST_ALWAYS: {
1156 AstNode *always = this->clone();
1157 ProcessGenerator generator(always);
1158 ignoreThisSignalsInInitial.append(generator.outputSignals);
1159 delete always;
1160 } break;
1161
1162 case AST_INITIAL: {
1163 AstNode *always = this->clone();
1164 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1165 delete always;
1166 } break;
1167
1168 // everything should have been handled above -> print error if not.
1169 default:
1170 for (auto f : log_files)
1171 current_ast->dumpAst(f, "verilog-ast> ");
1172 type_name = type2str(type);
1173 log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
1174 type_name.c_str(), filename.c_str(), linenum);
1175 }
1176
1177 return RTLIL::SigSpec();
1178 }
1179
1180 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1181 // signals must be substituted before beeing used as input values (used by ProcessGenerator)
1182 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1183 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RTLIL::SigSpec *subst_to)
1184 {
1185 RTLIL::SigSpec *backup_subst_from = genRTLIL_subst_from;
1186 RTLIL::SigSpec *backup_subst_to = genRTLIL_subst_to;
1187
1188 if (subst_from)
1189 genRTLIL_subst_from = subst_from;
1190 if (subst_to)
1191 genRTLIL_subst_to = subst_to;
1192
1193 bool sign_hint = true;
1194 int width_hint = width;
1195 detectSignWidthWorker(width_hint, sign_hint);
1196 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1197
1198 genRTLIL_subst_from = backup_subst_from;
1199 genRTLIL_subst_to = backup_subst_to;
1200
1201 if (width >= 0)
1202 sig.extend(width, is_signed);
1203
1204 return sig;
1205 }
1206