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Added $assert cell
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
31 #include "ast.h"
32
33 #include <sstream>
34 #include <stdarg.h>
35 #include <assert.h>
36 #include <algorithm>
37
38 using namespace AST;
39 using namespace AST_INTERNAL;
40
41 // helper function for creating RTLIL code for unary operations
42 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
43 {
44 std::stringstream sstr;
45 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
46
47 RTLIL::Cell *cell = new RTLIL::Cell;
48 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
49 cell->name = sstr.str();
50 cell->type = type;
51 current_module->cells[cell->name] = cell;
52
53 RTLIL::Wire *wire = new RTLIL::Wire;
54 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
55 wire->name = cell->name + "_Y";
56 wire->width = result_width;
57 current_module->wires[wire->name] = wire;
58
59 RTLIL::SigChunk chunk;
60 chunk.wire = wire;
61 chunk.width = wire->width;
62 chunk.offset = 0;
63
64 RTLIL::SigSpec sig;
65 sig.chunks.push_back(chunk);
66 sig.width = chunk.width;
67
68 if (gen_attributes)
69 for (auto &attr : that->attributes) {
70 if (attr.second->type != AST_CONSTANT)
71 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
72 attr.first.c_str(), that->filename.c_str(), that->linenum);
73 cell->attributes[attr.first] = attr.second->asAttrConst();
74 }
75
76 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
77 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.width);
78 cell->connections["\\A"] = arg;
79
80 cell->parameters["\\Y_WIDTH"] = result_width;
81 cell->connections["\\Y"] = sig;
82 return sig;
83 }
84
85 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
86 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
87 {
88 if (width <= sig.width) {
89 sig.extend(width, is_signed);
90 return;
91 }
92
93 std::stringstream sstr;
94 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
95
96 RTLIL::Cell *cell = new RTLIL::Cell;
97 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
98 cell->name = sstr.str();
99 cell->type = "$pos";
100 current_module->cells[cell->name] = cell;
101
102 RTLIL::Wire *wire = new RTLIL::Wire;
103 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
104 wire->name = cell->name + "_Y";
105 wire->width = width;
106 current_module->wires[wire->name] = wire;
107
108 RTLIL::SigChunk chunk;
109 chunk.wire = wire;
110 chunk.width = wire->width;
111 chunk.offset = 0;
112
113 RTLIL::SigSpec new_sig;
114 new_sig.chunks.push_back(chunk);
115 new_sig.width = chunk.width;
116
117 if (that != NULL)
118 for (auto &attr : that->attributes) {
119 if (attr.second->type != AST_CONSTANT)
120 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
121 attr.first.c_str(), that->filename.c_str(), that->linenum);
122 cell->attributes[attr.first] = attr.second->asAttrConst();
123 }
124
125 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
126 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.width);
127 cell->connections["\\A"] = sig;
128
129 cell->parameters["\\Y_WIDTH"] = width;
130 cell->connections["\\Y"] = new_sig;
131 sig = new_sig;
132 }
133
134 // helper function for creating RTLIL code for binary operations
135 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
136 {
137 std::stringstream sstr;
138 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
139
140 RTLIL::Cell *cell = new RTLIL::Cell;
141 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
142 cell->name = sstr.str();
143 cell->type = type;
144 current_module->cells[cell->name] = cell;
145
146 RTLIL::Wire *wire = new RTLIL::Wire;
147 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
148 wire->name = cell->name + "_Y";
149 wire->width = result_width;
150 current_module->wires[wire->name] = wire;
151
152 RTLIL::SigChunk chunk;
153 chunk.wire = wire;
154 chunk.width = wire->width;
155 chunk.offset = 0;
156
157 RTLIL::SigSpec sig;
158 sig.chunks.push_back(chunk);
159 sig.width = chunk.width;
160
161 for (auto &attr : that->attributes) {
162 if (attr.second->type != AST_CONSTANT)
163 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
164 attr.first.c_str(), that->filename.c_str(), that->linenum);
165 cell->attributes[attr.first] = attr.second->asAttrConst();
166 }
167
168 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
169 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
170
171 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.width);
172 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.width);
173
174 cell->connections["\\A"] = left;
175 cell->connections["\\B"] = right;
176
177 cell->parameters["\\Y_WIDTH"] = result_width;
178 cell->connections["\\Y"] = sig;
179 return sig;
180 }
181
182 // helper function for creating RTLIL code for multiplexers
183 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
184 {
185 assert(cond.width == 1);
186
187 std::stringstream sstr;
188 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
189
190 RTLIL::Cell *cell = new RTLIL::Cell;
191 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
192 cell->name = sstr.str();
193 cell->type = "$mux";
194 current_module->cells[cell->name] = cell;
195
196 RTLIL::Wire *wire = new RTLIL::Wire;
197 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
198 wire->name = cell->name + "_Y";
199 wire->width = left.width;
200 current_module->wires[wire->name] = wire;
201
202 RTLIL::SigChunk chunk;
203 chunk.wire = wire;
204 chunk.width = wire->width;
205 chunk.offset = 0;
206
207 RTLIL::SigSpec sig;
208 sig.chunks.push_back(chunk);
209 sig.width = chunk.width;
210
211 for (auto &attr : that->attributes) {
212 if (attr.second->type != AST_CONSTANT)
213 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
214 attr.first.c_str(), that->filename.c_str(), that->linenum);
215 cell->attributes[attr.first] = attr.second->asAttrConst();
216 }
217
218 cell->parameters["\\WIDTH"] = RTLIL::Const(left.width);
219
220 cell->connections["\\A"] = right;
221 cell->connections["\\B"] = left;
222 cell->connections["\\S"] = cond;
223 cell->connections["\\Y"] = sig;
224
225 return sig;
226 }
227
228 // helper class for converting AST always nodes to RTLIL processes
229 struct AST_INTERNAL::ProcessGenerator
230 {
231 // input and output structures
232 AstNode *always;
233 RTLIL::SigSpec initSyncSignals;
234 RTLIL::Process *proc;
235 const RTLIL::SigSpec &outputSignals;
236
237 // This always points to the RTLIL::CaseRule beeing filled at the moment
238 RTLIL::CaseRule *current_case;
239
240 // This two variables contain the replacement pattern to be used in the right hand side
241 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
242 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
243 // the value assigned in the first assignment. So when the first assignement is processed
244 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
245 RTLIL::SigSpec subst_rvalue_from, subst_rvalue_to;
246
247 // This two variables contain the replacement pattern to be used in the left hand side
248 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
249 // should not be connected to the signal foo. Instead it must be connected to the temporary
250 // signal that is used as input for the register that drives the signal foo.
251 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
252
253 // The code here generates a number of temprorary signal for each output register. This
254 // map helps generating nice numbered names for all this temporary signals.
255 std::map<RTLIL::Wire*, int> new_temp_count;
256
257 // Buffer for generating the init action
258 RTLIL::SigSpec init_lvalue, init_rvalue;
259
260 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg), outputSignals(subst_lvalue_from)
261 {
262 // generate process and simple root case
263 proc = new RTLIL::Process;
264 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
265 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, RTLIL::autoidx++);
266 for (auto &attr : always->attributes) {
267 if (attr.second->type != AST_CONSTANT)
268 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
269 attr.first.c_str(), always->filename.c_str(), always->linenum);
270 proc->attributes[attr.first] = attr.second->asAttrConst();
271 }
272 current_module->processes[proc->name] = proc;
273 current_case = &proc->root_case;
274
275 // create initial temporary signal for all output registers
276 collect_lvalues(subst_lvalue_from, always, true, true);
277 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
278
279 bool found_anyedge_syncs = false;
280 for (auto child : always->children)
281 if (child->type == AST_EDGE)
282 found_anyedge_syncs = true;
283
284 if (found_anyedge_syncs) {
285 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
286 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
287 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
288 }
289
290 // create syncs for the process
291 bool found_clocked_sync = false;
292 for (auto child : always->children)
293 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
294 found_clocked_sync = true;
295 if (found_anyedge_syncs)
296 log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
297 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
298 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
299 syncrule->signal = child->children[0]->genRTLIL();
300 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
301 proc->syncs.push_back(syncrule);
302 }
303 if (proc->syncs.empty()) {
304 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
305 syncrule->type = RTLIL::STa;
306 syncrule->signal = RTLIL::SigSpec();
307 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
308 proc->syncs.push_back(syncrule);
309 }
310
311 // create initial assignments for the temporary signals
312 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
313 subst_rvalue_from = subst_lvalue_from;
314 subst_rvalue_to = RTLIL::SigSpec(RTLIL::State::Sx, subst_rvalue_from.width);
315 } else {
316 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
317 }
318
319 // process the AST
320 for (auto child : always->children)
321 if (child->type == AST_BLOCK)
322 processAst(child);
323
324 if (initSyncSignals.width > 0)
325 {
326 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
327 sync->type = RTLIL::SyncType::STi;
328 proc->syncs.push_back(sync);
329
330 assert(init_lvalue.width == init_rvalue.width);
331 init_lvalue.optimize();
332 init_rvalue.optimize();
333
334 int offset = 0;
335 for (size_t i = 0; i < init_lvalue.chunks.size(); i++) {
336 RTLIL::SigSpec lhs = init_lvalue.chunks[i];
337 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue.chunks[i].width);
338 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
339 offset += lhs.width;
340 }
341 }
342 }
343
344 // create new temporary signals
345 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
346 {
347 sig.optimize();
348 for (size_t i = 0; i < sig.chunks.size(); i++)
349 {
350 RTLIL::SigChunk &chunk = sig.chunks[i];
351 if (chunk.wire == NULL)
352 continue;
353
354 RTLIL::Wire *wire = new RTLIL::Wire;
355 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
356 do {
357 wire->name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
358 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
359 if (chunk.wire->name.find('$') != std::string::npos)
360 wire->name += stringf("$%d", RTLIL::autoidx++);
361 } while (current_module->wires.count(wire->name) > 0);
362 wire->width = chunk.width;
363 current_module->wires[wire->name] = wire;
364
365 chunk.wire = wire;
366 chunk.offset = 0;
367 }
368 return sig;
369 }
370
371 // recursively traverse the AST an collect all assigned signals
372 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
373 {
374 switch (ast->type)
375 {
376 case AST_CASE:
377 for (auto child : ast->children)
378 if (child != ast->children[0]) {
379 assert(child->type == AST_COND);
380 collect_lvalues(reg, child, type_eq, type_le, false);
381 }
382 break;
383
384 case AST_COND:
385 case AST_ALWAYS:
386 case AST_INITIAL:
387 for (auto child : ast->children)
388 if (child->type == AST_BLOCK)
389 collect_lvalues(reg, child, type_eq, type_le, false);
390 break;
391
392 case AST_BLOCK:
393 for (auto child : ast->children) {
394 if (child->type == AST_ASSIGN_EQ && type_eq)
395 reg.append(child->children[0]->genRTLIL());
396 if (child->type == AST_ASSIGN_LE && type_le)
397 reg.append(child->children[0]->genRTLIL());
398 if (child->type == AST_CASE || child->type == AST_BLOCK)
399 collect_lvalues(reg, child, type_eq, type_le, false);
400 }
401 break;
402
403 default:
404 assert(0);
405 }
406
407 if (run_sort_and_unify)
408 reg.sort_and_unify();
409 }
410
411 // remove all assignments to the given signal pattern in a case and all its children.
412 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
413 // function is called to clean up the first two assignments as they are overwritten by
414 // the third assignment.
415 void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
416 {
417 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
418 it->first.remove2(pattern, &it->second);
419
420 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
421 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
422 removeSignalFromCaseTree(pattern, *it2);
423 }
424
425 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
426 // are avoided and the generated $mux cells have a more "natural" size.
427 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
428 {
429 if (inSyncRule && initSyncSignals.width > 0) {
430 init_lvalue.append(lvalue.extract(initSyncSignals));
431 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
432 lvalue.remove2(initSyncSignals, &rvalue);
433 }
434 assert(lvalue.width == rvalue.width);
435 lvalue.optimize();
436 rvalue.optimize();
437
438 int offset = 0;
439 for (size_t i = 0; i < lvalue.chunks.size(); i++) {
440 RTLIL::SigSpec lhs = lvalue.chunks[i];
441 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue.chunks[i].width);
442 if (inSyncRule && lvalue.chunks[i].wire && lvalue.chunks[i].wire->get_bool_attribute("\\nosync"))
443 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.width);
444 actions.push_back(RTLIL::SigSig(lhs, rhs));
445 offset += lhs.width;
446 }
447 }
448
449 // recursively process the AST and fill the RTLIL::Process
450 void processAst(AstNode *ast)
451 {
452 switch (ast->type)
453 {
454 case AST_BLOCK:
455 for (auto child : ast->children)
456 processAst(child);
457 break;
458
459 case AST_ASSIGN_EQ:
460 case AST_ASSIGN_LE:
461 {
462 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
463 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.width, &subst_rvalue_from, &subst_rvalue_to);
464 lvalue.replace(subst_lvalue_from, subst_lvalue_to);
465
466 if (ast->type == AST_ASSIGN_EQ) {
467 subst_rvalue_from.remove2(unmapped_lvalue, &subst_rvalue_to);
468 subst_rvalue_from.append(unmapped_lvalue);
469 subst_rvalue_from.optimize();
470 subst_rvalue_to.append(rvalue);
471 subst_rvalue_to.optimize();
472 }
473
474 removeSignalFromCaseTree(lvalue, current_case);
475 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
476 }
477 break;
478
479 case AST_CASE:
480 {
481 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
482 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_from, &subst_rvalue_to);
483 current_case->switches.push_back(sw);
484
485 for (auto &attr : ast->attributes) {
486 if (attr.second->type != AST_CONSTANT)
487 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
488 attr.first.c_str(), ast->filename.c_str(), ast->linenum);
489 sw->attributes[attr.first] = attr.second->asAttrConst();
490 }
491
492 RTLIL::SigSpec this_case_eq_lvalue;
493 collect_lvalues(this_case_eq_lvalue, ast, true, false);
494
495 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
496
497 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
498 this_case_eq_rvalue.replace(subst_rvalue_from, subst_rvalue_to);
499
500 RTLIL::SigSpec backup_subst_lvalue_from = subst_lvalue_from;
501 RTLIL::SigSpec backup_subst_lvalue_to = subst_lvalue_to;
502
503 RTLIL::SigSpec backup_subst_rvalue_from = subst_rvalue_from;
504 RTLIL::SigSpec backup_subst_rvalue_to = subst_rvalue_to;
505
506 RTLIL::CaseRule *default_case = NULL;
507 RTLIL::CaseRule *last_generated_case = NULL;
508 for (auto child : ast->children)
509 {
510 if (child == ast->children[0])
511 continue;
512 assert(child->type == AST_COND);
513
514 subst_lvalue_from = backup_subst_lvalue_from;
515 subst_lvalue_to = backup_subst_lvalue_to;
516
517 subst_rvalue_from = backup_subst_rvalue_from;
518 subst_rvalue_to = backup_subst_rvalue_to;
519
520 subst_lvalue_from.remove2(this_case_eq_lvalue, &subst_lvalue_to);
521 subst_lvalue_from.append(this_case_eq_lvalue);
522 subst_lvalue_from.optimize();
523 subst_lvalue_to.append(this_case_eq_ltemp);
524 subst_lvalue_to.optimize();
525
526 RTLIL::CaseRule *backup_case = current_case;
527 current_case = new RTLIL::CaseRule;
528 last_generated_case = current_case;
529 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
530 for (auto node : child->children) {
531 if (node->type == AST_DEFAULT)
532 default_case = current_case;
533 else if (node->type == AST_BLOCK)
534 processAst(node);
535 else
536 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.width, &subst_rvalue_from, &subst_rvalue_to));
537 }
538 if (default_case != current_case)
539 sw->cases.push_back(current_case);
540 else
541 log_assert(current_case->compare.size() == 0);
542 current_case = backup_case;
543 }
544
545 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
546 last_generated_case->compare.clear();
547 } else {
548 if (default_case == NULL) {
549 default_case = new RTLIL::CaseRule;
550 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
551 }
552 sw->cases.push_back(default_case);
553 }
554
555 subst_lvalue_from = backup_subst_lvalue_from;
556 subst_lvalue_to = backup_subst_lvalue_to;
557
558 subst_rvalue_from = backup_subst_rvalue_from;
559 subst_rvalue_to = backup_subst_rvalue_to;
560
561 subst_rvalue_from.remove2(this_case_eq_lvalue, &subst_rvalue_to);
562 subst_rvalue_from.append(this_case_eq_lvalue);
563 subst_rvalue_from.optimize();
564 subst_rvalue_to.append(this_case_eq_ltemp);
565 subst_rvalue_to.optimize();
566
567 this_case_eq_lvalue.replace(subst_lvalue_from, subst_lvalue_to);
568 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
569 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
570 }
571 break;
572
573 case AST_WIRE:
574 log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
575 break;
576
577 case AST_TCALL:
578 case AST_FOR:
579 break;
580
581 default:
582 assert(0);
583 }
584 }
585 };
586
587 // detect sign and width of an expression
588 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint)
589 {
590 std::string type_name;
591 bool sub_sign_hint = true;
592 int sub_width_hint = -1;
593 int this_width = 0;
594 AstNode *range = NULL;
595 AstNode *id_ast = NULL;
596
597 switch (type)
598 {
599 case AST_CONSTANT:
600 width_hint = std::max(width_hint, int(bits.size()));
601 if (!is_signed)
602 sign_hint = false;
603 break;
604
605 case AST_IDENTIFIER:
606 id_ast = id2ast;
607 if (id_ast == NULL && current_scope.count(str))
608 id_ast = current_scope.at(str);
609 if (!id_ast)
610 log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
611 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
612 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
613 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
614 } else
615 if (id_ast->children[0]->type == AST_CONSTANT) {
616 this_width = id_ast->children[0]->bits.size();
617 } else
618 log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
619 if (children.size() != 0)
620 range = children[0];
621 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
622 if (!id_ast->range_valid) {
623 if (id_ast->type == AST_AUTOWIRE)
624 this_width = 1;
625 else {
626 // current_ast_mod->dumpAst(stdout, "");
627 // printf("---\n");
628 // dumpAst(stdout, "");
629 // fflush(stdout);
630 log_error("Failed to detect with of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
631 }
632 } else {
633 this_width = id_ast->range_left - id_ast->range_right + 1;
634 if (children.size() != 0)
635 range = children[0];
636 }
637 } else if (id_ast->type == AST_GENVAR) {
638 this_width = 32;
639 } else if (id_ast->type == AST_MEMORY) {
640 if (!id_ast->children[0]->range_valid)
641 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
642 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
643 } else
644 log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
645 if (range) {
646 if (range->children.size() == 1)
647 this_width = 1;
648 else if (!range->range_valid) {
649 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
650 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
651 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false)) { }
652 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false)) { }
653 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
654 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
655 str.c_str(), filename.c_str(), linenum);
656 this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
657 delete left_at_zero_ast;
658 delete right_at_zero_ast;
659 } else
660 this_width = range->range_left - range->range_right + 1;
661 } else
662 width_hint = std::max(width_hint, this_width);
663 if (!id_ast->is_signed)
664 sign_hint = false;
665 break;
666
667 case AST_TO_SIGNED:
668 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
669 break;
670
671 case AST_TO_UNSIGNED:
672 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
673 sign_hint = false;
674 break;
675
676 case AST_CONCAT:
677 for (auto child : children) {
678 sub_width_hint = 0;
679 sub_sign_hint = true;
680 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
681 this_width += sub_width_hint;
682 }
683 width_hint = std::max(width_hint, this_width);
684 sign_hint = false;
685 break;
686
687 case AST_REPLICATE:
688 while (children[0]->simplify(true, false, false, 1, -1, false) == true) { }
689 if (children[0]->type != AST_CONSTANT)
690 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
691 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
692 width_hint = std::max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
693 sign_hint = false;
694 break;
695
696 case AST_NEG:
697 case AST_BIT_NOT:
698 case AST_POS:
699 children[0]->detectSignWidthWorker(width_hint, sign_hint);
700 break;
701
702 case AST_BIT_AND:
703 case AST_BIT_OR:
704 case AST_BIT_XOR:
705 case AST_BIT_XNOR:
706 for (auto child : children)
707 child->detectSignWidthWorker(width_hint, sign_hint);
708 break;
709
710 case AST_REDUCE_AND:
711 case AST_REDUCE_OR:
712 case AST_REDUCE_XOR:
713 case AST_REDUCE_XNOR:
714 case AST_REDUCE_BOOL:
715 width_hint = std::max(width_hint, 1);
716 sign_hint = false;
717 break;
718
719 case AST_SHIFT_LEFT:
720 case AST_SHIFT_RIGHT:
721 case AST_SHIFT_SLEFT:
722 case AST_SHIFT_SRIGHT:
723 case AST_POW:
724 children[0]->detectSignWidthWorker(width_hint, sign_hint);
725 break;
726
727 case AST_LT:
728 case AST_LE:
729 case AST_EQ:
730 case AST_NE:
731 case AST_EQX:
732 case AST_NEX:
733 case AST_GE:
734 case AST_GT:
735 width_hint = std::max(width_hint, 1);
736 sign_hint = false;
737 break;
738
739 case AST_ADD:
740 case AST_SUB:
741 case AST_MUL:
742 case AST_DIV:
743 case AST_MOD:
744 for (auto child : children)
745 child->detectSignWidthWorker(width_hint, sign_hint);
746 break;
747
748 case AST_LOGIC_AND:
749 case AST_LOGIC_OR:
750 case AST_LOGIC_NOT:
751 width_hint = std::max(width_hint, 1);
752 sign_hint = false;
753 break;
754
755 case AST_TERNARY:
756 children.at(1)->detectSignWidthWorker(width_hint, sign_hint);
757 children.at(2)->detectSignWidthWorker(width_hint, sign_hint);
758 break;
759
760 case AST_MEMRD:
761 if (!id2ast->is_signed)
762 sign_hint = false;
763 if (!id2ast->children[0]->range_valid)
764 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
765 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
766 width_hint = std::max(width_hint, this_width);
767 break;
768
769 // everything should have been handled above -> print error if not.
770 default:
771 for (auto f : log_files)
772 current_ast->dumpAst(f, "verilog-ast> ");
773 log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
774 type2str(type).c_str(), filename.c_str(), linenum);
775 }
776 }
777
778 // detect sign and width of an expression
779 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint)
780 {
781 width_hint = -1, sign_hint = true;
782 detectSignWidthWorker(width_hint, sign_hint);
783 }
784
785 // create RTLIL from an AST node
786 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
787 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
788 //
789 // note that this function is influenced by a number of global variables that might be set when
790 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
791 // larger expressions into a netlist of cells.
792 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
793 {
794 // in the following big switch() statement there are some uses of
795 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
796 // cases this variable is used to hold the type of the cell that should
797 // be instanciated for this type of AST node.
798 std::string type_name;
799
800 current_filename = filename;
801 set_line_num(linenum);
802
803 switch (type)
804 {
805 // simply ignore this nodes.
806 // they are eighter leftovers from simplify() or are referenced by other nodes
807 // and are only accessed here thru this references
808 case AST_TASK:
809 case AST_FUNCTION:
810 case AST_AUTOWIRE:
811 case AST_LOCALPARAM:
812 case AST_DEFPARAM:
813 case AST_GENVAR:
814 case AST_GENFOR:
815 case AST_GENBLOCK:
816 case AST_GENIF:
817 case AST_GENCASE:
818 break;
819
820 // remember the parameter, needed for example in techmap
821 case AST_PARAMETER:
822 current_module->avail_parameters.insert(str);
823 break;
824
825 // create an RTLIL::Wire for an AST_WIRE node
826 case AST_WIRE: {
827 if (current_module->wires.count(str) != 0)
828 log_error("Re-definition of signal `%s' at %s:%d!\n",
829 str.c_str(), filename.c_str(), linenum);
830 if (!range_valid)
831 log_error("Signal `%s' with non-constant width at %s:%d!\n",
832 str.c_str(), filename.c_str(), linenum);
833
834 if (range_left < range_right && (range_left != -1 || range_right != 0)) {
835 int tmp = range_left;
836 range_left = range_right;
837 range_right = tmp;
838 }
839
840 RTLIL::Wire *wire = new RTLIL::Wire;
841 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
842 wire->name = str;
843 wire->width = range_left - range_right + 1;
844 wire->start_offset = range_right;
845 wire->port_id = port_id;
846 wire->port_input = is_input;
847 wire->port_output = is_output;
848 current_module->wires[wire->name] = wire;
849
850 for (auto &attr : attributes) {
851 if (attr.second->type != AST_CONSTANT)
852 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
853 attr.first.c_str(), filename.c_str(), linenum);
854 wire->attributes[attr.first] = attr.second->asAttrConst();
855 }
856 }
857 break;
858
859 // create an RTLIL::Memory for an AST_MEMORY node
860 case AST_MEMORY: {
861 if (current_module->memories.count(str) != 0)
862 log_error("Re-definition of memory `%s' at %s:%d!\n",
863 str.c_str(), filename.c_str(), linenum);
864
865 assert(children.size() >= 2);
866 assert(children[0]->type == AST_RANGE);
867 assert(children[1]->type == AST_RANGE);
868
869 if (!children[0]->range_valid || !children[1]->range_valid)
870 log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
871 str.c_str(), filename.c_str(), linenum);
872
873 RTLIL::Memory *memory = new RTLIL::Memory;
874 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
875 memory->name = str;
876 memory->width = children[0]->range_left - children[0]->range_right + 1;
877 memory->start_offset = children[0]->range_right;
878 memory->size = children[1]->range_left - children[1]->range_right;
879 current_module->memories[memory->name] = memory;
880
881 if (memory->size < 0)
882 memory->size *= -1;
883 memory->size += std::min(children[1]->range_left, children[1]->range_right) + 1;
884
885 for (auto &attr : attributes) {
886 if (attr.second->type != AST_CONSTANT)
887 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
888 attr.first.c_str(), filename.c_str(), linenum);
889 memory->attributes[attr.first] = attr.second->asAttrConst();
890 }
891 }
892 break;
893
894 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
895 case AST_CONSTANT:
896 {
897 if (width_hint < 0)
898 detectSignWidth(width_hint, sign_hint);
899
900 RTLIL::SigChunk chunk;
901 chunk.wire = NULL;
902 chunk.data.bits = bits;
903 chunk.width = bits.size();
904 chunk.offset = 0;
905
906 RTLIL::SigSpec sig;
907 sig.chunks.push_back(chunk);
908 sig.width = chunk.width;
909
910 is_signed = sign_hint;
911 return sig;
912 }
913
914 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
915 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
916 // shifter cell is created and the output signal of this cell is returned
917 case AST_IDENTIFIER:
918 {
919 RTLIL::Wire *wire = NULL;
920 RTLIL::SigChunk chunk;
921
922 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires.count(str) == 0) {
923 RTLIL::Wire *wire = new RTLIL::Wire;
924 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
925 wire->name = str;
926 log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
927 current_module->wires[str] = wire;
928 }
929 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
930 if (id2ast->children[0]->type != AST_CONSTANT)
931 log_error("Parameter %s does not evaluate to constant value at %s:%d!\n",
932 str.c_str(), filename.c_str(), linenum);
933 chunk = RTLIL::Const(id2ast->children[0]->bits);
934 goto use_const_chunk;
935 }
936 else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
937 id2ast->type != AST_MEMORY) || current_module->wires.count(str) == 0)
938 log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
939 str.c_str(), filename.c_str(), linenum);
940
941 if (id2ast->type == AST_MEMORY)
942 log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
943 str.c_str(), filename.c_str(), linenum);
944
945 wire = current_module->wires[str];
946 chunk.wire = wire;
947 chunk.width = wire->width;
948 chunk.offset = 0;
949
950 use_const_chunk:
951 if (children.size() != 0) {
952 assert(children[0]->type == AST_RANGE);
953 if (!children[0]->range_valid) {
954 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
955 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
956 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false)) { }
957 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false)) { }
958 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
959 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
960 str.c_str(), filename.c_str(), linenum);
961 int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
962 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
963 children[0]->children[1]->clone() : children[0]->children[0]->clone());
964 fake_ast->children[0]->delete_children();
965 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width,
966 fake_ast->children[0]->genRTLIL(), fake_ast->children[1]->genRTLIL());
967 delete left_at_zero_ast;
968 delete right_at_zero_ast;
969 delete fake_ast;
970 return sig;
971 } else {
972 chunk.offset = children[0]->range_right - id2ast->range_right;
973 chunk.width = children[0]->range_left - children[0]->range_right + 1;
974 if (children[0]->range_left > id2ast->range_left || id2ast->range_right > children[0]->range_right)
975 log_error("Range select out of bounds on signal `%s' at %s:%d!\n",
976 str.c_str(), filename.c_str(), linenum);
977 }
978 }
979
980 RTLIL::SigSpec sig;
981 sig.chunks.push_back(chunk);
982 sig.width = chunk.width;
983
984 if (genRTLIL_subst_from && genRTLIL_subst_to)
985 sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
986
987 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
988 return sig;
989 }
990
991 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
992 case AST_TO_SIGNED:
993 case AST_TO_UNSIGNED: {
994 RTLIL::SigSpec sig = children[0]->genRTLIL();
995 if (sig.width < width_hint)
996 sig.extend_u0(width_hint, sign_hint);
997 is_signed = sign_hint;
998 return sig;
999 }
1000
1001 // concatenation of signals can be done directly using RTLIL::SigSpec
1002 case AST_CONCAT: {
1003 RTLIL::SigSpec sig;
1004 sig.width = 0;
1005 for (auto it = children.begin(); it != children.end(); it++) {
1006 RTLIL::SigSpec s = (*it)->genRTLIL();
1007 for (size_t i = 0; i < s.chunks.size(); i++) {
1008 sig.chunks.push_back(s.chunks[i]);
1009 sig.width += s.chunks[i].width;
1010 }
1011 }
1012 if (sig.width < width_hint)
1013 sig.extend_u0(width_hint, false);
1014 return sig;
1015 }
1016
1017 // replication of signals can be done directly using RTLIL::SigSpec
1018 case AST_REPLICATE: {
1019 RTLIL::SigSpec left = children[0]->genRTLIL();
1020 RTLIL::SigSpec right = children[1]->genRTLIL();
1021 if (!left.is_fully_const())
1022 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
1023 int count = left.as_int();
1024 RTLIL::SigSpec sig;
1025 for (int i = 0; i < count; i++)
1026 sig.append(right);
1027 if (sig.width < width_hint)
1028 sig.extend_u0(width_hint, false);
1029 is_signed = false;
1030 return sig;
1031 }
1032
1033 // generate cells for unary operations: $not, $pos, $neg
1034 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1035 if (0) { case AST_POS: type_name = "$pos"; }
1036 if (0) { case AST_NEG: type_name = "$neg"; }
1037 {
1038 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1039 is_signed = children[0]->is_signed;
1040 int width = arg.width;
1041 if (width_hint > 0) {
1042 width = width_hint;
1043 widthExtend(this, arg, width, is_signed);
1044 }
1045 return uniop2rtlil(this, type_name, width, arg);
1046 }
1047
1048 // generate cells for binary operations: $and, $or, $xor, $xnor
1049 if (0) { case AST_BIT_AND: type_name = "$and"; }
1050 if (0) { case AST_BIT_OR: type_name = "$or"; }
1051 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1052 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1053 {
1054 if (width_hint < 0)
1055 detectSignWidth(width_hint, sign_hint);
1056 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1057 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1058 int width = std::max(left.width, right.width);
1059 if (width_hint > 0)
1060 width = width_hint;
1061 is_signed = children[0]->is_signed && children[1]->is_signed;
1062 return binop2rtlil(this, type_name, width, left, right);
1063 }
1064
1065 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1066 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1067 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1068 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1069 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1070 {
1071 RTLIL::SigSpec arg = children[0]->genRTLIL();
1072 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, std::max(width_hint, 1), arg);
1073 return sig;
1074 }
1075
1076 // generate cells for unary operations: $reduce_bool
1077 // (this is actually just an $reduce_or, but for clearity a different cell type is used)
1078 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1079 {
1080 RTLIL::SigSpec arg = children[0]->genRTLIL();
1081 RTLIL::SigSpec sig = arg.width > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
1082 return sig;
1083 }
1084
1085 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1086 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1087 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1088 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1089 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1090 {
1091 if (width_hint < 0)
1092 detectSignWidth(width_hint, sign_hint);
1093 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1094 RTLIL::SigSpec right = children[1]->genRTLIL();
1095 int width = width_hint > 0 ? width_hint : left.width;
1096 is_signed = children[0]->is_signed;
1097 return binop2rtlil(this, type_name, width, left, right);
1098 }
1099
1100 // generate cells for binary operations: $pow
1101 case AST_POW:
1102 {
1103 int right_width;
1104 bool right_signed;
1105 children[1]->detectSignWidth(right_width, right_signed);
1106 if (width_hint < 0)
1107 detectSignWidth(width_hint, sign_hint);
1108 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1109 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1110 int width = width_hint > 0 ? width_hint : left.width;
1111 is_signed = children[0]->is_signed;
1112 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1113 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.width), right);
1114 return binop2rtlil(this, "$pow", width, left, right);
1115 }
1116
1117 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1118 if (0) { case AST_LT: type_name = "$lt"; }
1119 if (0) { case AST_LE: type_name = "$le"; }
1120 if (0) { case AST_EQ: type_name = "$eq"; }
1121 if (0) { case AST_NE: type_name = "$ne"; }
1122 if (0) { case AST_EQX: type_name = "$eqx"; }
1123 if (0) { case AST_NEX: type_name = "$nex"; }
1124 if (0) { case AST_GE: type_name = "$ge"; }
1125 if (0) { case AST_GT: type_name = "$gt"; }
1126 {
1127 int width = std::max(width_hint, 1);
1128 width_hint = -1, sign_hint = true;
1129 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1130 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1131 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1132 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1133 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1134 return sig;
1135 }
1136
1137 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1138 if (0) { case AST_ADD: type_name = "$add"; }
1139 if (0) { case AST_SUB: type_name = "$sub"; }
1140 if (0) { case AST_MUL: type_name = "$mul"; }
1141 if (0) { case AST_DIV: type_name = "$div"; }
1142 if (0) { case AST_MOD: type_name = "$mod"; }
1143 {
1144 if (width_hint < 0)
1145 detectSignWidth(width_hint, sign_hint);
1146 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1147 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1148 #if 0
1149 int width = std::max(left.width, right.width);
1150 if (width > width_hint && width_hint > 0)
1151 width = width_hint;
1152 if (width < width_hint) {
1153 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1154 width++;
1155 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1156 width = width_hint;
1157 if (type == AST_MUL)
1158 width = std::min(left.width + right.width, width_hint);
1159 }
1160 #else
1161 int width = std::max(std::max(left.width, right.width), width_hint);
1162 #endif
1163 is_signed = children[0]->is_signed && children[1]->is_signed;
1164 return binop2rtlil(this, type_name, width, left, right);
1165 }
1166
1167 // generate cells for binary operations: $logic_and, $logic_or
1168 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1169 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1170 {
1171 RTLIL::SigSpec left = children[0]->genRTLIL();
1172 RTLIL::SigSpec right = children[1]->genRTLIL();
1173 return binop2rtlil(this, type_name, std::max(width_hint, 1), left, right);
1174 }
1175
1176 // generate cells for unary operations: $logic_not
1177 case AST_LOGIC_NOT:
1178 {
1179 RTLIL::SigSpec arg = children[0]->genRTLIL();
1180 return uniop2rtlil(this, "$logic_not", std::max(width_hint, 1), arg);
1181 }
1182
1183 // generate multiplexer for ternary operator (aka ?:-operator)
1184 case AST_TERNARY:
1185 {
1186 if (width_hint < 0)
1187 detectSignWidth(width_hint, sign_hint);
1188
1189 RTLIL::SigSpec cond = children[0]->genRTLIL();
1190 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1191 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1192
1193 if (cond.width > 1)
1194 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1195
1196 int width = std::max(val1.width, val2.width);
1197 is_signed = children[1]->is_signed && children[2]->is_signed;
1198 widthExtend(this, val1, width, is_signed);
1199 widthExtend(this, val2, width, is_signed);
1200
1201 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1202
1203 if (sig.width < width_hint)
1204 sig.extend_u0(width_hint, sign_hint);
1205 return sig;
1206 }
1207
1208 // generate $memrd cells for memory read ports
1209 case AST_MEMRD:
1210 {
1211 std::stringstream sstr;
1212 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
1213
1214 RTLIL::Cell *cell = new RTLIL::Cell;
1215 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1216 cell->name = sstr.str();
1217 cell->type = "$memrd";
1218 current_module->cells[cell->name] = cell;
1219
1220 RTLIL::Wire *wire = new RTLIL::Wire;
1221 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1222 wire->name = cell->name + "_DATA";
1223 wire->width = current_module->memories[str]->width;
1224 current_module->wires[wire->name] = wire;
1225
1226 int addr_bits = 1;
1227 while ((1 << addr_bits) < current_module->memories[str]->size)
1228 addr_bits++;
1229
1230 cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
1231 cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
1232 cell->connections["\\DATA"] = RTLIL::SigSpec(wire);
1233
1234 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1235 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1236 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1237
1238 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1239 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1240
1241 return RTLIL::SigSpec(wire);
1242 }
1243
1244 // generate $memwr cells for memory write ports
1245 case AST_MEMWR:
1246 {
1247 std::stringstream sstr;
1248 sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
1249
1250 RTLIL::Cell *cell = new RTLIL::Cell;
1251 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1252 cell->name = sstr.str();
1253 cell->type = "$memwr";
1254 current_module->cells[cell->name] = cell;
1255
1256 int addr_bits = 1;
1257 while ((1 << addr_bits) < current_module->memories[str]->size)
1258 addr_bits++;
1259
1260 cell->connections["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx, 1);
1261 cell->connections["\\ADDR"] = children[0]->genWidthRTLIL(addr_bits);
1262 cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
1263 cell->connections["\\EN"] = children[2]->genRTLIL();
1264
1265 if (cell->connections["\\EN"].width > 1)
1266 cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
1267
1268 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1269 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1270 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1271
1272 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1273 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1274
1275 cell->parameters["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx-1);
1276 }
1277 break;
1278
1279 // generate $assert cells
1280 case AST_ASSERT:
1281 {
1282 log_assert(children.size() == 2);
1283
1284 RTLIL::SigSpec check = children[0]->genRTLIL();
1285 log_assert(check.width == 1);
1286
1287 RTLIL::SigSpec en = children[1]->genRTLIL();
1288 log_assert(en.width == 1);
1289
1290 std::stringstream sstr;
1291 sstr << "$assert$" << filename << ":" << linenum << "$" << (RTLIL::autoidx++);
1292
1293 RTLIL::Cell *cell = new RTLIL::Cell;
1294 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1295 cell->name = sstr.str();
1296 cell->type = "$assert";
1297 current_module->cells[cell->name] = cell;
1298
1299 for (auto &attr : attributes) {
1300 if (attr.second->type != AST_CONSTANT)
1301 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1302 attr.first.c_str(), filename.c_str(), linenum);
1303 cell->attributes[attr.first] = attr.second->asAttrConst();
1304 }
1305
1306 cell->connections["\\A"] = check;
1307 cell->connections["\\EN"] = en;
1308 }
1309 break;
1310
1311 // add entries to current_module->connections for assignments (outside of always blocks)
1312 case AST_ASSIGN:
1313 {
1314 if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
1315 RTLIL::SigSpec right = children[1]->genRTLIL();
1316 RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.width);
1317 current_module->connections.push_back(RTLIL::SigSig(left, right));
1318 } else {
1319 RTLIL::SigSpec left = children[0]->genRTLIL();
1320 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.width);
1321 current_module->connections.push_back(RTLIL::SigSig(left, right));
1322 }
1323 }
1324 break;
1325
1326 // create an RTLIL::Cell for an AST_CELL
1327 case AST_CELL:
1328 {
1329 int port_counter = 0, para_counter = 0;
1330 RTLIL::Cell *cell = new RTLIL::Cell;
1331 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1332 cell->name = str;
1333 for (auto it = children.begin(); it != children.end(); it++) {
1334 AstNode *child = *it;
1335 if (child->type == AST_CELLTYPE) {
1336 cell->type = child->str;
1337 continue;
1338 }
1339 if (child->type == AST_PARASET) {
1340 if (child->children[0]->type != AST_CONSTANT)
1341 log_error("Parameter `%s' with non-constant value at %s:%d!\n",
1342 child->str.c_str(), filename.c_str(), linenum);
1343 if (child->str.size() == 0) {
1344 char buf[100];
1345 snprintf(buf, 100, "$%d", ++para_counter);
1346 cell->parameters[buf] = child->children[0]->asParaConst();
1347 } else {
1348 cell->parameters[child->str] = child->children[0]->asParaConst();
1349 }
1350 continue;
1351 }
1352 if (child->type == AST_ARGUMENT) {
1353 RTLIL::SigSpec sig;
1354 if (child->children.size() > 0)
1355 sig = child->children[0]->genRTLIL();
1356 if (child->str.size() == 0) {
1357 char buf[100];
1358 snprintf(buf, 100, "$%d", ++port_counter);
1359 cell->connections[buf] = sig;
1360 } else {
1361 cell->connections[child->str] = sig;
1362 }
1363 continue;
1364 }
1365 assert(0);
1366 }
1367 for (auto &attr : attributes) {
1368 if (attr.second->type != AST_CONSTANT)
1369 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1370 attr.first.c_str(), filename.c_str(), linenum);
1371 cell->attributes[attr.first] = attr.second->asAttrConst();
1372 }
1373 if (current_module->cells.count(cell->name) != 0)
1374 log_error("Re-definition of cell `%s' at %s:%d!\n",
1375 str.c_str(), filename.c_str(), linenum);
1376 current_module->cells[str] = cell;
1377 }
1378 break;
1379
1380 // use ProcessGenerator for always blocks
1381 case AST_ALWAYS: {
1382 AstNode *always = this->clone();
1383 ProcessGenerator generator(always);
1384 ignoreThisSignalsInInitial.append(generator.outputSignals);
1385 delete always;
1386 } break;
1387
1388 case AST_INITIAL: {
1389 AstNode *always = this->clone();
1390 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1391 delete always;
1392 } break;
1393
1394 // everything should have been handled above -> print error if not.
1395 default:
1396 for (auto f : log_files)
1397 current_ast->dumpAst(f, "verilog-ast> ");
1398 type_name = type2str(type);
1399 log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
1400 type_name.c_str(), filename.c_str(), linenum);
1401 }
1402
1403 return RTLIL::SigSpec();
1404 }
1405
1406 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1407 // signals must be substituted before beeing used as input values (used by ProcessGenerator)
1408 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1409 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, RTLIL::SigSpec *subst_from, RTLIL::SigSpec *subst_to)
1410 {
1411 RTLIL::SigSpec *backup_subst_from = genRTLIL_subst_from;
1412 RTLIL::SigSpec *backup_subst_to = genRTLIL_subst_to;
1413
1414 if (subst_from)
1415 genRTLIL_subst_from = subst_from;
1416 if (subst_to)
1417 genRTLIL_subst_to = subst_to;
1418
1419 bool sign_hint = true;
1420 int width_hint = width;
1421 detectSignWidthWorker(width_hint, sign_hint);
1422 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1423
1424 genRTLIL_subst_from = backup_subst_from;
1425 genRTLIL_subst_to = backup_subst_to;
1426
1427 if (width >= 0)
1428 sig.extend_u0(width, is_signed);
1429
1430 return sig;
1431 }
1432