2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
38 using namespace AST_INTERNAL
;
40 // helper function for creating RTLIL code for unary operations
41 static RTLIL::SigSpec
uniop2rtlil(AstNode
*that
, std::string type
, int result_width
, const RTLIL::SigSpec
&arg
, bool gen_attributes
= true)
43 std::stringstream sstr
;
44 sstr
<< type
<< "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
46 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), type
);
47 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
49 RTLIL::Wire
*wire
= current_module
->addWire(cell
->name
+ "_Y", result_width
);
50 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
53 for (auto &attr
: that
->attributes
) {
54 if (attr
.second
->type
!= AST_CONSTANT
)
55 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
56 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
57 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
60 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(that
->children
[0]->is_signed
);
61 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(arg
.size());
62 cell
->set("\\A", arg
);
64 cell
->parameters
["\\Y_WIDTH"] = result_width
;
65 cell
->set("\\Y", wire
);
69 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
70 static void widthExtend(AstNode
*that
, RTLIL::SigSpec
&sig
, int width
, bool is_signed
, std::string celltype
)
72 if (width
<= sig
.size()) {
73 sig
.extend(width
, is_signed
);
77 std::stringstream sstr
;
78 sstr
<< "$extend" << "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
80 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), celltype
);
81 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
83 RTLIL::Wire
*wire
= current_module
->addWire(cell
->name
+ "_Y", width
);
84 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
87 for (auto &attr
: that
->attributes
) {
88 if (attr
.second
->type
!= AST_CONSTANT
)
89 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
90 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
91 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
94 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(is_signed
);
95 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(sig
.size());
96 cell
->set("\\A", sig
);
98 cell
->parameters
["\\Y_WIDTH"] = width
;
99 cell
->set("\\Y", wire
);
103 // helper function for creating RTLIL code for binary operations
104 static RTLIL::SigSpec
binop2rtlil(AstNode
*that
, std::string type
, int result_width
, const RTLIL::SigSpec
&left
, const RTLIL::SigSpec
&right
)
106 std::stringstream sstr
;
107 sstr
<< type
<< "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
109 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), type
);
110 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
112 RTLIL::Wire
*wire
= current_module
->addWire(cell
->name
+ "_Y", result_width
);
113 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
115 for (auto &attr
: that
->attributes
) {
116 if (attr
.second
->type
!= AST_CONSTANT
)
117 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
118 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
119 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
122 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(that
->children
[0]->is_signed
);
123 cell
->parameters
["\\B_SIGNED"] = RTLIL::Const(that
->children
[1]->is_signed
);
125 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(left
.size());
126 cell
->parameters
["\\B_WIDTH"] = RTLIL::Const(right
.size());
128 cell
->set("\\A", left
);
129 cell
->set("\\B", right
);
131 cell
->parameters
["\\Y_WIDTH"] = result_width
;
132 cell
->set("\\Y", wire
);
136 // helper function for creating RTLIL code for multiplexers
137 static RTLIL::SigSpec
mux2rtlil(AstNode
*that
, const RTLIL::SigSpec
&cond
, const RTLIL::SigSpec
&left
, const RTLIL::SigSpec
&right
)
139 log_assert(cond
.size() == 1);
141 std::stringstream sstr
;
142 sstr
<< "$ternary$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
144 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), "$mux");
145 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
147 RTLIL::Wire
*wire
= current_module
->addWire(cell
->name
+ "_Y", left
.size());
148 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
150 for (auto &attr
: that
->attributes
) {
151 if (attr
.second
->type
!= AST_CONSTANT
)
152 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
153 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
154 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
157 cell
->parameters
["\\WIDTH"] = RTLIL::Const(left
.size());
159 cell
->set("\\A", right
);
160 cell
->set("\\B", left
);
161 cell
->set("\\S", cond
);
162 cell
->set("\\Y", wire
);
167 // helper class for converting AST always nodes to RTLIL processes
168 struct AST_INTERNAL::ProcessGenerator
170 // input and output structures
172 RTLIL::SigSpec initSyncSignals
;
173 RTLIL::Process
*proc
;
174 const RTLIL::SigSpec
&outputSignals
;
176 // This always points to the RTLIL::CaseRule beeing filled at the moment
177 RTLIL::CaseRule
*current_case
;
179 // This two variables contain the replacement pattern to be used in the right hand side
180 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
181 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
182 // the value assigned in the first assignment. So when the first assignement is processed
183 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
184 RTLIL::SigSpec subst_rvalue_from
, subst_rvalue_to
;
186 // This two variables contain the replacement pattern to be used in the left hand side
187 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
188 // should not be connected to the signal foo. Instead it must be connected to the temporary
189 // signal that is used as input for the register that drives the signal foo.
190 RTLIL::SigSpec subst_lvalue_from
, subst_lvalue_to
;
192 // The code here generates a number of temprorary signal for each output register. This
193 // map helps generating nice numbered names for all this temporary signals.
194 std::map
<RTLIL::Wire
*, int> new_temp_count
;
196 // Buffer for generating the init action
197 RTLIL::SigSpec init_lvalue
, init_rvalue
;
199 ProcessGenerator(AstNode
*always
, RTLIL::SigSpec initSyncSignalsArg
= RTLIL::SigSpec()) : always(always
), initSyncSignals(initSyncSignalsArg
), outputSignals(subst_lvalue_from
)
201 // generate process and simple root case
202 proc
= new RTLIL::Process
;
203 proc
->attributes
["\\src"] = stringf("%s:%d", always
->filename
.c_str(), always
->linenum
);
204 proc
->name
= stringf("$proc$%s:%d$%d", always
->filename
.c_str(), always
->linenum
, RTLIL::autoidx
++);
205 for (auto &attr
: always
->attributes
) {
206 if (attr
.second
->type
!= AST_CONSTANT
)
207 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
208 attr
.first
.c_str(), always
->filename
.c_str(), always
->linenum
);
209 proc
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
211 current_module
->processes
[proc
->name
] = proc
;
212 current_case
= &proc
->root_case
;
214 // create initial temporary signal for all output registers
215 collect_lvalues(subst_lvalue_from
, always
, true, true);
216 subst_lvalue_to
= new_temp_signal(subst_lvalue_from
);
218 bool found_anyedge_syncs
= false;
219 for (auto child
: always
->children
)
220 if (child
->type
== AST_EDGE
)
221 found_anyedge_syncs
= true;
223 if (found_anyedge_syncs
) {
224 log("Note: Assuming pure combinatorial block at %s:%d in\n", always
->filename
.c_str(), always
->linenum
);
225 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
226 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
229 // create syncs for the process
230 bool found_clocked_sync
= false;
231 for (auto child
: always
->children
)
232 if (child
->type
== AST_POSEDGE
|| child
->type
== AST_NEGEDGE
) {
233 found_clocked_sync
= true;
234 if (found_anyedge_syncs
)
235 log_error("Found non-synthesizable event list at %s:%d!\n", always
->filename
.c_str(), always
->linenum
);
236 RTLIL::SyncRule
*syncrule
= new RTLIL::SyncRule
;
237 syncrule
->type
= child
->type
== AST_POSEDGE
? RTLIL::STp
: RTLIL::STn
;
238 syncrule
->signal
= child
->children
[0]->genRTLIL();
239 addChunkActions(syncrule
->actions
, subst_lvalue_from
, subst_lvalue_to
, true);
240 proc
->syncs
.push_back(syncrule
);
242 if (proc
->syncs
.empty()) {
243 RTLIL::SyncRule
*syncrule
= new RTLIL::SyncRule
;
244 syncrule
->type
= RTLIL::STa
;
245 syncrule
->signal
= RTLIL::SigSpec();
246 addChunkActions(syncrule
->actions
, subst_lvalue_from
, subst_lvalue_to
, true);
247 proc
->syncs
.push_back(syncrule
);
250 // create initial assignments for the temporary signals
251 if ((flag_nolatches
|| always
->get_bool_attribute("\\nolatches") || current_module
->get_bool_attribute("\\nolatches")) && !found_clocked_sync
) {
252 subst_rvalue_from
= subst_lvalue_from
;
253 subst_rvalue_to
= RTLIL::SigSpec(RTLIL::State::Sx
, subst_rvalue_from
.size());
255 addChunkActions(current_case
->actions
, subst_lvalue_to
, subst_lvalue_from
);
259 for (auto child
: always
->children
)
260 if (child
->type
== AST_BLOCK
)
263 if (initSyncSignals
.size() > 0)
265 RTLIL::SyncRule
*sync
= new RTLIL::SyncRule
;
266 sync
->type
= RTLIL::SyncType::STi
;
267 proc
->syncs
.push_back(sync
);
269 log_assert(init_lvalue
.size() == init_rvalue
.size());
272 for (auto &init_lvalue_c
: init_lvalue
.chunks()) {
273 RTLIL::SigSpec lhs
= init_lvalue_c
;
274 RTLIL::SigSpec rhs
= init_rvalue
.extract(offset
, init_lvalue_c
.width
);
275 sync
->actions
.push_back(RTLIL::SigSig(lhs
, rhs
));
276 offset
+= lhs
.size();
281 // create new temporary signals
282 RTLIL::SigSpec
new_temp_signal(RTLIL::SigSpec sig
)
284 std::vector
<RTLIL::SigChunk
> chunks
= sig
.chunks();
286 for (int i
= 0; i
< SIZE(chunks
); i
++)
288 RTLIL::SigChunk
&chunk
= chunks
[i
];
289 if (chunk
.wire
== NULL
)
292 std::string wire_name
;
294 wire_name
= stringf("$%d%s[%d:%d]", new_temp_count
[chunk
.wire
]++,
295 chunk
.wire
->name
.c_str(), chunk
.width
+chunk
.offset
-1, chunk
.offset
);;
296 if (chunk
.wire
->name
.find('$') != std::string::npos
)
297 wire_name
+= stringf("$%d", RTLIL::autoidx
++);
298 } while (current_module
->wires_
.count(wire_name
) > 0);
300 RTLIL::Wire
*wire
= current_module
->addWire(wire_name
, chunk
.width
);
301 wire
->attributes
["\\src"] = stringf("%s:%d", always
->filename
.c_str(), always
->linenum
);
310 // recursively traverse the AST an collect all assigned signals
311 void collect_lvalues(RTLIL::SigSpec
®
, AstNode
*ast
, bool type_eq
, bool type_le
, bool run_sort_and_unify
= true)
316 for (auto child
: ast
->children
)
317 if (child
!= ast
->children
[0]) {
318 log_assert(child
->type
== AST_COND
);
319 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
326 for (auto child
: ast
->children
)
327 if (child
->type
== AST_BLOCK
)
328 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
332 for (auto child
: ast
->children
) {
333 if (child
->type
== AST_ASSIGN_EQ
&& type_eq
)
334 reg
.append(child
->children
[0]->genRTLIL());
335 if (child
->type
== AST_ASSIGN_LE
&& type_le
)
336 reg
.append(child
->children
[0]->genRTLIL());
337 if (child
->type
== AST_CASE
|| child
->type
== AST_BLOCK
)
338 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
346 if (run_sort_and_unify
)
347 reg
.sort_and_unify();
350 // remove all assignments to the given signal pattern in a case and all its children.
351 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
352 // function is called to clean up the first two assignments as they are overwritten by
353 // the third assignment.
354 void removeSignalFromCaseTree(RTLIL::SigSpec pattern
, RTLIL::CaseRule
*cs
)
356 for (auto it
= cs
->actions
.begin(); it
!= cs
->actions
.end(); it
++)
357 it
->first
.remove2(pattern
, &it
->second
);
359 for (auto it
= cs
->switches
.begin(); it
!= cs
->switches
.end(); it
++)
360 for (auto it2
= (*it
)->cases
.begin(); it2
!= (*it
)->cases
.end(); it2
++)
361 removeSignalFromCaseTree(pattern
, *it2
);
364 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
365 // are avoided and the generated $mux cells have a more "natural" size.
366 void addChunkActions(std::vector
<RTLIL::SigSig
> &actions
, RTLIL::SigSpec lvalue
, RTLIL::SigSpec rvalue
, bool inSyncRule
= false)
368 if (inSyncRule
&& initSyncSignals
.size() > 0) {
369 init_lvalue
.append(lvalue
.extract(initSyncSignals
));
370 init_rvalue
.append(lvalue
.extract(initSyncSignals
, &rvalue
));
371 lvalue
.remove2(initSyncSignals
, &rvalue
);
373 log_assert(lvalue
.size() == rvalue
.size());
376 for (auto &lvalue_c
: lvalue
.chunks()) {
377 RTLIL::SigSpec lhs
= lvalue_c
;
378 RTLIL::SigSpec rhs
= rvalue
.extract(offset
, lvalue_c
.width
);
379 if (inSyncRule
&& lvalue_c
.wire
&& lvalue_c
.wire
->get_bool_attribute("\\nosync"))
380 rhs
= RTLIL::SigSpec(RTLIL::State::Sx
, rhs
.size());
381 actions
.push_back(RTLIL::SigSig(lhs
, rhs
));
382 offset
+= lhs
.size();
386 // recursively process the AST and fill the RTLIL::Process
387 void processAst(AstNode
*ast
)
392 for (auto child
: ast
->children
)
399 RTLIL::SigSpec unmapped_lvalue
= ast
->children
[0]->genRTLIL(), lvalue
= unmapped_lvalue
;
400 RTLIL::SigSpec rvalue
= ast
->children
[1]->genWidthRTLIL(lvalue
.size(), &subst_rvalue_from
, &subst_rvalue_to
);
401 lvalue
.replace(subst_lvalue_from
, subst_lvalue_to
);
403 if (ast
->type
== AST_ASSIGN_EQ
) {
404 subst_rvalue_from
.remove2(unmapped_lvalue
, &subst_rvalue_to
);
405 subst_rvalue_from
.append(unmapped_lvalue
);
406 subst_rvalue_to
.append(rvalue
);
409 removeSignalFromCaseTree(lvalue
, current_case
);
410 current_case
->actions
.push_back(RTLIL::SigSig(lvalue
, rvalue
));
416 RTLIL::SwitchRule
*sw
= new RTLIL::SwitchRule
;
417 sw
->signal
= ast
->children
[0]->genWidthRTLIL(-1, &subst_rvalue_from
, &subst_rvalue_to
);
418 current_case
->switches
.push_back(sw
);
420 for (auto &attr
: ast
->attributes
) {
421 if (attr
.second
->type
!= AST_CONSTANT
)
422 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
423 attr
.first
.c_str(), ast
->filename
.c_str(), ast
->linenum
);
424 sw
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
427 RTLIL::SigSpec this_case_eq_lvalue
;
428 collect_lvalues(this_case_eq_lvalue
, ast
, true, false);
430 RTLIL::SigSpec this_case_eq_ltemp
= new_temp_signal(this_case_eq_lvalue
);
432 RTLIL::SigSpec this_case_eq_rvalue
= this_case_eq_lvalue
;
433 this_case_eq_rvalue
.replace(subst_rvalue_from
, subst_rvalue_to
);
435 RTLIL::SigSpec backup_subst_lvalue_from
= subst_lvalue_from
;
436 RTLIL::SigSpec backup_subst_lvalue_to
= subst_lvalue_to
;
438 RTLIL::SigSpec backup_subst_rvalue_from
= subst_rvalue_from
;
439 RTLIL::SigSpec backup_subst_rvalue_to
= subst_rvalue_to
;
441 RTLIL::CaseRule
*default_case
= NULL
;
442 RTLIL::CaseRule
*last_generated_case
= NULL
;
443 for (auto child
: ast
->children
)
445 if (child
== ast
->children
[0])
447 log_assert(child
->type
== AST_COND
);
449 subst_lvalue_from
= backup_subst_lvalue_from
;
450 subst_lvalue_to
= backup_subst_lvalue_to
;
452 subst_rvalue_from
= backup_subst_rvalue_from
;
453 subst_rvalue_to
= backup_subst_rvalue_to
;
455 subst_lvalue_from
.remove2(this_case_eq_lvalue
, &subst_lvalue_to
);
456 subst_lvalue_from
.append(this_case_eq_lvalue
);
457 subst_lvalue_to
.append(this_case_eq_ltemp
);
459 RTLIL::CaseRule
*backup_case
= current_case
;
460 current_case
= new RTLIL::CaseRule
;
461 last_generated_case
= current_case
;
462 addChunkActions(current_case
->actions
, this_case_eq_ltemp
, this_case_eq_rvalue
);
463 for (auto node
: child
->children
) {
464 if (node
->type
== AST_DEFAULT
)
465 default_case
= current_case
;
466 else if (node
->type
== AST_BLOCK
)
469 current_case
->compare
.push_back(node
->genWidthRTLIL(sw
->signal
.size(), &subst_rvalue_from
, &subst_rvalue_to
));
471 if (default_case
!= current_case
)
472 sw
->cases
.push_back(current_case
);
474 log_assert(current_case
->compare
.size() == 0);
475 current_case
= backup_case
;
478 if (last_generated_case
!= NULL
&& ast
->get_bool_attribute("\\full_case") && default_case
== NULL
) {
479 last_generated_case
->compare
.clear();
481 if (default_case
== NULL
) {
482 default_case
= new RTLIL::CaseRule
;
483 addChunkActions(default_case
->actions
, this_case_eq_ltemp
, this_case_eq_rvalue
);
485 sw
->cases
.push_back(default_case
);
488 subst_lvalue_from
= backup_subst_lvalue_from
;
489 subst_lvalue_to
= backup_subst_lvalue_to
;
491 subst_rvalue_from
= backup_subst_rvalue_from
;
492 subst_rvalue_to
= backup_subst_rvalue_to
;
494 subst_rvalue_from
.remove2(this_case_eq_lvalue
, &subst_rvalue_to
);
495 subst_rvalue_from
.append(this_case_eq_lvalue
);
496 subst_rvalue_to
.append(this_case_eq_ltemp
);
498 this_case_eq_lvalue
.replace(subst_lvalue_from
, subst_lvalue_to
);
499 removeSignalFromCaseTree(this_case_eq_lvalue
, current_case
);
500 addChunkActions(current_case
->actions
, this_case_eq_lvalue
, this_case_eq_ltemp
);
505 log_error("Found wire declaration in block without label at at %s:%d!\n", ast
->filename
.c_str(), ast
->linenum
);
518 // detect sign and width of an expression
519 void AstNode::detectSignWidthWorker(int &width_hint
, bool &sign_hint
, bool *found_real
)
521 std::string type_name
;
522 bool sub_sign_hint
= true;
523 int sub_width_hint
= -1;
525 AstNode
*range
= NULL
;
526 AstNode
*id_ast
= NULL
;
528 bool local_found_real
= false;
529 if (found_real
== NULL
)
530 found_real
= &local_found_real
;
535 width_hint
= std::max(width_hint
, int(bits
.size()));
542 width_hint
= std::max(width_hint
, 32);
547 if (id_ast
== NULL
&& current_scope
.count(str
))
548 id_ast
= current_scope
.at(str
);
550 log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
551 if (id_ast
->type
== AST_PARAMETER
|| id_ast
->type
== AST_LOCALPARAM
) {
552 if (id_ast
->children
.size() > 1 && id_ast
->children
[1]->range_valid
) {
553 this_width
= id_ast
->children
[1]->range_left
- id_ast
->children
[1]->range_right
+ 1;
555 if (id_ast
->children
[0]->type
== AST_CONSTANT
) {
556 this_width
= id_ast
->children
[0]->bits
.size();
558 log_error("Failed to detect width for parameter %s at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
559 if (children
.size() != 0)
561 } else if (id_ast
->type
== AST_WIRE
|| id_ast
->type
== AST_AUTOWIRE
) {
562 if (!id_ast
->range_valid
) {
563 if (id_ast
->type
== AST_AUTOWIRE
)
566 // current_ast_mod->dumpAst(NULL, "mod> ");
568 // id_ast->dumpAst(NULL, "decl> ");
569 // dumpAst(NULL, "ref> ");
570 log_error("Failed to detect with of signal access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
573 this_width
= id_ast
->range_left
- id_ast
->range_right
+ 1;
574 if (children
.size() != 0)
577 } else if (id_ast
->type
== AST_GENVAR
) {
579 } else if (id_ast
->type
== AST_MEMORY
) {
580 if (!id_ast
->children
[0]->range_valid
)
581 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
582 this_width
= id_ast
->children
[0]->range_left
- id_ast
->children
[0]->range_right
+ 1;
584 log_error("Failed to detect width for identifier %s at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
586 if (range
->children
.size() == 1)
588 else if (!range
->range_valid
) {
589 AstNode
*left_at_zero_ast
= children
[0]->children
[0]->clone();
590 AstNode
*right_at_zero_ast
= children
[0]->children
.size() >= 2 ? children
[0]->children
[1]->clone() : left_at_zero_ast
->clone();
591 while (left_at_zero_ast
->simplify(true, true, false, 1, -1, false, false)) { }
592 while (right_at_zero_ast
->simplify(true, true, false, 1, -1, false, false)) { }
593 if (left_at_zero_ast
->type
!= AST_CONSTANT
|| right_at_zero_ast
->type
!= AST_CONSTANT
)
594 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
595 str
.c_str(), filename
.c_str(), linenum
);
596 this_width
= left_at_zero_ast
->integer
- right_at_zero_ast
->integer
+ 1;
597 delete left_at_zero_ast
;
598 delete right_at_zero_ast
;
600 this_width
= range
->range_left
- range
->range_right
+ 1;
603 width_hint
= std::max(width_hint
, this_width
);
604 if (!id_ast
->is_signed
)
609 while (children
[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
610 if (children
[0]->type
!= AST_CONSTANT
)
611 log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename
.c_str(), linenum
);
612 children
[1]->detectSignWidthWorker(sub_width_hint
, sign_hint
);
613 width_hint
= std::max(width_hint
, children
[0]->bitsAsConst().as_int());
617 children
.at(0)->detectSignWidthWorker(width_hint
, sub_sign_hint
);
620 case AST_TO_UNSIGNED
:
621 children
.at(0)->detectSignWidthWorker(width_hint
, sub_sign_hint
);
626 for (auto child
: children
) {
628 sub_sign_hint
= true;
629 child
->detectSignWidthWorker(sub_width_hint
, sub_sign_hint
);
630 this_width
+= sub_width_hint
;
632 width_hint
= std::max(width_hint
, this_width
);
637 while (children
[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
638 if (children
[0]->type
!= AST_CONSTANT
)
639 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename
.c_str(), linenum
);
640 children
[1]->detectSignWidthWorker(sub_width_hint
, sub_sign_hint
);
641 width_hint
= std::max(width_hint
, children
[0]->bitsAsConst().as_int() * sub_width_hint
);
648 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
655 for (auto child
: children
)
656 child
->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
662 case AST_REDUCE_XNOR
:
663 case AST_REDUCE_BOOL
:
664 width_hint
= std::max(width_hint
, 1);
669 case AST_SHIFT_RIGHT
:
670 case AST_SHIFT_SLEFT
:
671 case AST_SHIFT_SRIGHT
:
673 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
684 width_hint
= std::max(width_hint
, 1);
693 for (auto child
: children
)
694 child
->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
700 width_hint
= std::max(width_hint
, 1);
705 children
.at(1)->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
706 children
.at(2)->detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
710 if (!id2ast
->is_signed
)
712 if (!id2ast
->children
[0]->range_valid
)
713 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
714 this_width
= id2ast
->children
[0]->range_left
- id2ast
->children
[0]->range_right
+ 1;
715 width_hint
= std::max(width_hint
, this_width
);
718 // everything should have been handled above -> print error if not.
720 for (auto f
: log_files
)
721 current_ast
->dumpAst(f
, "verilog-ast> ");
722 log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
723 type2str(type
).c_str(), filename
.c_str(), linenum
);
730 // detect sign and width of an expression
731 void AstNode::detectSignWidth(int &width_hint
, bool &sign_hint
, bool *found_real
)
737 detectSignWidthWorker(width_hint
, sign_hint
, found_real
);
740 // create RTLIL from an AST node
741 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
742 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
744 // note that this function is influenced by a number of global variables that might be set when
745 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
746 // larger expressions into a netlist of cells.
747 RTLIL::SigSpec
AstNode::genRTLIL(int width_hint
, bool sign_hint
)
749 // in the following big switch() statement there are some uses of
750 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
751 // cases this variable is used to hold the type of the cell that should
752 // be instanciated for this type of AST node.
753 std::string type_name
;
755 current_filename
= filename
;
756 set_line_num(linenum
);
760 // simply ignore this nodes.
761 // they are eighter leftovers from simplify() or are referenced by other nodes
762 // and are only accessed here thru this references
775 // remember the parameter, needed for example in techmap
777 current_module
->avail_parameters
.insert(str
);
780 // create an RTLIL::Wire for an AST_WIRE node
782 if (current_module
->wires_
.count(str
) != 0)
783 log_error("Re-definition of signal `%s' at %s:%d!\n",
784 str
.c_str(), filename
.c_str(), linenum
);
786 log_error("Signal `%s' with non-constant width at %s:%d!\n",
787 str
.c_str(), filename
.c_str(), linenum
);
789 log_assert(range_left
>= range_right
|| (range_left
== -1 && range_right
== 0));
791 RTLIL::Wire
*wire
= current_module
->addWire(str
, range_left
- range_right
+ 1);
792 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
793 wire
->start_offset
= range_right
;
794 wire
->port_id
= port_id
;
795 wire
->port_input
= is_input
;
796 wire
->port_output
= is_output
;
797 wire
->upto
= range_swapped
;
799 for (auto &attr
: attributes
) {
800 if (attr
.second
->type
!= AST_CONSTANT
)
801 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
802 attr
.first
.c_str(), filename
.c_str(), linenum
);
803 wire
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
808 // create an RTLIL::Memory for an AST_MEMORY node
810 if (current_module
->memories
.count(str
) != 0)
811 log_error("Re-definition of memory `%s' at %s:%d!\n",
812 str
.c_str(), filename
.c_str(), linenum
);
814 log_assert(children
.size() >= 2);
815 log_assert(children
[0]->type
== AST_RANGE
);
816 log_assert(children
[1]->type
== AST_RANGE
);
818 if (!children
[0]->range_valid
|| !children
[1]->range_valid
)
819 log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
820 str
.c_str(), filename
.c_str(), linenum
);
822 RTLIL::Memory
*memory
= new RTLIL::Memory
;
823 memory
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
825 memory
->width
= children
[0]->range_left
- children
[0]->range_right
+ 1;
826 memory
->start_offset
= children
[0]->range_right
;
827 memory
->size
= children
[1]->range_left
- children
[1]->range_right
;
828 current_module
->memories
[memory
->name
] = memory
;
830 if (memory
->size
< 0)
832 memory
->size
+= std::min(children
[1]->range_left
, children
[1]->range_right
) + 1;
834 for (auto &attr
: attributes
) {
835 if (attr
.second
->type
!= AST_CONSTANT
)
836 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
837 attr
.first
.c_str(), filename
.c_str(), linenum
);
838 memory
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
843 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
847 detectSignWidth(width_hint
, sign_hint
);
849 is_signed
= sign_hint
;
850 return RTLIL::SigSpec(bitsAsConst());
855 RTLIL::SigSpec sig
= realAsConst(width_hint
);
856 log("Warning: converting real value %e to binary %s at %s:%d.\n",
857 realvalue
, log_signal(sig
), filename
.c_str(), linenum
);
861 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
862 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
863 // shifter cell is created and the output signal of this cell is returned
866 RTLIL::Wire
*wire
= NULL
;
867 RTLIL::SigChunk chunk
;
869 int add_undef_bits_msb
= 0;
870 int add_undef_bits_lsb
= 0;
872 if (id2ast
&& id2ast
->type
== AST_AUTOWIRE
&& current_module
->wires_
.count(str
) == 0) {
873 RTLIL::Wire
*wire
= current_module
->addWire(str
);
874 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
877 log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str
.c_str(), filename
.c_str(), linenum
);
879 log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str
.c_str(), filename
.c_str(), linenum
);
881 else if (id2ast
->type
== AST_PARAMETER
|| id2ast
->type
== AST_LOCALPARAM
) {
882 if (id2ast
->children
[0]->type
!= AST_CONSTANT
)
883 log_error("Parameter %s does not evaluate to constant value at %s:%d!\n",
884 str
.c_str(), filename
.c_str(), linenum
);
885 chunk
= RTLIL::Const(id2ast
->children
[0]->bits
);
886 goto use_const_chunk
;
888 else if (!id2ast
|| (id2ast
->type
!= AST_WIRE
&& id2ast
->type
!= AST_AUTOWIRE
&&
889 id2ast
->type
!= AST_MEMORY
) || current_module
->wires_
.count(str
) == 0)
890 log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
891 str
.c_str(), filename
.c_str(), linenum
);
893 if (id2ast
->type
== AST_MEMORY
)
894 log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
895 str
.c_str(), filename
.c_str(), linenum
);
897 wire
= current_module
->wires_
[str
];
899 chunk
.width
= wire
->width
;
903 if (children
.size() != 0) {
904 log_assert(children
[0]->type
== AST_RANGE
);
905 int source_width
= id2ast
->range_left
- id2ast
->range_right
+ 1;
906 int source_offset
= id2ast
->range_right
;
907 if (!children
[0]->range_valid
) {
908 AstNode
*left_at_zero_ast
= children
[0]->children
[0]->clone();
909 AstNode
*right_at_zero_ast
= children
[0]->children
.size() >= 2 ? children
[0]->children
[1]->clone() : left_at_zero_ast
->clone();
910 while (left_at_zero_ast
->simplify(true, true, false, 1, -1, false, false)) { }
911 while (right_at_zero_ast
->simplify(true, true, false, 1, -1, false, false)) { }
912 if (left_at_zero_ast
->type
!= AST_CONSTANT
|| right_at_zero_ast
->type
!= AST_CONSTANT
)
913 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
914 str
.c_str(), filename
.c_str(), linenum
);
915 int width
= left_at_zero_ast
->integer
- right_at_zero_ast
->integer
+ 1;
916 AstNode
*fake_ast
= new AstNode(AST_NONE
, clone(), children
[0]->children
.size() >= 2 ?
917 children
[0]->children
[1]->clone() : children
[0]->children
[0]->clone());
918 fake_ast
->children
[0]->delete_children();
919 RTLIL::SigSpec shift_val
= fake_ast
->children
[1]->genRTLIL();
920 if (id2ast
->range_right
!= 0)
921 shift_val
= current_module
->Sub(NEW_ID
, shift_val
, id2ast
->range_right
);
922 if (id2ast
->range_swapped
)
923 shift_val
= current_module
->Sub(NEW_ID
, RTLIL::SigSpec(source_width
- width
), shift_val
);
924 RTLIL::SigSpec sig
= binop2rtlil(fake_ast
, "$shr", width
, fake_ast
->children
[0]->genRTLIL(), shift_val
);
925 delete left_at_zero_ast
;
926 delete right_at_zero_ast
;
930 chunk
.width
= children
[0]->range_left
- children
[0]->range_right
+ 1;
931 chunk
.offset
= children
[0]->range_right
- source_offset
;
932 if (id2ast
->range_swapped
)
933 chunk
.offset
= (id2ast
->range_left
- id2ast
->range_right
+ 1) - (chunk
.offset
+ chunk
.width
);
934 if (chunk
.offset
>= source_width
|| chunk
.offset
+ chunk
.width
< 0) {
935 if (chunk
.width
== 1)
936 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
937 str
.c_str(), filename
.c_str(), linenum
);
939 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
940 str
.c_str(), filename
.c_str(), linenum
, chunk
.width
);
941 chunk
= RTLIL::SigChunk(RTLIL::State::Sx
, chunk
.width
);
943 if (chunk
.width
+ chunk
.offset
> source_width
) {
944 add_undef_bits_msb
= (chunk
.width
+ chunk
.offset
) - source_width
;
945 chunk
.width
-= add_undef_bits_msb
;
947 if (chunk
.offset
< 0) {
948 add_undef_bits_lsb
= -chunk
.offset
;
949 chunk
.width
-= add_undef_bits_lsb
;
950 chunk
.offset
+= add_undef_bits_lsb
;
952 if (add_undef_bits_lsb
)
953 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
954 str
.c_str(), filename
.c_str(), linenum
, add_undef_bits_lsb
);
955 if (add_undef_bits_msb
)
956 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
957 str
.c_str(), filename
.c_str(), linenum
, add_undef_bits_msb
);
962 RTLIL::SigSpec sig
= { RTLIL::SigSpec(RTLIL::State::Sx
, add_undef_bits_msb
), chunk
, RTLIL::SigSpec(RTLIL::State::Sx
, add_undef_bits_lsb
) };
964 if (genRTLIL_subst_from
&& genRTLIL_subst_to
)
965 sig
.replace(*genRTLIL_subst_from
, *genRTLIL_subst_to
);
967 is_signed
= children
.size() > 0 ? false : id2ast
->is_signed
&& sign_hint
;
971 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
973 case AST_TO_UNSIGNED
: {
974 RTLIL::SigSpec sig
= children
[0]->genRTLIL();
975 if (sig
.size() < width_hint
)
976 sig
.extend_u0(width_hint
, sign_hint
);
977 is_signed
= sign_hint
;
981 // concatenation of signals can be done directly using RTLIL::SigSpec
984 for (auto it
= children
.begin(); it
!= children
.end(); it
++)
985 sig
.append((*it
)->genRTLIL());
986 if (sig
.size() < width_hint
)
987 sig
.extend_u0(width_hint
, false);
991 // replication of signals can be done directly using RTLIL::SigSpec
992 case AST_REPLICATE
: {
993 RTLIL::SigSpec left
= children
[0]->genRTLIL();
994 RTLIL::SigSpec right
= children
[1]->genRTLIL();
995 if (!left
.is_fully_const())
996 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename
.c_str(), linenum
);
997 int count
= left
.as_int();
999 for (int i
= 0; i
< count
; i
++)
1001 if (sig
.size() < width_hint
)
1002 sig
.extend_u0(width_hint
, false);
1007 // generate cells for unary operations: $not, $pos, $neg
1008 if (0) { case AST_BIT_NOT
: type_name
= "$not"; }
1009 if (0) { case AST_POS
: type_name
= "$pos"; }
1010 if (0) { case AST_NEG
: type_name
= "$neg"; }
1012 RTLIL::SigSpec arg
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1013 is_signed
= children
[0]->is_signed
;
1014 int width
= arg
.size();
1015 if (width_hint
> 0) {
1017 widthExtend(this, arg
, width
, is_signed
, "$pos");
1019 return uniop2rtlil(this, type_name
, width
, arg
);
1022 // generate cells for binary operations: $and, $or, $xor, $xnor
1023 if (0) { case AST_BIT_AND
: type_name
= "$and"; }
1024 if (0) { case AST_BIT_OR
: type_name
= "$or"; }
1025 if (0) { case AST_BIT_XOR
: type_name
= "$xor"; }
1026 if (0) { case AST_BIT_XNOR
: type_name
= "$xnor"; }
1029 detectSignWidth(width_hint
, sign_hint
);
1030 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1031 RTLIL::SigSpec right
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1032 int width
= std::max(left
.size(), right
.size());
1035 is_signed
= children
[0]->is_signed
&& children
[1]->is_signed
;
1036 return binop2rtlil(this, type_name
, width
, left
, right
);
1039 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1040 if (0) { case AST_REDUCE_AND
: type_name
= "$reduce_and"; }
1041 if (0) { case AST_REDUCE_OR
: type_name
= "$reduce_or"; }
1042 if (0) { case AST_REDUCE_XOR
: type_name
= "$reduce_xor"; }
1043 if (0) { case AST_REDUCE_XNOR
: type_name
= "$reduce_xnor"; }
1045 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1046 RTLIL::SigSpec sig
= uniop2rtlil(this, type_name
, std::max(width_hint
, 1), arg
);
1050 // generate cells for unary operations: $reduce_bool
1051 // (this is actually just an $reduce_or, but for clearity a different cell type is used)
1052 if (0) { case AST_REDUCE_BOOL
: type_name
= "$reduce_bool"; }
1054 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1055 RTLIL::SigSpec sig
= arg
.size() > 1 ? uniop2rtlil(this, type_name
, std::max(width_hint
, 1), arg
) : arg
;
1059 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1060 if (0) { case AST_SHIFT_LEFT
: type_name
= "$shl"; }
1061 if (0) { case AST_SHIFT_RIGHT
: type_name
= "$shr"; }
1062 if (0) { case AST_SHIFT_SLEFT
: type_name
= "$sshl"; }
1063 if (0) { case AST_SHIFT_SRIGHT
: type_name
= "$sshr"; }
1066 detectSignWidth(width_hint
, sign_hint
);
1067 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1068 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1069 int width
= width_hint
> 0 ? width_hint
: left
.size();
1070 is_signed
= children
[0]->is_signed
;
1071 return binop2rtlil(this, type_name
, width
, left
, right
);
1074 // generate cells for binary operations: $pow
1079 children
[1]->detectSignWidth(right_width
, right_signed
);
1081 detectSignWidth(width_hint
, sign_hint
);
1082 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1083 RTLIL::SigSpec right
= children
[1]->genRTLIL(right_width
, right_signed
);
1084 int width
= width_hint
> 0 ? width_hint
: left
.size();
1085 is_signed
= children
[0]->is_signed
;
1086 if (!flag_noopt
&& left
.is_fully_const() && left
.as_int() == 2 && !right_signed
)
1087 return binop2rtlil(this, "$shl", width
, RTLIL::SigSpec(1, left
.size()), right
);
1088 return binop2rtlil(this, "$pow", width
, left
, right
);
1091 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1092 if (0) { case AST_LT
: type_name
= "$lt"; }
1093 if (0) { case AST_LE
: type_name
= "$le"; }
1094 if (0) { case AST_EQ
: type_name
= "$eq"; }
1095 if (0) { case AST_NE
: type_name
= "$ne"; }
1096 if (0) { case AST_EQX
: type_name
= "$eqx"; }
1097 if (0) { case AST_NEX
: type_name
= "$nex"; }
1098 if (0) { case AST_GE
: type_name
= "$ge"; }
1099 if (0) { case AST_GT
: type_name
= "$gt"; }
1101 int width
= std::max(width_hint
, 1);
1102 width_hint
= -1, sign_hint
= true;
1103 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
);
1104 children
[1]->detectSignWidthWorker(width_hint
, sign_hint
);
1105 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1106 RTLIL::SigSpec right
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1107 RTLIL::SigSpec sig
= binop2rtlil(this, type_name
, width
, left
, right
);
1111 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1112 if (0) { case AST_ADD
: type_name
= "$add"; }
1113 if (0) { case AST_SUB
: type_name
= "$sub"; }
1114 if (0) { case AST_MUL
: type_name
= "$mul"; }
1115 if (0) { case AST_DIV
: type_name
= "$div"; }
1116 if (0) { case AST_MOD
: type_name
= "$mod"; }
1119 detectSignWidth(width_hint
, sign_hint
);
1120 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1121 RTLIL::SigSpec right
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1123 int width
= std::max(left
.size(), right
.size());
1124 if (width
> width_hint
&& width_hint
> 0)
1126 if (width
< width_hint
) {
1127 if (type
== AST_ADD
|| type
== AST_SUB
|| type
== AST_DIV
)
1129 if (type
== AST_SUB
&& (!children
[0]->is_signed
|| !children
[1]->is_signed
))
1131 if (type
== AST_MUL
)
1132 width
= std::min(left
.size() + right
.size(), width_hint
);
1135 int width
= std::max(std::max(left
.size(), right
.size()), width_hint
);
1137 is_signed
= children
[0]->is_signed
&& children
[1]->is_signed
;
1138 return binop2rtlil(this, type_name
, width
, left
, right
);
1141 // generate cells for binary operations: $logic_and, $logic_or
1142 if (0) { case AST_LOGIC_AND
: type_name
= "$logic_and"; }
1143 if (0) { case AST_LOGIC_OR
: type_name
= "$logic_or"; }
1145 RTLIL::SigSpec left
= children
[0]->genRTLIL();
1146 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1147 return binop2rtlil(this, type_name
, std::max(width_hint
, 1), left
, right
);
1150 // generate cells for unary operations: $logic_not
1153 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1154 return uniop2rtlil(this, "$logic_not", std::max(width_hint
, 1), arg
);
1157 // generate multiplexer for ternary operator (aka ?:-operator)
1161 detectSignWidth(width_hint
, sign_hint
);
1163 RTLIL::SigSpec cond
= children
[0]->genRTLIL();
1164 RTLIL::SigSpec val1
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1165 RTLIL::SigSpec val2
= children
[2]->genRTLIL(width_hint
, sign_hint
);
1167 if (cond
.size() > 1)
1168 cond
= uniop2rtlil(this, "$reduce_bool", 1, cond
, false);
1170 int width
= std::max(val1
.size(), val2
.size());
1171 is_signed
= children
[1]->is_signed
&& children
[2]->is_signed
;
1172 widthExtend(this, val1
, width
, is_signed
, "$bu0");
1173 widthExtend(this, val2
, width
, is_signed
, "$bu0");
1175 RTLIL::SigSpec sig
= mux2rtlil(this, cond
, val1
, val2
);
1177 if (sig
.size() < width_hint
)
1178 sig
.extend_u0(width_hint
, sign_hint
);
1182 // generate $memrd cells for memory read ports
1185 std::stringstream sstr
;
1186 sstr
<< "$memrd$" << str
<< "$" << filename
<< ":" << linenum
<< "$" << (RTLIL::autoidx
++);
1188 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), "$memrd");
1189 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1191 RTLIL::Wire
*wire
= current_module
->addWire(cell
->name
+ "_DATA", current_module
->memories
[str
]->width
);
1192 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1195 while ((1 << addr_bits
) < current_module
->memories
[str
]->size
)
1198 cell
->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx
, 1));
1199 cell
->set("\\ADDR", children
[0]->genWidthRTLIL(addr_bits
));
1200 cell
->set("\\DATA", RTLIL::SigSpec(wire
));
1202 cell
->parameters
["\\MEMID"] = RTLIL::Const(str
);
1203 cell
->parameters
["\\ABITS"] = RTLIL::Const(addr_bits
);
1204 cell
->parameters
["\\WIDTH"] = RTLIL::Const(wire
->width
);
1206 cell
->parameters
["\\CLK_ENABLE"] = RTLIL::Const(0);
1207 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(0);
1208 cell
->parameters
["\\TRANSPARENT"] = RTLIL::Const(0);
1210 return RTLIL::SigSpec(wire
);
1213 // generate $memwr cells for memory write ports
1216 std::stringstream sstr
;
1217 sstr
<< "$memwr$" << str
<< "$" << filename
<< ":" << linenum
<< "$" << (RTLIL::autoidx
++);
1219 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), "$memwr");
1220 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1223 while ((1 << addr_bits
) < current_module
->memories
[str
]->size
)
1226 cell
->set("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx
, 1));
1227 cell
->set("\\ADDR", children
[0]->genWidthRTLIL(addr_bits
));
1228 cell
->set("\\DATA", children
[1]->genWidthRTLIL(current_module
->memories
[str
]->width
));
1229 cell
->set("\\EN", children
[2]->genRTLIL());
1231 cell
->parameters
["\\MEMID"] = RTLIL::Const(str
);
1232 cell
->parameters
["\\ABITS"] = RTLIL::Const(addr_bits
);
1233 cell
->parameters
["\\WIDTH"] = RTLIL::Const(current_module
->memories
[str
]->width
);
1235 cell
->parameters
["\\CLK_ENABLE"] = RTLIL::Const(0);
1236 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(0);
1238 cell
->parameters
["\\PRIORITY"] = RTLIL::Const(RTLIL::autoidx
-1);
1242 // generate $assert cells
1245 log_assert(children
.size() == 2);
1247 RTLIL::SigSpec check
= children
[0]->genRTLIL();
1248 log_assert(check
.size() == 1);
1250 RTLIL::SigSpec en
= children
[1]->genRTLIL();
1251 log_assert(en
.size() == 1);
1253 std::stringstream sstr
;
1254 sstr
<< "$assert$" << filename
<< ":" << linenum
<< "$" << (RTLIL::autoidx
++);
1256 RTLIL::Cell
*cell
= current_module
->addCell(sstr
.str(), "$assert");
1257 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1259 for (auto &attr
: attributes
) {
1260 if (attr
.second
->type
!= AST_CONSTANT
)
1261 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1262 attr
.first
.c_str(), filename
.c_str(), linenum
);
1263 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
1266 cell
->set("\\A", check
);
1267 cell
->set("\\EN", en
);
1271 // add entries to current_module->connections for assignments (outside of always blocks)
1274 if (children
[0]->type
== AST_IDENTIFIER
&& children
[0]->id2ast
&& children
[0]->id2ast
->type
== AST_AUTOWIRE
) {
1275 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1276 RTLIL::SigSpec left
= children
[0]->genWidthRTLIL(right
.size());
1277 current_module
->connect(RTLIL::SigSig(left
, right
));
1279 RTLIL::SigSpec left
= children
[0]->genRTLIL();
1280 RTLIL::SigSpec right
= children
[1]->genWidthRTLIL(left
.size());
1281 current_module
->connect(RTLIL::SigSig(left
, right
));
1286 // create an RTLIL::Cell for an AST_CELL
1289 int port_counter
= 0, para_counter
= 0;
1291 if (current_module
->count_id(str
) != 0)
1292 log_error("Re-definition of cell `%s' at %s:%d!\n",
1293 str
.c_str(), filename
.c_str(), linenum
);
1295 RTLIL::Cell
*cell
= current_module
->addCell(str
, "");
1296 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1298 for (auto it
= children
.begin(); it
!= children
.end(); it
++) {
1299 AstNode
*child
= *it
;
1300 if (child
->type
== AST_CELLTYPE
) {
1301 cell
->type
= child
->str
;
1302 if (flag_icells
&& cell
->type
.substr(0, 2) == "\\$")
1303 cell
->type
= cell
->type
.substr(1);
1306 if (child
->type
== AST_PARASET
) {
1307 if (child
->children
[0]->type
!= AST_CONSTANT
)
1308 log_error("Parameter `%s' with non-constant value at %s:%d!\n",
1309 child
->str
.c_str(), filename
.c_str(), linenum
);
1310 if (child
->str
.size() == 0) {
1312 snprintf(buf
, 100, "$%d", ++para_counter
);
1313 cell
->parameters
[buf
] = child
->children
[0]->asParaConst();
1315 cell
->parameters
[child
->str
] = child
->children
[0]->asParaConst();
1319 if (child
->type
== AST_ARGUMENT
) {
1321 if (child
->children
.size() > 0)
1322 sig
= child
->children
[0]->genRTLIL();
1323 if (child
->str
.size() == 0) {
1325 snprintf(buf
, 100, "$%d", ++port_counter
);
1326 cell
->set(buf
, sig
);
1328 cell
->set(child
->str
, sig
);
1334 for (auto &attr
: attributes
) {
1335 if (attr
.second
->type
!= AST_CONSTANT
)
1336 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1337 attr
.first
.c_str(), filename
.c_str(), linenum
);
1338 cell
->attributes
[attr
.first
] = attr
.second
->asAttrConst();
1343 // use ProcessGenerator for always blocks
1345 AstNode
*always
= this->clone();
1346 ProcessGenerator
generator(always
);
1347 ignoreThisSignalsInInitial
.append(generator
.outputSignals
);
1352 AstNode
*always
= this->clone();
1353 ProcessGenerator
generator(always
, ignoreThisSignalsInInitial
);
1357 // everything should have been handled above -> print error if not.
1359 for (auto f
: log_files
)
1360 current_ast
->dumpAst(f
, "verilog-ast> ");
1361 type_name
= type2str(type
);
1362 log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
1363 type_name
.c_str(), filename
.c_str(), linenum
);
1366 return RTLIL::SigSpec();
1369 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1370 // signals must be substituted before beeing used as input values (used by ProcessGenerator)
1371 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1372 RTLIL::SigSpec
AstNode::genWidthRTLIL(int width
, RTLIL::SigSpec
*subst_from
, RTLIL::SigSpec
*subst_to
)
1374 RTLIL::SigSpec
*backup_subst_from
= genRTLIL_subst_from
;
1375 RTLIL::SigSpec
*backup_subst_to
= genRTLIL_subst_to
;
1378 genRTLIL_subst_from
= subst_from
;
1380 genRTLIL_subst_to
= subst_to
;
1382 bool sign_hint
= true;
1383 int width_hint
= width
;
1384 detectSignWidthWorker(width_hint
, sign_hint
);
1385 RTLIL::SigSpec sig
= genRTLIL(width_hint
, sign_hint
);
1387 genRTLIL_subst_from
= backup_subst_from
;
1388 genRTLIL_subst_to
= backup_subst_to
;
1391 sig
.extend_u0(width
, is_signed
);