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Merge pull request #672 from daveshah1/fix_bram
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "kernel/utils.h"
31 #include "libs/sha1/sha1.h"
32 #include "ast.h"
33
34 #include <sstream>
35 #include <stdarg.h>
36 #include <algorithm>
37
38 YOSYS_NAMESPACE_BEGIN
39
40 using namespace AST;
41 using namespace AST_INTERNAL;
42
43 // helper function for creating RTLIL code for unary operations
44 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
45 {
46 std::stringstream sstr;
47 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
48
49 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
51
52 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
54
55 if (gen_attributes)
56 for (auto &attr : that->attributes) {
57 if (attr.second->type != AST_CONSTANT)
58 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
59 attr.first.c_str());
60 cell->attributes[attr.first] = attr.second->asAttrConst();
61 }
62
63 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
64 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
65 cell->setPort("\\A", arg);
66
67 cell->parameters["\\Y_WIDTH"] = result_width;
68 cell->setPort("\\Y", wire);
69 return wire;
70 }
71
72 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
73 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
74 {
75 if (width <= sig.size()) {
76 sig.extend_u0(width, is_signed);
77 return;
78 }
79
80 std::stringstream sstr;
81 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
82
83 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
84 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
85
86 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
87 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
88
89 if (that != NULL)
90 for (auto &attr : that->attributes) {
91 if (attr.second->type != AST_CONSTANT)
92 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
93 attr.first.c_str());
94 cell->attributes[attr.first] = attr.second->asAttrConst();
95 }
96
97 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
98 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
99 cell->setPort("\\A", sig);
100
101 cell->parameters["\\Y_WIDTH"] = width;
102 cell->setPort("\\Y", wire);
103 sig = wire;
104 }
105
106 // helper function for creating RTLIL code for binary operations
107 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
108 {
109 std::stringstream sstr;
110 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
111
112 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
113 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
114
115 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
116 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
117
118 for (auto &attr : that->attributes) {
119 if (attr.second->type != AST_CONSTANT)
120 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
121 attr.first.c_str());
122 cell->attributes[attr.first] = attr.second->asAttrConst();
123 }
124
125 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
126 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
127
128 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
129 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
130
131 cell->setPort("\\A", left);
132 cell->setPort("\\B", right);
133
134 cell->parameters["\\Y_WIDTH"] = result_width;
135 cell->setPort("\\Y", wire);
136 return wire;
137 }
138
139 // helper function for creating RTLIL code for multiplexers
140 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
141 {
142 log_assert(cond.size() == 1);
143
144 std::stringstream sstr;
145 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
146
147 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
148 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
149
150 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
151 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
152
153 for (auto &attr : that->attributes) {
154 if (attr.second->type != AST_CONSTANT)
155 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
156 attr.first.c_str());
157 cell->attributes[attr.first] = attr.second->asAttrConst();
158 }
159
160 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
161
162 cell->setPort("\\A", right);
163 cell->setPort("\\B", left);
164 cell->setPort("\\S", cond);
165 cell->setPort("\\Y", wire);
166
167 return wire;
168 }
169
170 // helper class for converting AST always nodes to RTLIL processes
171 struct AST_INTERNAL::ProcessGenerator
172 {
173 // input and output structures
174 AstNode *always;
175 RTLIL::SigSpec initSyncSignals;
176 RTLIL::Process *proc;
177 RTLIL::SigSpec outputSignals;
178
179 // This always points to the RTLIL::CaseRule being filled at the moment
180 RTLIL::CaseRule *current_case;
181
182 // This map contains the replacement pattern to be used in the right hand side
183 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
184 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
185 // the value assigned in the first assignment. So when the first assignment is processed
186 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
187 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
188
189 // This map contains the replacement pattern to be used in the left hand side
190 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
191 // should not be connected to the signal foo. Instead it must be connected to the temporary
192 // signal that is used as input for the register that drives the signal foo.
193 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
194
195 // The code here generates a number of temporary signal for each output register. This
196 // map helps generating nice numbered names for all this temporary signals.
197 std::map<RTLIL::Wire*, int> new_temp_count;
198
199 // Buffer for generating the init action
200 RTLIL::SigSpec init_lvalue, init_rvalue;
201
202 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
203 {
204 // generate process and simple root case
205 proc = new RTLIL::Process;
206 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
207 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
208 for (auto &attr : always->attributes) {
209 if (attr.second->type != AST_CONSTANT)
210 log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
211 attr.first.c_str());
212 proc->attributes[attr.first] = attr.second->asAttrConst();
213 }
214 current_module->processes[proc->name] = proc;
215 current_case = &proc->root_case;
216
217 // create initial temporary signal for all output registers
218 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
219 collect_lvalues(subst_lvalue_from, always, true, true);
220 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
221 subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
222
223 bool found_global_syncs = false;
224 bool found_anyedge_syncs = false;
225 for (auto child : always->children)
226 {
227 if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
228 child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
229 found_global_syncs = true;
230 }
231 if (child->type == AST_EDGE) {
232 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock")
233 found_global_syncs = true;
234 else
235 found_anyedge_syncs = true;
236 }
237 }
238
239 if (found_anyedge_syncs) {
240 if (found_global_syncs)
241 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
242 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
243 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
244 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
245 }
246
247 // create syncs for the process
248 bool found_clocked_sync = false;
249 for (auto child : always->children)
250 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
251 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
252 child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
253 continue;
254 found_clocked_sync = true;
255 if (found_global_syncs || found_anyedge_syncs)
256 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
257 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
258 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
259 syncrule->signal = child->children[0]->genRTLIL();
260 if (GetSize(syncrule->signal) != 1)
261 log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
262 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
263 proc->syncs.push_back(syncrule);
264 }
265 if (proc->syncs.empty()) {
266 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
267 syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
268 syncrule->signal = RTLIL::SigSpec();
269 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
270 proc->syncs.push_back(syncrule);
271 }
272
273 // create initial assignments for the temporary signals
274 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
275 subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
276 } else {
277 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
278 }
279
280 // process the AST
281 for (auto child : always->children)
282 if (child->type == AST_BLOCK)
283 processAst(child);
284
285 if (initSyncSignals.size() > 0)
286 {
287 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
288 sync->type = RTLIL::SyncType::STi;
289 proc->syncs.push_back(sync);
290
291 log_assert(init_lvalue.size() == init_rvalue.size());
292
293 int offset = 0;
294 for (auto &init_lvalue_c : init_lvalue.chunks()) {
295 RTLIL::SigSpec lhs = init_lvalue_c;
296 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
297 remove_unwanted_lvalue_bits(lhs, rhs);
298 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
299 offset += lhs.size();
300 }
301 }
302
303 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
304 }
305
306 void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
307 {
308 RTLIL::SigSpec new_lhs, new_rhs;
309
310 log_assert(GetSize(lhs) == GetSize(rhs));
311 for (int i = 0; i < GetSize(lhs); i++) {
312 if (lhs[i].wire == nullptr)
313 continue;
314 new_lhs.append(lhs[i]);
315 new_rhs.append(rhs[i]);
316 }
317
318 lhs = new_lhs;
319 rhs = new_rhs;
320 }
321
322 // create new temporary signals
323 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
324 {
325 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
326
327 for (int i = 0; i < GetSize(chunks); i++)
328 {
329 RTLIL::SigChunk &chunk = chunks[i];
330 if (chunk.wire == NULL)
331 continue;
332
333 std::string wire_name;
334 do {
335 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
336 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
337 if (chunk.wire->name.str().find('$') != std::string::npos)
338 wire_name += stringf("$%d", autoidx++);
339 } while (current_module->wires_.count(wire_name) > 0);
340
341 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
342 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
343
344 chunk.wire = wire;
345 chunk.offset = 0;
346 }
347
348 return chunks;
349 }
350
351 // recursively traverse the AST an collect all assigned signals
352 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
353 {
354 switch (ast->type)
355 {
356 case AST_CASE:
357 for (auto child : ast->children)
358 if (child != ast->children[0]) {
359 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
360 collect_lvalues(reg, child, type_eq, type_le, false);
361 }
362 break;
363
364 case AST_COND:
365 case AST_CONDX:
366 case AST_CONDZ:
367 case AST_ALWAYS:
368 case AST_INITIAL:
369 for (auto child : ast->children)
370 if (child->type == AST_BLOCK)
371 collect_lvalues(reg, child, type_eq, type_le, false);
372 break;
373
374 case AST_BLOCK:
375 for (auto child : ast->children) {
376 if (child->type == AST_ASSIGN_EQ && type_eq)
377 reg.append(child->children[0]->genRTLIL());
378 if (child->type == AST_ASSIGN_LE && type_le)
379 reg.append(child->children[0]->genRTLIL());
380 if (child->type == AST_CASE || child->type == AST_BLOCK)
381 collect_lvalues(reg, child, type_eq, type_le, false);
382 }
383 break;
384
385 default:
386 log_abort();
387 }
388
389 if (run_sort_and_unify) {
390 std::set<RTLIL::SigBit> sorted_reg;
391 for (auto bit : reg)
392 if (bit.wire)
393 sorted_reg.insert(bit);
394 reg = RTLIL::SigSpec(sorted_reg);
395 }
396 }
397
398 // remove all assignments to the given signal pattern in a case and all its children.
399 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
400 // function is called to clean up the first two assignments as they are overwritten by
401 // the third assignment.
402 void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
403 {
404 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
405 it->first.remove2(pattern, &it->second);
406
407 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
408 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
409 removeSignalFromCaseTree(pattern, *it2);
410 }
411
412 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
413 // are avoided and the generated $mux cells have a more "natural" size.
414 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
415 {
416 if (inSyncRule && initSyncSignals.size() > 0) {
417 init_lvalue.append(lvalue.extract(initSyncSignals));
418 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
419 lvalue.remove2(initSyncSignals, &rvalue);
420 }
421 log_assert(lvalue.size() == rvalue.size());
422
423 int offset = 0;
424 for (auto &lvalue_c : lvalue.chunks()) {
425 RTLIL::SigSpec lhs = lvalue_c;
426 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
427 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
428 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
429 remove_unwanted_lvalue_bits(lhs, rhs);
430 actions.push_back(RTLIL::SigSig(lhs, rhs));
431 offset += lhs.size();
432 }
433 }
434
435 // recursively process the AST and fill the RTLIL::Process
436 void processAst(AstNode *ast)
437 {
438 switch (ast->type)
439 {
440 case AST_BLOCK:
441 for (auto child : ast->children)
442 processAst(child);
443 break;
444
445 case AST_ASSIGN_EQ:
446 case AST_ASSIGN_LE:
447 {
448 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
449 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
450
451 pool<SigBit> lvalue_sigbits;
452 for (int i = 0; i < GetSize(lvalue); i++) {
453 if (lvalue_sigbits.count(lvalue[i]) > 0) {
454 unmapped_lvalue.remove(i);
455 lvalue.remove(i);
456 rvalue.remove(i--);
457 } else
458 lvalue_sigbits.insert(lvalue[i]);
459 }
460
461 lvalue.replace(subst_lvalue_map.stdmap());
462
463 if (ast->type == AST_ASSIGN_EQ) {
464 for (int i = 0; i < GetSize(unmapped_lvalue); i++)
465 subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
466 }
467
468 removeSignalFromCaseTree(lvalue, current_case);
469 remove_unwanted_lvalue_bits(lvalue, rvalue);
470 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
471 }
472 break;
473
474 case AST_CASE:
475 {
476 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
477 sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
478 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
479 current_case->switches.push_back(sw);
480
481 for (auto &attr : ast->attributes) {
482 if (attr.second->type != AST_CONSTANT)
483 log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
484 attr.first.c_str());
485 sw->attributes[attr.first] = attr.second->asAttrConst();
486 }
487
488 RTLIL::SigSpec this_case_eq_lvalue;
489 collect_lvalues(this_case_eq_lvalue, ast, true, false);
490
491 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
492
493 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
494 this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
495
496 RTLIL::CaseRule *default_case = NULL;
497 RTLIL::CaseRule *last_generated_case = NULL;
498 for (auto child : ast->children)
499 {
500 if (child == ast->children[0])
501 continue;
502 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
503
504 subst_lvalue_map.save();
505 subst_rvalue_map.save();
506
507 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
508 subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
509
510 RTLIL::CaseRule *backup_case = current_case;
511 current_case = new RTLIL::CaseRule;
512 last_generated_case = current_case;
513 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
514 for (auto node : child->children) {
515 if (node->type == AST_DEFAULT)
516 default_case = current_case;
517 else if (node->type == AST_BLOCK)
518 processAst(node);
519 else
520 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
521 }
522 if (default_case != current_case)
523 sw->cases.push_back(current_case);
524 else
525 log_assert(current_case->compare.size() == 0);
526 current_case = backup_case;
527
528 subst_lvalue_map.restore();
529 subst_rvalue_map.restore();
530 }
531
532 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
533 last_generated_case->compare.clear();
534 } else {
535 if (default_case == NULL) {
536 default_case = new RTLIL::CaseRule;
537 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
538 }
539 sw->cases.push_back(default_case);
540 }
541
542 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
543 subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
544
545 this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
546 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
547 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
548 }
549 break;
550
551 case AST_WIRE:
552 log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
553 break;
554
555 case AST_PARAMETER:
556 case AST_LOCALPARAM:
557 log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
558 break;
559
560 case AST_NONE:
561 case AST_TCALL:
562 case AST_FOR:
563 break;
564
565 default:
566 // ast->dumpAst(NULL, "ast> ");
567 // current_ast_mod->dumpAst(NULL, "mod> ");
568 log_abort();
569 }
570 }
571 };
572
573 // detect sign and width of an expression
574 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
575 {
576 std::string type_name;
577 bool sub_sign_hint = true;
578 int sub_width_hint = -1;
579 int this_width = 0;
580 AstNode *range = NULL;
581 AstNode *id_ast = NULL;
582
583 bool local_found_real = false;
584 if (found_real == NULL)
585 found_real = &local_found_real;
586
587 switch (type)
588 {
589 case AST_CONSTANT:
590 width_hint = max(width_hint, int(bits.size()));
591 if (!is_signed)
592 sign_hint = false;
593 break;
594
595 case AST_REALVALUE:
596 *found_real = true;
597 width_hint = max(width_hint, 32);
598 break;
599
600 case AST_IDENTIFIER:
601 id_ast = id2ast;
602 if (id_ast == NULL && current_scope.count(str))
603 id_ast = current_scope.at(str);
604 if (!id_ast)
605 log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
606 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
607 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
608 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
609 } else
610 if (id_ast->children[0]->type != AST_CONSTANT)
611 while (id_ast->simplify(true, false, false, 1, -1, false, true)) { }
612 if (id_ast->children[0]->type == AST_CONSTANT)
613 this_width = id_ast->children[0]->bits.size();
614 else
615 log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
616 if (children.size() != 0)
617 range = children[0];
618 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
619 if (!id_ast->range_valid) {
620 if (id_ast->type == AST_AUTOWIRE)
621 this_width = 1;
622 else {
623 // current_ast_mod->dumpAst(NULL, "mod> ");
624 // log("---\n");
625 // id_ast->dumpAst(NULL, "decl> ");
626 // dumpAst(NULL, "ref> ");
627 log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
628 }
629 } else {
630 this_width = id_ast->range_left - id_ast->range_right + 1;
631 if (children.size() != 0)
632 range = children[0];
633 }
634 } else if (id_ast->type == AST_GENVAR) {
635 this_width = 32;
636 } else if (id_ast->type == AST_MEMORY) {
637 if (!id_ast->children[0]->range_valid)
638 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
639 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
640 } else
641 log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
642 if (range) {
643 if (range->children.size() == 1)
644 this_width = 1;
645 else if (!range->range_valid) {
646 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
647 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
648 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
649 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
650 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
651 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
652 str.c_str());
653 this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
654 delete left_at_zero_ast;
655 delete right_at_zero_ast;
656 } else
657 this_width = range->range_left - range->range_right + 1;
658 sign_hint = false;
659 }
660 width_hint = max(width_hint, this_width);
661 if (!id_ast->is_signed)
662 sign_hint = false;
663 break;
664
665 case AST_TO_BITS:
666 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
667 if (children[0]->type != AST_CONSTANT)
668 log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
669 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
670 width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
671 break;
672
673 case AST_TO_SIGNED:
674 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
675 break;
676
677 case AST_TO_UNSIGNED:
678 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
679 sign_hint = false;
680 break;
681
682 case AST_CONCAT:
683 for (auto child : children) {
684 sub_width_hint = 0;
685 sub_sign_hint = true;
686 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
687 this_width += sub_width_hint;
688 }
689 width_hint = max(width_hint, this_width);
690 sign_hint = false;
691 break;
692
693 case AST_REPLICATE:
694 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
695 if (children[0]->type != AST_CONSTANT)
696 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
697 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
698 width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
699 sign_hint = false;
700 break;
701
702 case AST_NEG:
703 case AST_BIT_NOT:
704 case AST_POS:
705 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
706 break;
707
708 case AST_BIT_AND:
709 case AST_BIT_OR:
710 case AST_BIT_XOR:
711 case AST_BIT_XNOR:
712 for (auto child : children)
713 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
714 break;
715
716 case AST_REDUCE_AND:
717 case AST_REDUCE_OR:
718 case AST_REDUCE_XOR:
719 case AST_REDUCE_XNOR:
720 case AST_REDUCE_BOOL:
721 width_hint = max(width_hint, 1);
722 sign_hint = false;
723 break;
724
725 case AST_SHIFT_LEFT:
726 case AST_SHIFT_RIGHT:
727 case AST_SHIFT_SLEFT:
728 case AST_SHIFT_SRIGHT:
729 case AST_POW:
730 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
731 break;
732
733 case AST_LT:
734 case AST_LE:
735 case AST_EQ:
736 case AST_NE:
737 case AST_EQX:
738 case AST_NEX:
739 case AST_GE:
740 case AST_GT:
741 width_hint = max(width_hint, 1);
742 sign_hint = false;
743 break;
744
745 case AST_ADD:
746 case AST_SUB:
747 case AST_MUL:
748 case AST_DIV:
749 case AST_MOD:
750 for (auto child : children)
751 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
752 break;
753
754 case AST_LOGIC_AND:
755 case AST_LOGIC_OR:
756 case AST_LOGIC_NOT:
757 width_hint = max(width_hint, 1);
758 sign_hint = false;
759 break;
760
761 case AST_TERNARY:
762 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
763 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
764 break;
765
766 case AST_MEMRD:
767 if (!id2ast->is_signed)
768 sign_hint = false;
769 if (!id2ast->children[0]->range_valid)
770 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
771 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
772 width_hint = max(width_hint, this_width);
773 break;
774
775 case AST_FCALL:
776 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
777 if (GetSize(children) == 1) {
778 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
779 if (children[0]->type != AST_CONSTANT)
780 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
781 RTLIL::unescape_id(str).c_str());
782 width_hint = max(width_hint, int(children[0]->asInt(true)));
783 }
784 break;
785 }
786 if (str == "\\$past") {
787 if (GetSize(children) > 0) {
788 sub_width_hint = 0;
789 sub_sign_hint = true;
790 children.at(0)->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
791 width_hint = max(width_hint, sub_width_hint);
792 sign_hint = false;
793 }
794 break;
795 }
796 /* fall through */
797
798 // everything should have been handled above -> print error if not.
799 default:
800 for (auto f : log_files)
801 current_ast->dumpAst(f, "verilog-ast> ");
802 log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n",
803 type2str(type).c_str());
804 }
805
806 if (*found_real)
807 sign_hint = true;
808 }
809
810 // detect sign and width of an expression
811 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
812 {
813 width_hint = -1;
814 sign_hint = true;
815 if (found_real)
816 *found_real = false;
817 detectSignWidthWorker(width_hint, sign_hint, found_real);
818 }
819
820 // create RTLIL from an AST node
821 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
822 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
823 //
824 // note that this function is influenced by a number of global variables that might be set when
825 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
826 // larger expressions into a netlist of cells.
827 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
828 {
829 // in the following big switch() statement there are some uses of
830 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
831 // cases this variable is used to hold the type of the cell that should
832 // be instantiated for this type of AST node.
833 std::string type_name;
834
835 current_filename = filename;
836 set_line_num(linenum);
837
838 switch (type)
839 {
840 // simply ignore this nodes.
841 // they are either leftovers from simplify() or are referenced by other nodes
842 // and are only accessed here thru this references
843 case AST_NONE:
844 case AST_TASK:
845 case AST_FUNCTION:
846 case AST_DPI_FUNCTION:
847 case AST_AUTOWIRE:
848 case AST_LOCALPARAM:
849 case AST_DEFPARAM:
850 case AST_GENVAR:
851 case AST_GENFOR:
852 case AST_GENBLOCK:
853 case AST_GENIF:
854 case AST_GENCASE:
855 case AST_PACKAGE:
856 case AST_MODPORT:
857 case AST_MODPORTMEMBER:
858 break;
859 case AST_INTERFACEPORT: {
860 // If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
861 // This is used by the hierarchy pass to know when it can replace interface connection with the individual
862 // signals.
863 RTLIL::Wire *wire = current_module->addWire(str, 1);
864 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
865 wire->start_offset = 0;
866 wire->port_id = port_id;
867 wire->port_input = true;
868 wire->port_output = true;
869 wire->set_bool_attribute("\\is_interface");
870 if (children.size() > 0) {
871 for(size_t i=0; i<children.size();i++) {
872 if(children[i]->type == AST_INTERFACEPORTTYPE) {
873 std::string name_type = children[i]->str;
874 size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
875 // Separate the interface instance name from any modports:
876 if (ndots == 0) { // Does not have modport
877 wire->attributes["\\interface_type"] = name_type;
878 }
879 else {
880 std::stringstream name_type_stream(name_type);
881 std::string segment;
882 std::vector<std::string> seglist;
883 while(std::getline(name_type_stream, segment, '.')) {
884 seglist.push_back(segment);
885 }
886 if (ndots == 1) { // Has modport
887 wire->attributes["\\interface_type"] = seglist[0];
888 wire->attributes["\\interface_modport"] = seglist[1];
889 }
890 else { // Erroneous port type
891 log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
892 }
893 }
894 break;
895 }
896 }
897 }
898 wire->upto = 0;
899 }
900 break;
901 case AST_INTERFACEPORTTYPE:
902 break;
903
904 // remember the parameter, needed for example in techmap
905 case AST_PARAMETER:
906 current_module->avail_parameters.insert(str);
907 break;
908
909 // create an RTLIL::Wire for an AST_WIRE node
910 case AST_WIRE: {
911 if (current_module->wires_.count(str) != 0)
912 log_file_error(filename, linenum, "Re-definition of signal `%s'!\n",
913 str.c_str());
914 if (!range_valid)
915 log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n",
916 str.c_str());
917
918 log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
919
920 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
921 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
922 wire->start_offset = range_right;
923 wire->port_id = port_id;
924 wire->port_input = is_input;
925 wire->port_output = is_output;
926 wire->upto = range_swapped;
927
928 for (auto &attr : attributes) {
929 if (attr.second->type != AST_CONSTANT)
930 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
931 attr.first.c_str());
932 wire->attributes[attr.first] = attr.second->asAttrConst();
933 }
934 }
935 break;
936
937 // create an RTLIL::Memory for an AST_MEMORY node
938 case AST_MEMORY: {
939 if (current_module->memories.count(str) != 0)
940 log_file_error(filename, linenum, "Re-definition of memory `%s'!\n",
941 str.c_str());
942
943 log_assert(children.size() >= 2);
944 log_assert(children[0]->type == AST_RANGE);
945 log_assert(children[1]->type == AST_RANGE);
946
947 if (!children[0]->range_valid || !children[1]->range_valid)
948 log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n",
949 str.c_str());
950
951 RTLIL::Memory *memory = new RTLIL::Memory;
952 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
953 memory->name = str;
954 memory->width = children[0]->range_left - children[0]->range_right + 1;
955 if (children[1]->range_right < children[1]->range_left) {
956 memory->start_offset = children[1]->range_right;
957 memory->size = children[1]->range_left - children[1]->range_right + 1;
958 } else {
959 memory->start_offset = children[1]->range_left;
960 memory->size = children[1]->range_right - children[1]->range_left + 1;
961 }
962 current_module->memories[memory->name] = memory;
963
964 for (auto &attr : attributes) {
965 if (attr.second->type != AST_CONSTANT)
966 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
967 attr.first.c_str());
968 memory->attributes[attr.first] = attr.second->asAttrConst();
969 }
970 }
971 break;
972
973 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
974 case AST_CONSTANT:
975 {
976 if (width_hint < 0)
977 detectSignWidth(width_hint, sign_hint);
978
979 is_signed = sign_hint;
980 return RTLIL::SigSpec(bitsAsConst());
981 }
982
983 case AST_REALVALUE:
984 {
985 RTLIL::SigSpec sig = realAsConst(width_hint);
986 log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
987 realvalue, log_signal(sig));
988 return sig;
989 }
990
991 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
992 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
993 // shifter cell is created and the output signal of this cell is returned
994 case AST_IDENTIFIER:
995 {
996 RTLIL::Wire *wire = NULL;
997 RTLIL::SigChunk chunk;
998 bool is_interface = false;
999
1000 int add_undef_bits_msb = 0;
1001 int add_undef_bits_lsb = 0;
1002
1003 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
1004 RTLIL::Wire *wire = current_module->addWire(str);
1005 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1006 wire->name = str;
1007 if (flag_autowire)
1008 log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
1009 else
1010 log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
1011 }
1012 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
1013 if (id2ast->children[0]->type != AST_CONSTANT)
1014 log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n",
1015 str.c_str());
1016 chunk = RTLIL::Const(id2ast->children[0]->bits);
1017 goto use_const_chunk;
1018 }
1019 else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
1020 RTLIL::Wire *current_wire = current_module->wire(str);
1021 if (current_wire->get_bool_attribute("\\is_interface"))
1022 is_interface = true;
1023 // Ignore
1024 }
1025 // If an identifier is found that is not already known, assume that it is an interface:
1026 else if (1) { // FIXME: Check if sv_mode first?
1027 is_interface = true;
1028 }
1029 else {
1030 log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
1031 str.c_str());
1032 }
1033
1034 if (id2ast->type == AST_MEMORY)
1035 log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
1036 str.c_str());
1037
1038 // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
1039 // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
1040 // with the individual signals:
1041 if (is_interface) {
1042 RTLIL::Wire *dummy_wire;
1043 std::string dummy_wire_name = "$dummywireforinterface" + str;
1044 if (current_module->wires_.count(dummy_wire_name))
1045 dummy_wire = current_module->wires_[dummy_wire_name];
1046 else {
1047 dummy_wire = current_module->addWire(dummy_wire_name);
1048 dummy_wire->set_bool_attribute("\\is_interface");
1049 }
1050 RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
1051 return tmp;
1052 }
1053
1054 wire = current_module->wires_[str];
1055 chunk.wire = wire;
1056 chunk.width = wire->width;
1057 chunk.offset = 0;
1058
1059 use_const_chunk:
1060 if (children.size() != 0) {
1061 if (children[0]->type != AST_RANGE)
1062 log_file_error(filename, linenum, "Single range expected.\n");
1063 int source_width = id2ast->range_left - id2ast->range_right + 1;
1064 int source_offset = id2ast->range_right;
1065 if (!children[0]->range_valid) {
1066 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
1067 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
1068 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1069 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1070 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
1071 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
1072 str.c_str());
1073 int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
1074 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
1075 children[0]->children[1]->clone() : children[0]->children[0]->clone());
1076 fake_ast->children[0]->delete_children();
1077 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
1078 if (id2ast->range_right != 0) {
1079 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
1080 fake_ast->children[1]->is_signed = true;
1081 }
1082 if (id2ast->range_swapped) {
1083 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
1084 fake_ast->children[1]->is_signed = true;
1085 }
1086 if (GetSize(shift_val) >= 32)
1087 fake_ast->children[1]->is_signed = true;
1088 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
1089 delete left_at_zero_ast;
1090 delete right_at_zero_ast;
1091 delete fake_ast;
1092 return sig;
1093 } else {
1094 chunk.width = children[0]->range_left - children[0]->range_right + 1;
1095 chunk.offset = children[0]->range_right - source_offset;
1096 if (id2ast->range_swapped)
1097 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
1098 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
1099 if (chunk.width == 1)
1100 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
1101 str.c_str());
1102 else
1103 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n",
1104 str.c_str(), chunk.width);
1105 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
1106 } else {
1107 if (chunk.width + chunk.offset > source_width) {
1108 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
1109 chunk.width -= add_undef_bits_msb;
1110 }
1111 if (chunk.offset < 0) {
1112 add_undef_bits_lsb = -chunk.offset;
1113 chunk.width -= add_undef_bits_lsb;
1114 chunk.offset += add_undef_bits_lsb;
1115 }
1116 if (add_undef_bits_lsb)
1117 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
1118 str.c_str(), add_undef_bits_lsb);
1119 if (add_undef_bits_msb)
1120 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
1121 str.c_str(), add_undef_bits_msb);
1122 }
1123 }
1124 }
1125
1126 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
1127
1128 if (genRTLIL_subst_ptr)
1129 sig.replace(*genRTLIL_subst_ptr);
1130
1131 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
1132 return sig;
1133 }
1134
1135 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
1136 case AST_TO_SIGNED:
1137 case AST_TO_UNSIGNED: {
1138 RTLIL::SigSpec sig = children[0]->genRTLIL();
1139 if (sig.size() < width_hint)
1140 sig.extend_u0(width_hint, sign_hint);
1141 is_signed = sign_hint;
1142 return sig;
1143 }
1144
1145 // concatenation of signals can be done directly using RTLIL::SigSpec
1146 case AST_CONCAT: {
1147 RTLIL::SigSpec sig;
1148 for (auto it = children.begin(); it != children.end(); it++)
1149 sig.append((*it)->genRTLIL());
1150 if (sig.size() < width_hint)
1151 sig.extend_u0(width_hint, false);
1152 return sig;
1153 }
1154
1155 // replication of signals can be done directly using RTLIL::SigSpec
1156 case AST_REPLICATE: {
1157 RTLIL::SigSpec left = children[0]->genRTLIL();
1158 RTLIL::SigSpec right = children[1]->genRTLIL();
1159 if (!left.is_fully_const())
1160 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
1161 int count = left.as_int();
1162 RTLIL::SigSpec sig;
1163 for (int i = 0; i < count; i++)
1164 sig.append(right);
1165 if (sig.size() < width_hint)
1166 sig.extend_u0(width_hint, false);
1167 is_signed = false;
1168 return sig;
1169 }
1170
1171 // generate cells for unary operations: $not, $pos, $neg
1172 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1173 if (0) { case AST_POS: type_name = "$pos"; }
1174 if (0) { case AST_NEG: type_name = "$neg"; }
1175 {
1176 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1177 is_signed = children[0]->is_signed;
1178 int width = arg.size();
1179 if (width_hint > 0) {
1180 width = width_hint;
1181 widthExtend(this, arg, width, is_signed);
1182 }
1183 return uniop2rtlil(this, type_name, width, arg);
1184 }
1185
1186 // generate cells for binary operations: $and, $or, $xor, $xnor
1187 if (0) { case AST_BIT_AND: type_name = "$and"; }
1188 if (0) { case AST_BIT_OR: type_name = "$or"; }
1189 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1190 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1191 {
1192 if (width_hint < 0)
1193 detectSignWidth(width_hint, sign_hint);
1194 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1195 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1196 int width = max(left.size(), right.size());
1197 if (width_hint > 0)
1198 width = width_hint;
1199 is_signed = children[0]->is_signed && children[1]->is_signed;
1200 return binop2rtlil(this, type_name, width, left, right);
1201 }
1202
1203 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1204 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1205 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1206 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1207 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1208 {
1209 RTLIL::SigSpec arg = children[0]->genRTLIL();
1210 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
1211 return sig;
1212 }
1213
1214 // generate cells for unary operations: $reduce_bool
1215 // (this is actually just an $reduce_or, but for clarity a different cell type is used)
1216 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1217 {
1218 RTLIL::SigSpec arg = children[0]->genRTLIL();
1219 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
1220 return sig;
1221 }
1222
1223 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1224 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1225 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1226 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1227 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1228 {
1229 if (width_hint < 0)
1230 detectSignWidth(width_hint, sign_hint);
1231 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1232 RTLIL::SigSpec right = children[1]->genRTLIL();
1233 int width = width_hint > 0 ? width_hint : left.size();
1234 is_signed = children[0]->is_signed;
1235 return binop2rtlil(this, type_name, width, left, right);
1236 }
1237
1238 // generate cells for binary operations: $pow
1239 case AST_POW:
1240 {
1241 int right_width;
1242 bool right_signed;
1243 children[1]->detectSignWidth(right_width, right_signed);
1244 if (width_hint < 0)
1245 detectSignWidth(width_hint, sign_hint);
1246 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1247 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1248 int width = width_hint > 0 ? width_hint : left.size();
1249 is_signed = children[0]->is_signed;
1250 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1251 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1252 return binop2rtlil(this, "$pow", width, left, right);
1253 }
1254
1255 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1256 if (0) { case AST_LT: type_name = "$lt"; }
1257 if (0) { case AST_LE: type_name = "$le"; }
1258 if (0) { case AST_EQ: type_name = "$eq"; }
1259 if (0) { case AST_NE: type_name = "$ne"; }
1260 if (0) { case AST_EQX: type_name = "$eqx"; }
1261 if (0) { case AST_NEX: type_name = "$nex"; }
1262 if (0) { case AST_GE: type_name = "$ge"; }
1263 if (0) { case AST_GT: type_name = "$gt"; }
1264 {
1265 int width = max(width_hint, 1);
1266 width_hint = -1, sign_hint = true;
1267 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1268 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1269 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1270 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1271 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1272 return sig;
1273 }
1274
1275 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1276 if (0) { case AST_ADD: type_name = "$add"; }
1277 if (0) { case AST_SUB: type_name = "$sub"; }
1278 if (0) { case AST_MUL: type_name = "$mul"; }
1279 if (0) { case AST_DIV: type_name = "$div"; }
1280 if (0) { case AST_MOD: type_name = "$mod"; }
1281 {
1282 if (width_hint < 0)
1283 detectSignWidth(width_hint, sign_hint);
1284 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1285 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1286 #if 0
1287 int width = max(left.size(), right.size());
1288 if (width > width_hint && width_hint > 0)
1289 width = width_hint;
1290 if (width < width_hint) {
1291 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1292 width++;
1293 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1294 width = width_hint;
1295 if (type == AST_MUL)
1296 width = min(left.size() + right.size(), width_hint);
1297 }
1298 #else
1299 int width = max(max(left.size(), right.size()), width_hint);
1300 #endif
1301 is_signed = children[0]->is_signed && children[1]->is_signed;
1302 return binop2rtlil(this, type_name, width, left, right);
1303 }
1304
1305 // generate cells for binary operations: $logic_and, $logic_or
1306 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1307 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1308 {
1309 RTLIL::SigSpec left = children[0]->genRTLIL();
1310 RTLIL::SigSpec right = children[1]->genRTLIL();
1311 return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
1312 }
1313
1314 // generate cells for unary operations: $logic_not
1315 case AST_LOGIC_NOT:
1316 {
1317 RTLIL::SigSpec arg = children[0]->genRTLIL();
1318 return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
1319 }
1320
1321 // generate multiplexer for ternary operator (aka ?:-operator)
1322 case AST_TERNARY:
1323 {
1324 if (width_hint < 0)
1325 detectSignWidth(width_hint, sign_hint);
1326
1327 RTLIL::SigSpec cond = children[0]->genRTLIL();
1328 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1329 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1330
1331 if (cond.size() > 1)
1332 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1333
1334 int width = max(val1.size(), val2.size());
1335 is_signed = children[1]->is_signed && children[2]->is_signed;
1336 widthExtend(this, val1, width, is_signed);
1337 widthExtend(this, val2, width, is_signed);
1338
1339 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1340
1341 if (sig.size() < width_hint)
1342 sig.extend_u0(width_hint, sign_hint);
1343 return sig;
1344 }
1345
1346 // generate $memrd cells for memory read ports
1347 case AST_MEMRD:
1348 {
1349 std::stringstream sstr;
1350 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1351
1352 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1353 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1354
1355 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1356 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1357
1358 int mem_width, mem_size, addr_bits;
1359 is_signed = id2ast->is_signed;
1360 id2ast->meminfo(mem_width, mem_size, addr_bits);
1361
1362 RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
1363
1364 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1365 cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1366 cell->setPort("\\ADDR", addr_sig);
1367 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1368
1369 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1370 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1371 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1372
1373 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1374 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1375 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1376
1377 if (!sign_hint)
1378 is_signed = false;
1379
1380 return RTLIL::SigSpec(wire);
1381 }
1382
1383 // generate $memwr cells for memory write ports
1384 case AST_MEMWR:
1385 case AST_MEMINIT:
1386 {
1387 std::stringstream sstr;
1388 sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1389
1390 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
1391 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1392
1393 int mem_width, mem_size, addr_bits;
1394 id2ast->meminfo(mem_width, mem_size, addr_bits);
1395
1396 int num_words = 1;
1397 if (type == AST_MEMINIT) {
1398 if (children[2]->type != AST_CONSTANT)
1399 log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
1400 num_words = int(children[2]->asInt(false));
1401 cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
1402 }
1403
1404 SigSpec addr_sig = children[0]->genRTLIL();
1405
1406 cell->setPort("\\ADDR", addr_sig);
1407 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
1408
1409 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1410 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1411 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1412
1413 if (type == AST_MEMWR) {
1414 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1415 cell->setPort("\\EN", children[2]->genRTLIL());
1416 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1417 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1418 }
1419
1420 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1421 }
1422 break;
1423
1424 // generate $assert cells
1425 case AST_ASSERT:
1426 case AST_ASSUME:
1427 case AST_LIVE:
1428 case AST_FAIR:
1429 case AST_COVER:
1430 {
1431 const char *celltype = nullptr;
1432 if (type == AST_ASSERT) celltype = "$assert";
1433 if (type == AST_ASSUME) celltype = "$assume";
1434 if (type == AST_LIVE) celltype = "$live";
1435 if (type == AST_FAIR) celltype = "$fair";
1436 if (type == AST_COVER) celltype = "$cover";
1437
1438 log_assert(children.size() == 2);
1439
1440 RTLIL::SigSpec check = children[0]->genRTLIL();
1441 if (GetSize(check) != 1)
1442 check = current_module->ReduceBool(NEW_ID, check);
1443
1444 RTLIL::SigSpec en = children[1]->genRTLIL();
1445 if (GetSize(en) != 1)
1446 en = current_module->ReduceBool(NEW_ID, en);
1447
1448 std::stringstream sstr;
1449 sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
1450
1451 RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
1452 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1453
1454 for (auto &attr : attributes) {
1455 if (attr.second->type != AST_CONSTANT)
1456 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
1457 attr.first.c_str());
1458 cell->attributes[attr.first] = attr.second->asAttrConst();
1459 }
1460
1461 cell->setPort("\\A", check);
1462 cell->setPort("\\EN", en);
1463 }
1464 break;
1465
1466 // add entries to current_module->connections for assignments (outside of always blocks)
1467 case AST_ASSIGN:
1468 {
1469 RTLIL::SigSpec left = children[0]->genRTLIL();
1470 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1471 if (left.has_const()) {
1472 RTLIL::SigSpec new_left, new_right;
1473 for (int i = 0; i < GetSize(left); i++)
1474 if (left[i].wire) {
1475 new_left.append(left[i]);
1476 new_right.append(right[i]);
1477 }
1478 log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
1479 " old assignment: %s = %s\n new assignment: %s = %s.\n",
1480 log_signal(left), log_signal(right),
1481 log_signal(new_left), log_signal(new_right));
1482 left = new_left;
1483 right = new_right;
1484 }
1485 current_module->connect(RTLIL::SigSig(left, right));
1486 }
1487 break;
1488
1489 // create an RTLIL::Cell for an AST_CELL
1490 case AST_CELL:
1491 {
1492 int port_counter = 0, para_counter = 0;
1493
1494 if (current_module->count_id(str) != 0)
1495 log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
1496
1497 RTLIL::Cell *cell = current_module->addCell(str, "");
1498 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1499 // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
1500 cell->set_bool_attribute("\\module_not_derived");
1501
1502 for (auto it = children.begin(); it != children.end(); it++) {
1503 AstNode *child = *it;
1504 if (child->type == AST_CELLTYPE) {
1505 cell->type = child->str;
1506 if (flag_icells && cell->type.substr(0, 2) == "\\$")
1507 cell->type = cell->type.substr(1);
1508 continue;
1509 }
1510 if (child->type == AST_PARASET) {
1511 IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
1512 if (child->children[0]->type == AST_REALVALUE) {
1513 log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
1514 log_id(cell), log_id(paraname), child->children[0]->realvalue);
1515 auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
1516 strnode->cloneInto(child->children[0]);
1517 delete strnode;
1518 }
1519 if (child->children[0]->type != AST_CONSTANT)
1520 log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
1521 log_id(cell), log_id(paraname));
1522 cell->parameters[paraname] = child->children[0]->asParaConst();
1523 continue;
1524 }
1525 if (child->type == AST_ARGUMENT) {
1526 RTLIL::SigSpec sig;
1527 if (child->children.size() > 0)
1528 sig = child->children[0]->genRTLIL();
1529 if (child->str.size() == 0) {
1530 char buf[100];
1531 snprintf(buf, 100, "$%d", ++port_counter);
1532 cell->setPort(buf, sig);
1533 } else {
1534 cell->setPort(child->str, sig);
1535 }
1536 continue;
1537 }
1538 log_abort();
1539 }
1540 for (auto &attr : attributes) {
1541 if (attr.second->type != AST_CONSTANT)
1542 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
1543 attr.first.c_str());
1544 cell->attributes[attr.first] = attr.second->asAttrConst();
1545 }
1546 }
1547 break;
1548
1549 // use ProcessGenerator for always blocks
1550 case AST_ALWAYS: {
1551 AstNode *always = this->clone();
1552 ProcessGenerator generator(always);
1553 ignoreThisSignalsInInitial.append(generator.outputSignals);
1554 delete always;
1555 } break;
1556
1557 case AST_INITIAL: {
1558 AstNode *always = this->clone();
1559 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1560 delete always;
1561 } break;
1562
1563 case AST_FCALL: {
1564 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
1565 {
1566 string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
1567 int width = width_hint;
1568
1569 if (GetSize(children) > 1)
1570 log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
1571 RTLIL::unescape_id(str).c_str(), GetSize(children));
1572
1573 if (GetSize(children) == 1) {
1574 if (children[0]->type != AST_CONSTANT)
1575 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
1576 RTLIL::unescape_id(str).c_str());
1577 width = children[0]->asInt(true);
1578 }
1579
1580 if (width <= 0)
1581 log_file_error(filename, linenum, "Failed to detect width of %s!\n",
1582 RTLIL::unescape_id(str).c_str());
1583
1584 Cell *cell = current_module->addCell(myid, str.substr(1));
1585 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1586 cell->parameters["\\WIDTH"] = width;
1587
1588 if (attributes.count("\\reg")) {
1589 auto &attr = attributes.at("\\reg");
1590 if (attr->type != AST_CONSTANT)
1591 log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
1592 cell->attributes["\\reg"] = attr->asAttrConst();
1593 }
1594
1595 Wire *wire = current_module->addWire(myid + "_wire", width);
1596 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1597 cell->setPort("\\Y", wire);
1598
1599 is_signed = sign_hint;
1600 return SigSpec(wire);
1601 }
1602 } /* fall through */
1603
1604 // everything should have been handled above -> print error if not.
1605 default:
1606 for (auto f : log_files)
1607 current_ast->dumpAst(f, "verilog-ast> ");
1608 type_name = type2str(type);
1609 log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n",
1610 type_name.c_str());
1611 }
1612
1613 return RTLIL::SigSpec();
1614 }
1615
1616 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1617 // signals must be substituted before being used as input values (used by ProcessGenerator)
1618 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1619 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1620 {
1621 const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1622
1623 if (new_subst_ptr)
1624 genRTLIL_subst_ptr = new_subst_ptr;
1625
1626 bool sign_hint = true;
1627 int width_hint = width;
1628 detectSignWidthWorker(width_hint, sign_hint);
1629 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1630
1631 genRTLIL_subst_ptr = backup_subst_ptr;
1632
1633 if (width >= 0)
1634 sig.extend_u0(width, is_signed);
1635
1636 return sig;
1637 }
1638
1639 YOSYS_NAMESPACE_END