2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * This is the AST frontend library.
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
39 using namespace AST_INTERNAL
;
41 // helper function for creating RTLIL code for unary operations
42 static RTLIL::SigSpec
uniop2rtlil(AstNode
*that
, std::string type
, int result_width
, const RTLIL::SigSpec
&arg
, bool gen_attributes
= true)
44 std::stringstream sstr
;
45 sstr
<< type
<< "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
47 RTLIL::Cell
*cell
= new RTLIL::Cell
;
48 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
49 cell
->name
= sstr
.str();
51 current_module
->cells
[cell
->name
] = cell
;
53 RTLIL::Wire
*wire
= new RTLIL::Wire
;
54 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
55 wire
->name
= cell
->name
+ "_Y";
56 wire
->width
= result_width
;
57 current_module
->wires
[wire
->name
] = wire
;
59 RTLIL::SigChunk chunk
;
61 chunk
.width
= wire
->width
;
65 sig
.chunks
.push_back(chunk
);
66 sig
.width
= chunk
.width
;
69 for (auto &attr
: that
->attributes
) {
70 if (attr
.second
->type
!= AST_CONSTANT
)
71 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
72 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
73 cell
->attributes
[attr
.first
].str
= attr
.second
->str
;
74 cell
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
77 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(that
->children
[0]->is_signed
);
78 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(arg
.width
);
79 cell
->connections
["\\A"] = arg
;
81 cell
->parameters
["\\Y_WIDTH"] = result_width
;
82 cell
->connections
["\\Y"] = sig
;
86 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
87 static void widthExtend(AstNode
*that
, RTLIL::SigSpec
&sig
, int width
, bool is_signed
)
89 if (width
<= sig
.width
) {
90 sig
.extend(width
, is_signed
);
94 std::stringstream sstr
;
95 sstr
<< "$extend" << "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
97 RTLIL::Cell
*cell
= new RTLIL::Cell
;
98 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
99 cell
->name
= sstr
.str();
101 current_module
->cells
[cell
->name
] = cell
;
103 RTLIL::Wire
*wire
= new RTLIL::Wire
;
104 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
105 wire
->name
= cell
->name
+ "_Y";
107 current_module
->wires
[wire
->name
] = wire
;
109 RTLIL::SigChunk chunk
;
111 chunk
.width
= wire
->width
;
114 RTLIL::SigSpec new_sig
;
115 new_sig
.chunks
.push_back(chunk
);
116 new_sig
.width
= chunk
.width
;
119 for (auto &attr
: that
->attributes
) {
120 if (attr
.second
->type
!= AST_CONSTANT
)
121 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
122 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
123 cell
->attributes
[attr
.first
].str
= attr
.second
->str
;
124 cell
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
127 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(is_signed
);
128 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(sig
.width
);
129 cell
->connections
["\\A"] = sig
;
131 cell
->parameters
["\\Y_WIDTH"] = width
;
132 cell
->connections
["\\Y"] = new_sig
;
136 // helper function for creating RTLIL code for binary operations
137 static RTLIL::SigSpec
binop2rtlil(AstNode
*that
, std::string type
, int result_width
, const RTLIL::SigSpec
&left
, const RTLIL::SigSpec
&right
)
139 std::stringstream sstr
;
140 sstr
<< type
<< "$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
142 RTLIL::Cell
*cell
= new RTLIL::Cell
;
143 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
144 cell
->name
= sstr
.str();
146 current_module
->cells
[cell
->name
] = cell
;
148 RTLIL::Wire
*wire
= new RTLIL::Wire
;
149 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
150 wire
->name
= cell
->name
+ "_Y";
151 wire
->width
= result_width
;
152 current_module
->wires
[wire
->name
] = wire
;
154 RTLIL::SigChunk chunk
;
156 chunk
.width
= wire
->width
;
160 sig
.chunks
.push_back(chunk
);
161 sig
.width
= chunk
.width
;
163 for (auto &attr
: that
->attributes
) {
164 if (attr
.second
->type
!= AST_CONSTANT
)
165 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
166 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
167 cell
->attributes
[attr
.first
].str
= attr
.second
->str
;
168 cell
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
171 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(that
->children
[0]->is_signed
);
172 cell
->parameters
["\\B_SIGNED"] = RTLIL::Const(that
->children
[1]->is_signed
);
174 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(left
.width
);
175 cell
->parameters
["\\B_WIDTH"] = RTLIL::Const(right
.width
);
177 cell
->connections
["\\A"] = left
;
178 cell
->connections
["\\B"] = right
;
180 cell
->parameters
["\\Y_WIDTH"] = result_width
;
181 cell
->connections
["\\Y"] = sig
;
185 // helper function for creating RTLIL code for multiplexers
186 static RTLIL::SigSpec
mux2rtlil(AstNode
*that
, const RTLIL::SigSpec
&cond
, const RTLIL::SigSpec
&left
, const RTLIL::SigSpec
&right
)
188 assert(cond
.width
== 1);
190 std::stringstream sstr
;
191 sstr
<< "$ternary$" << that
->filename
<< ":" << that
->linenum
<< "$" << (RTLIL::autoidx
++);
193 RTLIL::Cell
*cell
= new RTLIL::Cell
;
194 cell
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
195 cell
->name
= sstr
.str();
197 current_module
->cells
[cell
->name
] = cell
;
199 RTLIL::Wire
*wire
= new RTLIL::Wire
;
200 wire
->attributes
["\\src"] = stringf("%s:%d", that
->filename
.c_str(), that
->linenum
);
201 wire
->name
= cell
->name
+ "_Y";
202 wire
->width
= left
.width
;
203 current_module
->wires
[wire
->name
] = wire
;
205 RTLIL::SigChunk chunk
;
207 chunk
.width
= wire
->width
;
211 sig
.chunks
.push_back(chunk
);
212 sig
.width
= chunk
.width
;
214 for (auto &attr
: that
->attributes
) {
215 if (attr
.second
->type
!= AST_CONSTANT
)
216 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
217 attr
.first
.c_str(), that
->filename
.c_str(), that
->linenum
);
218 cell
->attributes
[attr
.first
].str
= attr
.second
->str
;
219 cell
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
222 cell
->parameters
["\\WIDTH"] = RTLIL::Const(left
.width
);
224 cell
->connections
["\\A"] = right
;
225 cell
->connections
["\\B"] = left
;
226 cell
->connections
["\\S"] = cond
;
227 cell
->connections
["\\Y"] = sig
;
232 // helper class for converting AST always nodes to RTLIL processes
233 struct AST_INTERNAL::ProcessGenerator
235 // input and output structures
237 RTLIL::SigSpec skipSyncSignals
;
238 RTLIL::Process
*proc
;
239 const RTLIL::SigSpec
&outputSignals
;
241 // This always points to the RTLIL::CaseRule beeing filled at the moment
242 RTLIL::CaseRule
*current_case
;
244 // This two variables contain the replacement pattern to be used in the right hand side
245 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
246 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
247 // the value assigned in the first assignment. So when the first assignement is processed
248 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
249 RTLIL::SigSpec subst_rvalue_from
, subst_rvalue_to
;
251 // This two variables contain the replacement pattern to be used in the left hand side
252 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
253 // should not be connected to the signal foo. Instead it must be connected to the temporary
254 // signal that is used as input for the register that drives the signal foo.
255 RTLIL::SigSpec subst_lvalue_from
, subst_lvalue_to
;
257 // The code here generates a number of temprorary signal for each output register. This
258 // map helps generating nice numbered names for all this temporary signals.
259 std::map
<RTLIL::Wire
*, int> new_temp_count
;
261 ProcessGenerator(AstNode
*always
, RTLIL::SigSpec skipSyncSignalsArg
= RTLIL::SigSpec()) : always(always
), skipSyncSignals(skipSyncSignalsArg
), outputSignals(subst_lvalue_from
)
263 // generate process and simple root case
264 proc
= new RTLIL::Process
;
265 proc
->name
= stringf("$proc$%s:%d$%d", always
->filename
.c_str(), always
->linenum
, RTLIL::autoidx
++);
266 for (auto &attr
: always
->attributes
) {
267 if (attr
.second
->type
!= AST_CONSTANT
)
268 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
269 attr
.first
.c_str(), always
->filename
.c_str(), always
->linenum
);
270 proc
->attributes
[attr
.first
].str
= attr
.second
->str
;
271 proc
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
273 current_module
->processes
[proc
->name
] = proc
;
274 current_case
= &proc
->root_case
;
276 // create initial temporary signal for all output registers
277 collect_lvalues(subst_lvalue_from
, always
, true, true);
278 subst_lvalue_to
= new_temp_signal(subst_lvalue_from
);
280 bool found_anyedge_syncs
= false;
281 for (auto child
: always
->children
)
282 if (child
->type
== AST_EDGE
)
283 found_anyedge_syncs
= true;
285 if (found_anyedge_syncs
) {
286 log("Note: Assuming pure combinatorial block at %s:%d in\n", always
->filename
.c_str(), always
->linenum
);
287 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
288 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
291 // create syncs for the process
292 bool found_clocked_sync
= false;
293 for (auto child
: always
->children
)
294 if (child
->type
== AST_POSEDGE
|| child
->type
== AST_NEGEDGE
) {
295 found_clocked_sync
= true;
296 if (found_anyedge_syncs
)
297 log_error("Found non-synthesizable event list at %s:%d!\n", always
->filename
.c_str(), always
->linenum
);
298 RTLIL::SyncRule
*syncrule
= new RTLIL::SyncRule
;
299 syncrule
->type
= child
->type
== AST_POSEDGE
? RTLIL::STp
: RTLIL::STn
;
300 syncrule
->signal
= child
->children
[0]->genRTLIL();
301 addChunkActions(syncrule
->actions
, subst_lvalue_from
, subst_lvalue_to
, true);
302 proc
->syncs
.push_back(syncrule
);
304 if (proc
->syncs
.empty()) {
305 RTLIL::SyncRule
*syncrule
= new RTLIL::SyncRule
;
306 syncrule
->type
= RTLIL::STa
;
307 syncrule
->signal
= RTLIL::SigSpec();
308 addChunkActions(syncrule
->actions
, subst_lvalue_from
, subst_lvalue_to
, true);
309 proc
->syncs
.push_back(syncrule
);
312 // create initial assignments for the temporary signals
313 if ((flag_nolatches
|| always
->get_bool_attribute("\\nolatches") || current_module
->get_bool_attribute("\\nolatches")) && !found_clocked_sync
) {
314 subst_rvalue_from
= subst_lvalue_from
;
315 subst_rvalue_to
= RTLIL::SigSpec(RTLIL::State::Sx
, subst_rvalue_from
.width
);
317 addChunkActions(current_case
->actions
, subst_lvalue_to
, subst_lvalue_from
);
321 for (auto child
: always
->children
)
322 if (child
->type
== AST_BLOCK
)
326 // create new temporary signals
327 RTLIL::SigSpec
new_temp_signal(RTLIL::SigSpec sig
)
330 for (size_t i
= 0; i
< sig
.chunks
.size(); i
++)
332 RTLIL::SigChunk
&chunk
= sig
.chunks
[i
];
333 if (chunk
.wire
== NULL
)
336 RTLIL::Wire
*wire
= new RTLIL::Wire
;
337 wire
->attributes
["\\src"] = stringf("%s:%d", always
->filename
.c_str(), always
->linenum
);
339 wire
->name
= stringf("$%d%s[%d:%d]", new_temp_count
[chunk
.wire
]++,
340 chunk
.wire
->name
.c_str(), chunk
.width
+chunk
.offset
-1, chunk
.offset
);;
341 } while (current_module
->wires
.count(wire
->name
) > 0);
342 wire
->width
= chunk
.width
;
343 current_module
->wires
[wire
->name
] = wire
;
351 // recursively traverse the AST an collect all assigned signals
352 void collect_lvalues(RTLIL::SigSpec
®
, AstNode
*ast
, bool type_eq
, bool type_le
, bool run_sort_and_unify
= true)
357 for (auto child
: ast
->children
)
358 if (child
!= ast
->children
[0]) {
359 assert(child
->type
== AST_COND
);
360 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
367 for (auto child
: ast
->children
)
368 if (child
->type
== AST_BLOCK
)
369 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
373 for (auto child
: ast
->children
) {
374 if (child
->type
== AST_ASSIGN_EQ
&& type_eq
)
375 reg
.append(child
->children
[0]->genRTLIL());
376 if (child
->type
== AST_ASSIGN_LE
&& type_le
)
377 reg
.append(child
->children
[0]->genRTLIL());
378 if (child
->type
== AST_CASE
|| child
->type
== AST_BLOCK
)
379 collect_lvalues(reg
, child
, type_eq
, type_le
, false);
387 if (run_sort_and_unify
)
388 reg
.sort_and_unify();
391 // remove all assignments to the given signal pattern in a case and all its children.
392 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
393 // function is called to clean up the first two assignments as they are overwritten by
394 // the third assignment.
395 void removeSignalFromCaseTree(RTLIL::SigSpec pattern
, RTLIL::CaseRule
*cs
)
397 for (auto it
= cs
->actions
.begin(); it
!= cs
->actions
.end(); it
++)
398 it
->first
.remove2(pattern
, &it
->second
);
400 for (auto it
= cs
->switches
.begin(); it
!= cs
->switches
.end(); it
++)
401 for (auto it2
= (*it
)->cases
.begin(); it2
!= (*it
)->cases
.end(); it2
++)
402 removeSignalFromCaseTree(pattern
, *it2
);
405 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
406 // are avoided and the generated $mux cells have a more "natural" size.
407 void addChunkActions(std::vector
<RTLIL::SigSig
> &actions
, RTLIL::SigSpec lvalue
, RTLIL::SigSpec rvalue
, bool inSyncRule
= false)
410 lvalue
.remove2(skipSyncSignals
, &rvalue
);
411 assert(lvalue
.width
== rvalue
.width
);
416 for (size_t i
= 0; i
< lvalue
.chunks
.size(); i
++) {
417 RTLIL::SigSpec lhs
= lvalue
.chunks
[i
];
418 RTLIL::SigSpec rhs
= rvalue
.extract(offset
, lvalue
.chunks
[i
].width
);
419 if (inSyncRule
&& lvalue
.chunks
[i
].wire
&& lvalue
.chunks
[i
].wire
->get_bool_attribute("\\nosync"))
420 rhs
= RTLIL::SigSpec(RTLIL::State::Sx
, rhs
.width
);
421 actions
.push_back(RTLIL::SigSig(lhs
, rhs
));
426 // recursively process the AST and fill the RTLIL::Process
427 void processAst(AstNode
*ast
)
432 for (auto child
: ast
->children
)
439 RTLIL::SigSpec unmapped_lvalue
= ast
->children
[0]->genRTLIL(), lvalue
= unmapped_lvalue
;
440 RTLIL::SigSpec rvalue
= ast
->children
[1]->genWidthRTLIL(lvalue
.width
, &subst_rvalue_from
, &subst_rvalue_to
);
441 lvalue
.replace(subst_lvalue_from
, subst_lvalue_to
);
443 if (ast
->type
== AST_ASSIGN_EQ
) {
444 subst_rvalue_from
.remove2(unmapped_lvalue
, &subst_rvalue_to
);
445 subst_rvalue_from
.append(unmapped_lvalue
);
446 subst_rvalue_from
.optimize();
447 subst_rvalue_to
.append(rvalue
);
448 subst_rvalue_to
.optimize();
451 removeSignalFromCaseTree(lvalue
, current_case
);
452 current_case
->actions
.push_back(RTLIL::SigSig(lvalue
, rvalue
));
458 RTLIL::SwitchRule
*sw
= new RTLIL::SwitchRule
;
459 sw
->signal
= ast
->children
[0]->genWidthRTLIL(-1, &subst_rvalue_from
, &subst_rvalue_to
);
460 current_case
->switches
.push_back(sw
);
462 for (auto &attr
: ast
->attributes
) {
463 if (attr
.second
->type
!= AST_CONSTANT
)
464 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
465 attr
.first
.c_str(), ast
->filename
.c_str(), ast
->linenum
);
466 sw
->attributes
[attr
.first
].str
= attr
.second
->str
;
467 sw
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
470 RTLIL::SigSpec this_case_eq_lvalue
;
471 collect_lvalues(this_case_eq_lvalue
, ast
, true, false);
473 RTLIL::SigSpec this_case_eq_ltemp
= new_temp_signal(this_case_eq_lvalue
);
475 RTLIL::SigSpec this_case_eq_rvalue
= this_case_eq_lvalue
;
476 this_case_eq_rvalue
.replace(subst_rvalue_from
, subst_rvalue_to
);
478 RTLIL::SigSpec backup_subst_lvalue_from
= subst_lvalue_from
;
479 RTLIL::SigSpec backup_subst_lvalue_to
= subst_lvalue_to
;
481 RTLIL::SigSpec backup_subst_rvalue_from
= subst_rvalue_from
;
482 RTLIL::SigSpec backup_subst_rvalue_to
= subst_rvalue_to
;
484 bool generated_default_case
= false;
485 RTLIL::CaseRule
*last_generated_case
= NULL
;
486 for (auto child
: ast
->children
)
488 if (child
== ast
->children
[0] || generated_default_case
)
490 assert(child
->type
== AST_COND
);
492 subst_lvalue_from
= backup_subst_lvalue_from
;
493 subst_lvalue_to
= backup_subst_lvalue_to
;
495 subst_rvalue_from
= backup_subst_rvalue_from
;
496 subst_rvalue_to
= backup_subst_rvalue_to
;
498 subst_lvalue_from
.remove2(this_case_eq_lvalue
, &subst_lvalue_to
);
499 subst_lvalue_from
.append(this_case_eq_lvalue
);
500 subst_lvalue_from
.optimize();
501 subst_lvalue_to
.append(this_case_eq_ltemp
);
502 subst_lvalue_to
.optimize();
504 RTLIL::CaseRule
*backup_case
= current_case
;
505 current_case
= new RTLIL::CaseRule
;
506 last_generated_case
= current_case
;
507 addChunkActions(current_case
->actions
, this_case_eq_ltemp
, this_case_eq_rvalue
);
508 for (auto node
: child
->children
) {
509 if (node
->type
== AST_DEFAULT
) {
510 generated_default_case
= true;
511 current_case
->compare
.clear();
512 } else if (node
->type
== AST_BLOCK
) {
514 } else if (!generated_default_case
)
515 current_case
->compare
.push_back(node
->genWidthRTLIL(sw
->signal
.width
, &subst_rvalue_from
, &subst_rvalue_to
));
517 sw
->cases
.push_back(current_case
);
518 current_case
= backup_case
;
521 if (last_generated_case
!= NULL
&& ast
->get_bool_attribute("\\full_case")) {
522 last_generated_case
->compare
.clear();
523 } else if (!generated_default_case
) {
524 RTLIL::CaseRule
*default_case
= new RTLIL::CaseRule
;
525 addChunkActions(default_case
->actions
, this_case_eq_ltemp
, this_case_eq_rvalue
);
526 sw
->cases
.push_back(default_case
);
529 subst_lvalue_from
= backup_subst_lvalue_from
;
530 subst_lvalue_to
= backup_subst_lvalue_to
;
532 subst_rvalue_from
= backup_subst_rvalue_from
;
533 subst_rvalue_to
= backup_subst_rvalue_to
;
535 subst_rvalue_from
.remove2(this_case_eq_lvalue
, &subst_rvalue_to
);
536 subst_rvalue_from
.append(this_case_eq_lvalue
);
537 subst_rvalue_from
.optimize();
538 subst_rvalue_to
.append(this_case_eq_ltemp
);
539 subst_rvalue_to
.optimize();
541 this_case_eq_lvalue
.replace(subst_lvalue_from
, subst_lvalue_to
);
542 removeSignalFromCaseTree(this_case_eq_lvalue
, current_case
);
543 addChunkActions(current_case
->actions
, this_case_eq_lvalue
, this_case_eq_ltemp
);
557 // detect sign and width of an expression
558 void AstNode::detectSignWidthWorker(int &width_hint
, bool &sign_hint
)
560 std::string type_name
;
561 bool sub_sign_hint
= true;
562 int sub_width_hint
= -1;
564 AstNode
*range
= NULL
;
565 AstNode
*id_ast
= NULL
;
570 width_hint
= std::max(width_hint
, int(bits
.size()));
577 if (id_ast
== NULL
&& current_scope
.count(str
))
578 id_ast
= current_scope
.at(str
);
580 log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
581 if (id_ast
->type
== AST_PARAMETER
|| id_ast
->type
== AST_LOCALPARAM
) {
582 if (id_ast
->children
.size() > 1 && id_ast
->children
[1]->range_valid
) {
583 this_width
= id_ast
->children
[1]->range_left
- id_ast
->children
[1]->range_right
+ 1;
585 if (id_ast
->children
[0]->type
== AST_CONSTANT
) {
586 this_width
= id_ast
->children
[0]->bits
.size();
588 log_error("Failed to detect width for parameter %s at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
589 if (children
.size() != 0)
591 } else if (id_ast
->type
== AST_WIRE
|| id_ast
->type
== AST_AUTOWIRE
) {
592 if (!id_ast
->range_valid
) {
593 if (id_ast
->type
== AST_AUTOWIRE
)
596 // current_ast_mod->dumpAst(stdout, "");
598 // dumpAst(stdout, "");
600 log_error("Failed to detect with of signal access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
603 this_width
= id_ast
->range_left
- id_ast
->range_right
+ 1;
604 if (children
.size() != 0)
607 } else if (id_ast
->type
== AST_GENVAR
) {
609 } else if (id_ast
->type
== AST_MEMORY
) {
610 if (!id_ast
->children
[0]->range_valid
)
611 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
612 this_width
= id_ast
->children
[0]->range_left
- id_ast
->children
[0]->range_right
+ 1;
614 log_error("Failed to detect width for identifier %s at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
616 if (range
->children
.size() == 1)
618 else if (!range
->range_valid
) {
619 AstNode
*left_at_zero_ast
= children
[0]->children
[0]->clone();
620 AstNode
*right_at_zero_ast
= children
[0]->children
.size() >= 2 ? children
[0]->children
[1]->clone() : left_at_zero_ast
->clone();
621 while (left_at_zero_ast
->simplify(true, true, false, 1, -1, false)) { }
622 while (right_at_zero_ast
->simplify(true, true, false, 1, -1, false)) { }
623 if (left_at_zero_ast
->type
!= AST_CONSTANT
|| right_at_zero_ast
->type
!= AST_CONSTANT
)
624 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
625 str
.c_str(), filename
.c_str(), linenum
);
626 this_width
= left_at_zero_ast
->integer
- right_at_zero_ast
->integer
+ 1;
627 delete left_at_zero_ast
;
628 delete right_at_zero_ast
;
630 this_width
= range
->range_left
- range
->range_right
+ 1;
632 width_hint
= std::max(width_hint
, this_width
);
633 if (!id_ast
->is_signed
)
638 children
.at(0)->detectSignWidthWorker(width_hint
, sub_sign_hint
);
641 case AST_TO_UNSIGNED
:
642 children
.at(0)->detectSignWidthWorker(width_hint
, sub_sign_hint
);
647 for (auto child
: children
) {
649 sub_sign_hint
= true;
650 child
->detectSignWidthWorker(sub_width_hint
, sub_sign_hint
);
651 this_width
+= sub_width_hint
;
653 width_hint
= std::max(width_hint
, this_width
);
658 while (children
[0]->simplify(true, false, false, 1, -1, false) == true) { }
659 if (children
[0]->type
!= AST_CONSTANT
)
660 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename
.c_str(), linenum
);
661 children
[1]->detectSignWidthWorker(sub_width_hint
, sub_sign_hint
);
662 width_hint
= std::max(width_hint
, children
[0]->bitsAsConst().as_int() * sub_width_hint
);
669 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
);
676 for (auto child
: children
)
677 child
->detectSignWidthWorker(width_hint
, sign_hint
);
683 case AST_REDUCE_XNOR
:
684 case AST_REDUCE_BOOL
:
685 width_hint
= std::max(width_hint
, 1);
690 case AST_SHIFT_RIGHT
:
691 case AST_SHIFT_SLEFT
:
692 case AST_SHIFT_SRIGHT
:
694 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
);
703 width_hint
= std::max(width_hint
, 1);
712 for (auto child
: children
)
713 child
->detectSignWidthWorker(width_hint
, sign_hint
);
719 width_hint
= std::max(width_hint
, 1);
724 children
.at(1)->detectSignWidthWorker(width_hint
, sign_hint
);
725 children
.at(2)->detectSignWidthWorker(width_hint
, sign_hint
);
729 if (!id2ast
->is_signed
)
731 if (!id2ast
->children
[0]->range_valid
)
732 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str
.c_str(), filename
.c_str(), linenum
);
733 this_width
= id2ast
->children
[0]->range_left
- id2ast
->children
[0]->range_right
+ 1;
734 width_hint
= std::max(width_hint
, this_width
);
737 // everything should have been handled above -> print error if not.
739 for (auto f
: log_files
)
740 current_ast
->dumpAst(f
, "verilog-ast> ");
741 log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
742 type2str(type
).c_str(), filename
.c_str(), linenum
);
746 // detect sign and width of an expression
747 void AstNode::detectSignWidth(int &width_hint
, bool &sign_hint
)
749 width_hint
= -1, sign_hint
= true;
750 detectSignWidthWorker(width_hint
, sign_hint
);
753 // create RTLIL from an AST node
754 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
755 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
757 // note that this function is influenced by a number of global variables that might be set when
758 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
759 // larger expressions into a netlist of cells.
760 RTLIL::SigSpec
AstNode::genRTLIL(int width_hint
, bool sign_hint
)
762 // in the following big switch() statement there are some uses of
763 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
764 // cases this variable is used to hold the type of the cell that should
765 // be instanciated for this type of AST node.
766 std::string type_name
;
768 current_filename
= filename
;
769 set_line_num(linenum
);
773 // simply ignore this nodes.
774 // they are eighter leftovers from simplify() or are referenced by other nodes
775 // and are only accessed here thru this references
788 // create an RTLIL::Wire for an AST_WIRE node
790 if (current_module
->wires
.count(str
) != 0)
791 log_error("Re-definition of signal `%s' at %s:%d!\n",
792 str
.c_str(), filename
.c_str(), linenum
);
794 log_error("Signal `%s' with non-constant width at %s:%d!\n",
795 str
.c_str(), filename
.c_str(), linenum
);
797 if (range_left
< range_right
&& (range_left
!= -1 || range_right
!= 0)) {
798 int tmp
= range_left
;
799 range_left
= range_right
;
803 RTLIL::Wire
*wire
= new RTLIL::Wire
;
804 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
806 wire
->width
= range_left
- range_right
+ 1;
807 wire
->start_offset
= range_right
;
808 wire
->port_id
= port_id
;
809 wire
->port_input
= is_input
;
810 wire
->port_output
= is_output
;
811 current_module
->wires
[wire
->name
] = wire
;
813 for (auto &attr
: attributes
) {
814 if (attr
.second
->type
!= AST_CONSTANT
)
815 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
816 attr
.first
.c_str(), filename
.c_str(), linenum
);
817 wire
->attributes
[attr
.first
].str
= attr
.second
->str
;
818 wire
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
823 // create an RTLIL::Memory for an AST_MEMORY node
825 if (current_module
->memories
.count(str
) != 0)
826 log_error("Re-definition of memory `%s' at %s:%d!\n",
827 str
.c_str(), filename
.c_str(), linenum
);
829 assert(children
.size() >= 2);
830 assert(children
[0]->type
== AST_RANGE
);
831 assert(children
[1]->type
== AST_RANGE
);
833 if (!children
[0]->range_valid
|| !children
[1]->range_valid
)
834 log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
835 str
.c_str(), filename
.c_str(), linenum
);
837 RTLIL::Memory
*memory
= new RTLIL::Memory
;
838 memory
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
840 memory
->width
= children
[0]->range_left
- children
[0]->range_right
+ 1;
841 memory
->start_offset
= children
[0]->range_right
;
842 memory
->size
= children
[1]->range_left
- children
[1]->range_right
;
843 current_module
->memories
[memory
->name
] = memory
;
845 if (memory
->size
< 0)
847 memory
->size
+= std::min(children
[1]->range_left
, children
[1]->range_right
) + 1;
849 for (auto &attr
: attributes
) {
850 if (attr
.second
->type
!= AST_CONSTANT
)
851 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
852 attr
.first
.c_str(), filename
.c_str(), linenum
);
853 memory
->attributes
[attr
.first
].str
= attr
.second
->str
;
854 memory
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
859 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
863 detectSignWidth(width_hint
, sign_hint
);
865 RTLIL::SigChunk chunk
;
867 chunk
.data
.bits
= bits
;
868 chunk
.width
= bits
.size();
872 sig
.chunks
.push_back(chunk
);
873 sig
.width
= chunk
.width
;
875 is_signed
= sign_hint
;
879 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
880 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
881 // shifter cell is created and the output signal of this cell is returned
884 RTLIL::Wire
*wire
= NULL
;
885 RTLIL::SigChunk chunk
;
887 if (id2ast
&& id2ast
->type
== AST_AUTOWIRE
&& current_module
->wires
.count(str
) == 0) {
888 RTLIL::Wire
*wire
= new RTLIL::Wire
;
889 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
891 if (width_hint
>= 0) {
892 wire
->width
= width_hint
;
893 log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n",
894 str
.c_str(), width_hint
, filename
.c_str(), linenum
);
896 log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n",
897 str
.c_str(), filename
.c_str(), linenum
);
899 wire
->auto_width
= true;
900 current_module
->wires
[str
] = wire
;
902 else if (id2ast
->type
== AST_PARAMETER
|| id2ast
->type
== AST_LOCALPARAM
) {
903 if (id2ast
->children
[0]->type
!= AST_CONSTANT
)
904 log_error("Parameter %s does not evaluate to constant value at %s:%d!\n",
905 str
.c_str(), filename
.c_str(), linenum
);
906 chunk
= RTLIL::Const(id2ast
->children
[0]->bits
);
907 goto use_const_chunk
;
909 else if (!id2ast
|| (id2ast
->type
!= AST_WIRE
&& id2ast
->type
!= AST_AUTOWIRE
&&
910 id2ast
->type
!= AST_MEMORY
) || current_module
->wires
.count(str
) == 0)
911 log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
912 str
.c_str(), filename
.c_str(), linenum
);
914 if (id2ast
->type
== AST_MEMORY
)
915 log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
916 str
.c_str(), filename
.c_str(), linenum
);
918 wire
= current_module
->wires
[str
];
920 chunk
.width
= wire
->width
;
924 if (children
.size() != 0) {
925 assert(children
[0]->type
== AST_RANGE
);
926 if (!children
[0]->range_valid
) {
927 AstNode
*left_at_zero_ast
= children
[0]->children
[0]->clone();
928 AstNode
*right_at_zero_ast
= children
[0]->children
.size() >= 2 ? children
[0]->children
[1]->clone() : left_at_zero_ast
->clone();
929 while (left_at_zero_ast
->simplify(true, true, false, 1, -1, false)) { }
930 while (right_at_zero_ast
->simplify(true, true, false, 1, -1, false)) { }
931 if (left_at_zero_ast
->type
!= AST_CONSTANT
|| right_at_zero_ast
->type
!= AST_CONSTANT
)
932 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
933 str
.c_str(), filename
.c_str(), linenum
);
934 int width
= left_at_zero_ast
->integer
- right_at_zero_ast
->integer
+ 1;
935 AstNode
*fake_ast
= new AstNode(AST_NONE
, clone(), children
[0]->children
.size() >= 2 ?
936 children
[0]->children
[1]->clone() : children
[0]->children
[0]->clone());
937 fake_ast
->children
[0]->delete_children();
938 RTLIL::SigSpec sig
= binop2rtlil(fake_ast
, "$shr", width
,
939 fake_ast
->children
[0]->genRTLIL(), fake_ast
->children
[1]->genRTLIL());
940 delete left_at_zero_ast
;
941 delete right_at_zero_ast
;
945 chunk
.offset
= children
[0]->range_right
- id2ast
->range_right
;
946 chunk
.width
= children
[0]->range_left
- children
[0]->range_right
+ 1;
947 if (children
[0]->range_left
> id2ast
->range_left
|| id2ast
->range_right
> children
[0]->range_right
)
948 log_error("Range select out of bounds on signal `%s' at %s:%d!\n",
949 str
.c_str(), filename
.c_str(), linenum
);
954 sig
.chunks
.push_back(chunk
);
955 sig
.width
= chunk
.width
;
957 if (genRTLIL_subst_from
&& genRTLIL_subst_to
)
958 sig
.replace(*genRTLIL_subst_from
, *genRTLIL_subst_to
);
960 is_signed
= children
.size() > 0 ? false : id2ast
->is_signed
&& sign_hint
;
964 // just pass thru the signal. the parent will evaluate the is_signed property and inperpret the SigSpec accordingly
966 case AST_TO_UNSIGNED
: {
967 RTLIL::SigSpec sig
= children
[0]->genRTLIL();
968 if (sig
.width
< width_hint
)
969 sig
.extend_u0(width_hint
, sign_hint
);
970 is_signed
= sign_hint
;
974 // concatenation of signals can be done directly using RTLIL::SigSpec
978 for (auto it
= children
.begin(); it
!= children
.end(); it
++) {
979 RTLIL::SigSpec s
= (*it
)->genRTLIL();
980 for (size_t i
= 0; i
< s
.chunks
.size(); i
++) {
981 sig
.chunks
.push_back(s
.chunks
[i
]);
982 sig
.width
+= s
.chunks
[i
].width
;
985 if (sig
.width
< width_hint
)
986 sig
.extend_u0(width_hint
, false);
990 // replication of signals can be done directly using RTLIL::SigSpec
991 case AST_REPLICATE
: {
992 RTLIL::SigSpec left
= children
[0]->genRTLIL();
993 RTLIL::SigSpec right
= children
[1]->genRTLIL();
994 if (!left
.is_fully_const())
995 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename
.c_str(), linenum
);
996 int count
= left
.as_int();
998 for (int i
= 0; i
< count
; i
++)
1000 if (sig
.width
< width_hint
)
1001 sig
.extend_u0(width_hint
, false);
1006 // generate cells for unary operations: $not, $pos, $neg
1007 if (0) { case AST_BIT_NOT
: type_name
= "$not"; }
1008 if (0) { case AST_POS
: type_name
= "$pos"; }
1009 if (0) { case AST_NEG
: type_name
= "$neg"; }
1011 RTLIL::SigSpec arg
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1012 is_signed
= children
[0]->is_signed
;
1013 int width
= arg
.width
;
1014 if (width_hint
> 0) {
1016 widthExtend(this, arg
, width
, is_signed
);
1018 return uniop2rtlil(this, type_name
, width
, arg
);
1021 // generate cells for binary operations: $and, $or, $xor, $xnor
1022 if (0) { case AST_BIT_AND
: type_name
= "$and"; }
1023 if (0) { case AST_BIT_OR
: type_name
= "$or"; }
1024 if (0) { case AST_BIT_XOR
: type_name
= "$xor"; }
1025 if (0) { case AST_BIT_XNOR
: type_name
= "$xnor"; }
1028 detectSignWidth(width_hint
, sign_hint
);
1029 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1030 RTLIL::SigSpec right
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1031 int width
= std::max(left
.width
, right
.width
);
1034 is_signed
= children
[0]->is_signed
&& children
[1]->is_signed
;
1035 return binop2rtlil(this, type_name
, width
, left
, right
);
1038 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1039 if (0) { case AST_REDUCE_AND
: type_name
= "$reduce_and"; }
1040 if (0) { case AST_REDUCE_OR
: type_name
= "$reduce_or"; }
1041 if (0) { case AST_REDUCE_XOR
: type_name
= "$reduce_xor"; }
1042 if (0) { case AST_REDUCE_XNOR
: type_name
= "$reduce_xnor"; }
1044 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1045 RTLIL::SigSpec sig
= uniop2rtlil(this, type_name
, std::max(width_hint
, 1), arg
);
1049 // generate cells for unary operations: $reduce_bool
1050 // (this is actually just an $reduce_or, but for clearity a different cell type is used)
1051 if (0) { case AST_REDUCE_BOOL
: type_name
= "$reduce_bool"; }
1053 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1054 RTLIL::SigSpec sig
= arg
.width
> 1 ? uniop2rtlil(this, type_name
, std::max(width_hint
, 1), arg
) : arg
;
1058 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1059 if (0) { case AST_SHIFT_LEFT
: type_name
= "$shl"; }
1060 if (0) { case AST_SHIFT_RIGHT
: type_name
= "$shr"; }
1061 if (0) { case AST_SHIFT_SLEFT
: type_name
= "$sshl"; }
1062 if (0) { case AST_SHIFT_SRIGHT
: type_name
= "$sshr"; }
1065 detectSignWidth(width_hint
, sign_hint
);
1066 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1067 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1068 int width
= width_hint
> 0 ? width_hint
: left
.width
;
1069 is_signed
= children
[0]->is_signed
;
1070 return binop2rtlil(this, type_name
, width
, left
, right
);
1073 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1074 if (0) { case AST_LT
: type_name
= "$lt"; }
1075 if (0) { case AST_LE
: type_name
= "$le"; }
1076 if (0) { case AST_EQ
: type_name
= "$eq"; }
1077 if (0) { case AST_NE
: type_name
= "$ne"; }
1078 if (0) { case AST_GE
: type_name
= "$ge"; }
1079 if (0) { case AST_GT
: type_name
= "$gt"; }
1081 int width
= std::max(width_hint
, 1);
1082 width_hint
= -1, sign_hint
= true;
1083 children
[0]->detectSignWidthWorker(width_hint
, sign_hint
);
1084 children
[1]->detectSignWidthWorker(width_hint
, sign_hint
);
1085 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1086 RTLIL::SigSpec right
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1087 RTLIL::SigSpec sig
= binop2rtlil(this, type_name
, width
, left
, right
);
1091 // generate cells for binary operations: $add, $sub, $mul, $div, $mod, $pow
1092 if (0) { case AST_ADD
: type_name
= "$add"; }
1093 if (0) { case AST_SUB
: type_name
= "$sub"; }
1094 if (0) { case AST_MUL
: type_name
= "$mul"; }
1095 if (0) { case AST_DIV
: type_name
= "$div"; }
1096 if (0) { case AST_MOD
: type_name
= "$mod"; }
1097 if (0) { case AST_POW
: type_name
= "$pow"; }
1100 detectSignWidth(width_hint
, sign_hint
);
1101 RTLIL::SigSpec left
= children
[0]->genRTLIL(width_hint
, sign_hint
);
1102 RTLIL::SigSpec right
= type
== AST_POW
? children
[1]->genRTLIL() : children
[1]->genRTLIL(width_hint
, sign_hint
);
1103 int width
= type
== AST_POW
? left
.width
: std::max(left
.width
, right
.width
);
1104 if (width
> width_hint
&& width_hint
> 0)
1106 if (width
< width_hint
) {
1107 if (type
== AST_ADD
|| type
== AST_SUB
|| type
== AST_DIV
)
1109 if (type
== AST_SUB
&& (!children
[0]->is_signed
|| !children
[1]->is_signed
))
1111 if (type
== AST_MUL
)
1112 width
= std::min(left
.width
+ right
.width
, width_hint
);
1113 if (type
== AST_POW
)
1116 is_signed
= children
[0]->is_signed
&& children
[1]->is_signed
;
1117 if (!flag_noopt
&& type
== AST_POW
&& left
.is_fully_const() && left
.as_int() == 2)
1118 return binop2rtlil(this, "$shl", width
, RTLIL::SigSpec(1, left
.width
), right
);
1119 return binop2rtlil(this, type_name
, width
, left
, right
);
1122 // generate cells for binary operations: $logic_and, $logic_or
1123 if (0) { case AST_LOGIC_AND
: type_name
= "$logic_and"; }
1124 if (0) { case AST_LOGIC_OR
: type_name
= "$logic_or"; }
1126 RTLIL::SigSpec left
= children
[0]->genRTLIL();
1127 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1128 return binop2rtlil(this, type_name
, std::max(width_hint
, 1), left
, right
);
1131 // generate cells for unary operations: $logic_not
1134 RTLIL::SigSpec arg
= children
[0]->genRTLIL();
1135 return uniop2rtlil(this, "$logic_not", std::max(width_hint
, 1), arg
);
1138 // generate multiplexer for ternary operator (aka ?:-operator)
1142 detectSignWidth(width_hint
, sign_hint
);
1144 RTLIL::SigSpec cond
= children
[0]->genRTLIL();
1145 RTLIL::SigSpec val1
= children
[1]->genRTLIL(width_hint
, sign_hint
);
1146 RTLIL::SigSpec val2
= children
[2]->genRTLIL(width_hint
, sign_hint
);
1149 cond
= uniop2rtlil(this, "$reduce_bool", 1, cond
, false);
1151 int width
= std::max(val1
.width
, val2
.width
);
1152 is_signed
= children
[1]->is_signed
&& children
[2]->is_signed
;
1153 widthExtend(this, val1
, width
, is_signed
);
1154 widthExtend(this, val2
, width
, is_signed
);
1156 RTLIL::SigSpec sig
= mux2rtlil(this, cond
, val1
, val2
);
1158 if (sig
.width
< width_hint
)
1159 sig
.extend_u0(width_hint
, sign_hint
);
1163 // generate $memrd cells for memory read ports
1166 std::stringstream sstr
;
1167 sstr
<< "$memrd$" << str
<< "$" << filename
<< ":" << linenum
<< "$" << (RTLIL::autoidx
++);
1169 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1170 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1171 cell
->name
= sstr
.str();
1172 cell
->type
= "$memrd";
1173 current_module
->cells
[cell
->name
] = cell
;
1175 RTLIL::Wire
*wire
= new RTLIL::Wire
;
1176 wire
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1177 wire
->name
= cell
->name
+ "_DATA";
1178 wire
->width
= current_module
->memories
[str
]->width
;
1179 current_module
->wires
[wire
->name
] = wire
;
1182 while ((1 << addr_bits
) < current_module
->memories
[str
]->size
)
1185 cell
->connections
["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx
, 1);
1186 cell
->connections
["\\ADDR"] = children
[0]->genRTLIL();
1187 cell
->connections
["\\DATA"] = RTLIL::SigSpec(wire
);
1189 cell
->parameters
["\\MEMID"] = RTLIL::Const(str
);
1190 cell
->parameters
["\\ABITS"] = RTLIL::Const(addr_bits
);
1191 cell
->parameters
["\\WIDTH"] = RTLIL::Const(wire
->width
);
1193 cell
->parameters
["\\CLK_ENABLE"] = RTLIL::Const(0);
1194 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(0);
1196 return RTLIL::SigSpec(wire
);
1199 // generate $memwr cells for memory write ports
1202 std::stringstream sstr
;
1203 sstr
<< "$memwr$" << str
<< "$" << filename
<< ":" << linenum
<< "$" << (RTLIL::autoidx
++);
1205 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1206 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1207 cell
->name
= sstr
.str();
1208 cell
->type
= "$memwr";
1209 current_module
->cells
[cell
->name
] = cell
;
1212 while ((1 << addr_bits
) < current_module
->memories
[str
]->size
)
1215 cell
->connections
["\\CLK"] = RTLIL::SigSpec(RTLIL::State::Sx
, 1);
1216 cell
->connections
["\\ADDR"] = children
[0]->genRTLIL();
1217 cell
->connections
["\\DATA"] = children
[1]->genRTLIL();
1218 cell
->connections
["\\EN"] = children
[2]->genRTLIL();
1220 cell
->parameters
["\\MEMID"] = RTLIL::Const(str
);
1221 cell
->parameters
["\\ABITS"] = RTLIL::Const(addr_bits
);
1222 cell
->parameters
["\\WIDTH"] = RTLIL::Const(current_module
->memories
[str
]->width
);
1224 cell
->parameters
["\\CLK_ENABLE"] = RTLIL::Const(0);
1225 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(0);
1229 // add entries to current_module->connections for assignments (outside of always blocks)
1232 if (children
[0]->type
== AST_IDENTIFIER
&& children
[0]->id2ast
&& children
[0]->id2ast
->type
== AST_AUTOWIRE
) {
1233 RTLIL::SigSpec right
= children
[1]->genRTLIL();
1234 RTLIL::SigSpec left
= children
[0]->genWidthRTLIL(right
.width
);
1235 current_module
->connections
.push_back(RTLIL::SigSig(left
, right
));
1237 RTLIL::SigSpec left
= children
[0]->genRTLIL();
1238 RTLIL::SigSpec right
= children
[1]->genWidthRTLIL(left
.width
);
1239 current_module
->connections
.push_back(RTLIL::SigSig(left
, right
));
1244 // create an RTLIL::Cell for an AST_CELL
1247 int port_counter
= 0, para_counter
= 0;
1248 RTLIL::Cell
*cell
= new RTLIL::Cell
;
1249 cell
->attributes
["\\src"] = stringf("%s:%d", filename
.c_str(), linenum
);
1251 for (auto it
= children
.begin(); it
!= children
.end(); it
++) {
1252 AstNode
*child
= *it
;
1253 if (child
->type
== AST_CELLTYPE
) {
1254 cell
->type
= child
->str
;
1257 if (child
->type
== AST_PARASET
) {
1258 if (child
->children
[0]->type
!= AST_CONSTANT
)
1259 log_error("Parameter `%s' with non-constant value at %s:%d!\n",
1260 child
->str
.c_str(), filename
.c_str(), linenum
);
1261 if (child
->str
.size() == 0) {
1263 snprintf(buf
, 100, "$%d", ++para_counter
);
1264 cell
->parameters
[buf
].str
= child
->children
[0]->str
;
1265 cell
->parameters
[buf
].bits
= child
->children
[0]->bits
;
1267 cell
->parameters
[child
->str
].str
= child
->children
[0]->str
;
1268 cell
->parameters
[child
->str
].bits
= child
->children
[0]->bits
;
1272 if (child
->type
== AST_ARGUMENT
) {
1274 if (child
->children
.size() > 0)
1275 sig
= child
->children
[0]->genRTLIL();
1276 if (child
->str
.size() == 0) {
1278 snprintf(buf
, 100, "$%d", ++port_counter
);
1279 cell
->connections
[buf
] = sig
;
1281 cell
->connections
[child
->str
] = sig
;
1287 for (auto &attr
: attributes
) {
1288 if (attr
.second
->type
!= AST_CONSTANT
)
1289 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1290 attr
.first
.c_str(), filename
.c_str(), linenum
);
1291 cell
->attributes
[attr
.first
].str
= attr
.second
->str
;
1292 cell
->attributes
[attr
.first
].bits
= attr
.second
->bits
;
1294 if (current_module
->cells
.count(cell
->name
) != 0)
1295 log_error("Re-definition of cell `%s' at %s:%d!\n",
1296 str
.c_str(), filename
.c_str(), linenum
);
1297 current_module
->cells
[str
] = cell
;
1301 // use ProcessGenerator for always blocks
1303 AstNode
*always
= this->clone();
1304 ProcessGenerator
generator(always
);
1305 ignoreThisSignalsInInitial
.append(generator
.outputSignals
);
1310 AstNode
*always
= this->clone();
1311 ProcessGenerator
generator(always
, ignoreThisSignalsInInitial
);
1315 // everything should have been handled above -> print error if not.
1317 for (auto f
: log_files
)
1318 current_ast
->dumpAst(f
, "verilog-ast> ");
1319 type_name
= type2str(type
);
1320 log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
1321 type_name
.c_str(), filename
.c_str(), linenum
);
1324 return RTLIL::SigSpec();
1327 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1328 // signals must be substituted before beeing used as input values (used by ProcessGenerator)
1329 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1330 RTLIL::SigSpec
AstNode::genWidthRTLIL(int width
, RTLIL::SigSpec
*subst_from
, RTLIL::SigSpec
*subst_to
)
1332 RTLIL::SigSpec
*backup_subst_from
= genRTLIL_subst_from
;
1333 RTLIL::SigSpec
*backup_subst_to
= genRTLIL_subst_to
;
1336 genRTLIL_subst_from
= subst_from
;
1338 genRTLIL_subst_to
= subst_to
;
1340 bool sign_hint
= true;
1341 int width_hint
= width
;
1342 detectSignWidthWorker(width_hint
, sign_hint
);
1343 RTLIL::SigSpec sig
= genRTLIL(width_hint
, sign_hint
);
1345 genRTLIL_subst_from
= backup_subst_from
;
1346 genRTLIL_subst_to
= backup_subst_to
;
1349 widthExtend(this, sig
, width
, is_signed
);