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Changed the AST genWidthRTLIL subst interface to use a std::map
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "libs/sha1/sha1.h"
31 #include "ast.h"
32
33 #include <sstream>
34 #include <stdarg.h>
35 #include <algorithm>
36
37 YOSYS_NAMESPACE_BEGIN
38
39 using namespace AST;
40 using namespace AST_INTERNAL;
41
42 // helper function for creating RTLIL code for unary operations
43 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
44 {
45 std::stringstream sstr;
46 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
47
48 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
49 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
50
51 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
52 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
53
54 if (gen_attributes)
55 for (auto &attr : that->attributes) {
56 if (attr.second->type != AST_CONSTANT)
57 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
58 attr.first.c_str(), that->filename.c_str(), that->linenum);
59 cell->attributes[attr.first] = attr.second->asAttrConst();
60 }
61
62 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
63 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
64 cell->setPort("\\A", arg);
65
66 cell->parameters["\\Y_WIDTH"] = result_width;
67 cell->setPort("\\Y", wire);
68 return wire;
69 }
70
71 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
72 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed, std::string celltype)
73 {
74 if (width <= sig.size()) {
75 sig.extend(width, is_signed);
76 return;
77 }
78
79 std::stringstream sstr;
80 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
81
82 RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
83 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
84
85 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
86 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
87
88 if (that != NULL)
89 for (auto &attr : that->attributes) {
90 if (attr.second->type != AST_CONSTANT)
91 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
92 attr.first.c_str(), that->filename.c_str(), that->linenum);
93 cell->attributes[attr.first] = attr.second->asAttrConst();
94 }
95
96 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
97 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
98 cell->setPort("\\A", sig);
99
100 cell->parameters["\\Y_WIDTH"] = width;
101 cell->setPort("\\Y", wire);
102 sig = wire;
103 }
104
105 // helper function for creating RTLIL code for binary operations
106 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
107 {
108 std::stringstream sstr;
109 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
110
111 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
112 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
113
114 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
115 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
116
117 for (auto &attr : that->attributes) {
118 if (attr.second->type != AST_CONSTANT)
119 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
120 attr.first.c_str(), that->filename.c_str(), that->linenum);
121 cell->attributes[attr.first] = attr.second->asAttrConst();
122 }
123
124 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
125 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
126
127 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
128 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
129
130 cell->setPort("\\A", left);
131 cell->setPort("\\B", right);
132
133 cell->parameters["\\Y_WIDTH"] = result_width;
134 cell->setPort("\\Y", wire);
135 return wire;
136 }
137
138 // helper function for creating RTLIL code for multiplexers
139 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
140 {
141 log_assert(cond.size() == 1);
142
143 std::stringstream sstr;
144 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
145
146 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
147 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
148
149 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
150 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
151
152 for (auto &attr : that->attributes) {
153 if (attr.second->type != AST_CONSTANT)
154 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
155 attr.first.c_str(), that->filename.c_str(), that->linenum);
156 cell->attributes[attr.first] = attr.second->asAttrConst();
157 }
158
159 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
160
161 cell->setPort("\\A", right);
162 cell->setPort("\\B", left);
163 cell->setPort("\\S", cond);
164 cell->setPort("\\Y", wire);
165
166 return wire;
167 }
168
169 // helper class for converting AST always nodes to RTLIL processes
170 struct AST_INTERNAL::ProcessGenerator
171 {
172 // input and output structures
173 AstNode *always;
174 RTLIL::SigSpec initSyncSignals;
175 RTLIL::Process *proc;
176 RTLIL::SigSpec outputSignals;
177
178 // This always points to the RTLIL::CaseRule beeing filled at the moment
179 RTLIL::CaseRule *current_case;
180
181 // This two variables contain the replacement pattern to be used in the right hand side
182 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
183 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
184 // the value assigned in the first assignment. So when the first assignement is processed
185 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
186 RTLIL::SigSpec subst_rvalue_from, subst_rvalue_to;
187
188 // This two variables contain the replacement pattern to be used in the left hand side
189 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
190 // should not be connected to the signal foo. Instead it must be connected to the temporary
191 // signal that is used as input for the register that drives the signal foo.
192 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
193
194 // The code here generates a number of temprorary signal for each output register. This
195 // map helps generating nice numbered names for all this temporary signals.
196 std::map<RTLIL::Wire*, int> new_temp_count;
197
198 // Buffer for generating the init action
199 RTLIL::SigSpec init_lvalue, init_rvalue;
200
201 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
202 {
203 // generate process and simple root case
204 proc = new RTLIL::Process;
205 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
206 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
207 for (auto &attr : always->attributes) {
208 if (attr.second->type != AST_CONSTANT)
209 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
210 attr.first.c_str(), always->filename.c_str(), always->linenum);
211 proc->attributes[attr.first] = attr.second->asAttrConst();
212 }
213 current_module->processes[proc->name] = proc;
214 current_case = &proc->root_case;
215
216 // create initial temporary signal for all output registers
217 collect_lvalues(subst_lvalue_from, always, true, true);
218 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
219
220 bool found_anyedge_syncs = false;
221 for (auto child : always->children)
222 if (child->type == AST_EDGE)
223 found_anyedge_syncs = true;
224
225 if (found_anyedge_syncs) {
226 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
227 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
228 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
229 }
230
231 // create syncs for the process
232 bool found_clocked_sync = false;
233 for (auto child : always->children)
234 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
235 found_clocked_sync = true;
236 if (found_anyedge_syncs)
237 log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
238 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
239 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
240 syncrule->signal = child->children[0]->genRTLIL();
241 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
242 proc->syncs.push_back(syncrule);
243 }
244 if (proc->syncs.empty()) {
245 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
246 syncrule->type = RTLIL::STa;
247 syncrule->signal = RTLIL::SigSpec();
248 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
249 proc->syncs.push_back(syncrule);
250 }
251
252 // create initial assignments for the temporary signals
253 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
254 subst_rvalue_from = subst_lvalue_from;
255 subst_rvalue_to = RTLIL::SigSpec(RTLIL::State::Sx, subst_rvalue_from.size());
256 } else {
257 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
258 }
259
260 // process the AST
261 for (auto child : always->children)
262 if (child->type == AST_BLOCK)
263 processAst(child);
264
265 if (initSyncSignals.size() > 0)
266 {
267 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
268 sync->type = RTLIL::SyncType::STi;
269 proc->syncs.push_back(sync);
270
271 log_assert(init_lvalue.size() == init_rvalue.size());
272
273 int offset = 0;
274 for (auto &init_lvalue_c : init_lvalue.chunks()) {
275 RTLIL::SigSpec lhs = init_lvalue_c;
276 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
277 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
278 offset += lhs.size();
279 }
280 }
281
282 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
283 }
284
285 // create new temporary signals
286 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
287 {
288 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
289
290 for (int i = 0; i < SIZE(chunks); i++)
291 {
292 RTLIL::SigChunk &chunk = chunks[i];
293 if (chunk.wire == NULL)
294 continue;
295
296 std::string wire_name;
297 do {
298 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
299 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
300 if (chunk.wire->name.str().find('$') != std::string::npos)
301 wire_name += stringf("$%d", autoidx++);
302 } while (current_module->wires_.count(wire_name) > 0);
303
304 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
305 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
306
307 chunk.wire = wire;
308 chunk.offset = 0;
309 }
310
311 return chunks;
312 }
313
314 // recursively traverse the AST an collect all assigned signals
315 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
316 {
317 switch (ast->type)
318 {
319 case AST_CASE:
320 for (auto child : ast->children)
321 if (child != ast->children[0]) {
322 log_assert(child->type == AST_COND);
323 collect_lvalues(reg, child, type_eq, type_le, false);
324 }
325 break;
326
327 case AST_COND:
328 case AST_ALWAYS:
329 case AST_INITIAL:
330 for (auto child : ast->children)
331 if (child->type == AST_BLOCK)
332 collect_lvalues(reg, child, type_eq, type_le, false);
333 break;
334
335 case AST_BLOCK:
336 for (auto child : ast->children) {
337 if (child->type == AST_ASSIGN_EQ && type_eq)
338 reg.append(child->children[0]->genRTLIL());
339 if (child->type == AST_ASSIGN_LE && type_le)
340 reg.append(child->children[0]->genRTLIL());
341 if (child->type == AST_CASE || child->type == AST_BLOCK)
342 collect_lvalues(reg, child, type_eq, type_le, false);
343 }
344 break;
345
346 default:
347 log_abort();
348 }
349
350 if (run_sort_and_unify)
351 reg.sort_and_unify();
352 }
353
354 // remove all assignments to the given signal pattern in a case and all its children.
355 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
356 // function is called to clean up the first two assignments as they are overwritten by
357 // the third assignment.
358 void removeSignalFromCaseTree(RTLIL::SigSpec pattern, RTLIL::CaseRule *cs)
359 {
360 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
361 it->first.remove2(pattern, &it->second);
362
363 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
364 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
365 removeSignalFromCaseTree(pattern, *it2);
366 }
367
368 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
369 // are avoided and the generated $mux cells have a more "natural" size.
370 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
371 {
372 if (inSyncRule && initSyncSignals.size() > 0) {
373 init_lvalue.append(lvalue.extract(initSyncSignals));
374 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
375 lvalue.remove2(initSyncSignals, &rvalue);
376 }
377 log_assert(lvalue.size() == rvalue.size());
378
379 int offset = 0;
380 for (auto &lvalue_c : lvalue.chunks()) {
381 RTLIL::SigSpec lhs = lvalue_c;
382 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
383 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
384 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
385 actions.push_back(RTLIL::SigSig(lhs, rhs));
386 offset += lhs.size();
387 }
388 }
389
390 // recursively process the AST and fill the RTLIL::Process
391 void processAst(AstNode *ast)
392 {
393 switch (ast->type)
394 {
395 case AST_BLOCK:
396 for (auto child : ast->children)
397 processAst(child);
398 break;
399
400 case AST_ASSIGN_EQ:
401 case AST_ASSIGN_LE:
402 {
403 std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
404 for (int i = 0; i < SIZE(subst_rvalue_to); i++)
405 new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
406
407 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
408 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &new_subst_rvalue_map);
409 lvalue.replace(subst_lvalue_from, subst_lvalue_to);
410
411 if (ast->type == AST_ASSIGN_EQ) {
412 subst_rvalue_from.remove2(unmapped_lvalue, &subst_rvalue_to);
413 subst_rvalue_from.append(unmapped_lvalue);
414 subst_rvalue_to.append(rvalue);
415 }
416
417 removeSignalFromCaseTree(lvalue, current_case);
418 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
419 }
420 break;
421
422 case AST_CASE:
423 {
424 std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
425 for (int i = 0; i < SIZE(subst_rvalue_to); i++)
426 new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
427
428 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
429 sw->signal = ast->children[0]->genWidthRTLIL(-1, &new_subst_rvalue_map);
430 current_case->switches.push_back(sw);
431
432 for (auto &attr : ast->attributes) {
433 if (attr.second->type != AST_CONSTANT)
434 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
435 attr.first.c_str(), ast->filename.c_str(), ast->linenum);
436 sw->attributes[attr.first] = attr.second->asAttrConst();
437 }
438
439 RTLIL::SigSpec this_case_eq_lvalue;
440 collect_lvalues(this_case_eq_lvalue, ast, true, false);
441
442 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
443
444 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
445 this_case_eq_rvalue.replace(subst_rvalue_from, subst_rvalue_to);
446
447 RTLIL::SigSpec backup_subst_lvalue_from = subst_lvalue_from;
448 RTLIL::SigSpec backup_subst_lvalue_to = subst_lvalue_to;
449
450 RTLIL::SigSpec backup_subst_rvalue_from = subst_rvalue_from;
451 RTLIL::SigSpec backup_subst_rvalue_to = subst_rvalue_to;
452
453 RTLIL::CaseRule *default_case = NULL;
454 RTLIL::CaseRule *last_generated_case = NULL;
455 for (auto child : ast->children)
456 {
457 if (child == ast->children[0])
458 continue;
459 log_assert(child->type == AST_COND);
460
461 subst_lvalue_from = backup_subst_lvalue_from;
462 subst_lvalue_to = backup_subst_lvalue_to;
463
464 subst_rvalue_from = backup_subst_rvalue_from;
465 subst_rvalue_to = backup_subst_rvalue_to;
466
467 subst_lvalue_from.remove2(this_case_eq_lvalue, &subst_lvalue_to);
468 subst_lvalue_from.append(this_case_eq_lvalue);
469 subst_lvalue_to.append(this_case_eq_ltemp);
470
471 RTLIL::CaseRule *backup_case = current_case;
472 current_case = new RTLIL::CaseRule;
473 last_generated_case = current_case;
474 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
475 for (auto node : child->children) {
476 if (node->type == AST_DEFAULT)
477 default_case = current_case;
478 else if (node->type == AST_BLOCK)
479 processAst(node);
480 else {
481 std::map<RTLIL::SigBit, RTLIL::SigBit> new_subst_rvalue_map;
482 for (int i = 0; i < SIZE(subst_rvalue_to); i++)
483 new_subst_rvalue_map[subst_rvalue_from[i]] = subst_rvalue_to[i];
484 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &new_subst_rvalue_map));
485 }
486 }
487 if (default_case != current_case)
488 sw->cases.push_back(current_case);
489 else
490 log_assert(current_case->compare.size() == 0);
491 current_case = backup_case;
492 }
493
494 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
495 last_generated_case->compare.clear();
496 } else {
497 if (default_case == NULL) {
498 default_case = new RTLIL::CaseRule;
499 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
500 }
501 sw->cases.push_back(default_case);
502 }
503
504 subst_lvalue_from = backup_subst_lvalue_from;
505 subst_lvalue_to = backup_subst_lvalue_to;
506
507 subst_rvalue_from = backup_subst_rvalue_from;
508 subst_rvalue_to = backup_subst_rvalue_to;
509
510 subst_rvalue_from.remove2(this_case_eq_lvalue, &subst_rvalue_to);
511 subst_rvalue_from.append(this_case_eq_lvalue);
512 subst_rvalue_to.append(this_case_eq_ltemp);
513
514 this_case_eq_lvalue.replace(subst_lvalue_from, subst_lvalue_to);
515 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
516 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
517 }
518 break;
519
520 case AST_WIRE:
521 log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
522 break;
523
524 case AST_TCALL:
525 case AST_FOR:
526 break;
527
528 default:
529 log_abort();
530 }
531 }
532 };
533
534 // detect sign and width of an expression
535 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
536 {
537 std::string type_name;
538 bool sub_sign_hint = true;
539 int sub_width_hint = -1;
540 int this_width = 0;
541 AstNode *range = NULL;
542 AstNode *id_ast = NULL;
543
544 bool local_found_real = false;
545 if (found_real == NULL)
546 found_real = &local_found_real;
547
548 switch (type)
549 {
550 case AST_CONSTANT:
551 width_hint = std::max(width_hint, int(bits.size()));
552 if (!is_signed)
553 sign_hint = false;
554 break;
555
556 case AST_REALVALUE:
557 *found_real = true;
558 width_hint = std::max(width_hint, 32);
559 break;
560
561 case AST_IDENTIFIER:
562 id_ast = id2ast;
563 if (id_ast == NULL && current_scope.count(str))
564 id_ast = current_scope.at(str);
565 if (!id_ast)
566 log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
567 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
568 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
569 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
570 } else
571 if (id_ast->children[0]->type == AST_CONSTANT) {
572 this_width = id_ast->children[0]->bits.size();
573 } else
574 log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
575 if (children.size() != 0)
576 range = children[0];
577 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
578 if (!id_ast->range_valid) {
579 if (id_ast->type == AST_AUTOWIRE)
580 this_width = 1;
581 else {
582 // current_ast_mod->dumpAst(NULL, "mod> ");
583 // log("---\n");
584 // id_ast->dumpAst(NULL, "decl> ");
585 // dumpAst(NULL, "ref> ");
586 log_error("Failed to detect with of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
587 }
588 } else {
589 this_width = id_ast->range_left - id_ast->range_right + 1;
590 if (children.size() != 0)
591 range = children[0];
592 }
593 } else if (id_ast->type == AST_GENVAR) {
594 this_width = 32;
595 } else if (id_ast->type == AST_MEMORY) {
596 if (!id_ast->children[0]->range_valid)
597 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
598 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
599 } else
600 log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
601 if (range) {
602 if (range->children.size() == 1)
603 this_width = 1;
604 else if (!range->range_valid) {
605 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
606 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
607 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
608 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
609 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
610 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
611 str.c_str(), filename.c_str(), linenum);
612 this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
613 delete left_at_zero_ast;
614 delete right_at_zero_ast;
615 } else
616 this_width = range->range_left - range->range_right + 1;
617 sign_hint = false;
618 }
619 width_hint = std::max(width_hint, this_width);
620 if (!id_ast->is_signed)
621 sign_hint = false;
622 break;
623
624 case AST_TO_BITS:
625 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
626 if (children[0]->type != AST_CONSTANT)
627 log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename.c_str(), linenum);
628 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
629 width_hint = std::max(width_hint, children[0]->bitsAsConst().as_int());
630 break;
631
632 case AST_TO_SIGNED:
633 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
634 break;
635
636 case AST_TO_UNSIGNED:
637 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
638 sign_hint = false;
639 break;
640
641 case AST_CONCAT:
642 for (auto child : children) {
643 sub_width_hint = 0;
644 sub_sign_hint = true;
645 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
646 this_width += sub_width_hint;
647 }
648 width_hint = std::max(width_hint, this_width);
649 sign_hint = false;
650 break;
651
652 case AST_REPLICATE:
653 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
654 if (children[0]->type != AST_CONSTANT)
655 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
656 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
657 width_hint = std::max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
658 sign_hint = false;
659 break;
660
661 case AST_NEG:
662 case AST_BIT_NOT:
663 case AST_POS:
664 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
665 break;
666
667 case AST_BIT_AND:
668 case AST_BIT_OR:
669 case AST_BIT_XOR:
670 case AST_BIT_XNOR:
671 for (auto child : children)
672 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
673 break;
674
675 case AST_REDUCE_AND:
676 case AST_REDUCE_OR:
677 case AST_REDUCE_XOR:
678 case AST_REDUCE_XNOR:
679 case AST_REDUCE_BOOL:
680 width_hint = std::max(width_hint, 1);
681 sign_hint = false;
682 break;
683
684 case AST_SHIFT_LEFT:
685 case AST_SHIFT_RIGHT:
686 case AST_SHIFT_SLEFT:
687 case AST_SHIFT_SRIGHT:
688 case AST_POW:
689 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
690 break;
691
692 case AST_LT:
693 case AST_LE:
694 case AST_EQ:
695 case AST_NE:
696 case AST_EQX:
697 case AST_NEX:
698 case AST_GE:
699 case AST_GT:
700 width_hint = std::max(width_hint, 1);
701 sign_hint = false;
702 break;
703
704 case AST_ADD:
705 case AST_SUB:
706 case AST_MUL:
707 case AST_DIV:
708 case AST_MOD:
709 for (auto child : children)
710 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
711 break;
712
713 case AST_LOGIC_AND:
714 case AST_LOGIC_OR:
715 case AST_LOGIC_NOT:
716 width_hint = std::max(width_hint, 1);
717 sign_hint = false;
718 break;
719
720 case AST_TERNARY:
721 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
722 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
723 break;
724
725 case AST_MEMRD:
726 if (!id2ast->is_signed)
727 sign_hint = false;
728 if (!id2ast->children[0]->range_valid)
729 log_error("Failed to detect with of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
730 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
731 width_hint = std::max(width_hint, this_width);
732 break;
733
734 // everything should have been handled above -> print error if not.
735 default:
736 for (auto f : log_files)
737 current_ast->dumpAst(f, "verilog-ast> ");
738 log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
739 type2str(type).c_str(), filename.c_str(), linenum);
740 }
741
742 if (*found_real)
743 sign_hint = true;
744 }
745
746 // detect sign and width of an expression
747 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
748 {
749 width_hint = -1;
750 sign_hint = true;
751 if (found_real)
752 *found_real = false;
753 detectSignWidthWorker(width_hint, sign_hint, found_real);
754 }
755
756 // create RTLIL from an AST node
757 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
758 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
759 //
760 // note that this function is influenced by a number of global variables that might be set when
761 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
762 // larger expressions into a netlist of cells.
763 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
764 {
765 // in the following big switch() statement there are some uses of
766 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
767 // cases this variable is used to hold the type of the cell that should
768 // be instanciated for this type of AST node.
769 std::string type_name;
770
771 current_filename = filename;
772 set_line_num(linenum);
773
774 switch (type)
775 {
776 // simply ignore this nodes.
777 // they are eighter leftovers from simplify() or are referenced by other nodes
778 // and are only accessed here thru this references
779 case AST_TASK:
780 case AST_FUNCTION:
781 case AST_AUTOWIRE:
782 case AST_LOCALPARAM:
783 case AST_DEFPARAM:
784 case AST_GENVAR:
785 case AST_GENFOR:
786 case AST_GENBLOCK:
787 case AST_GENIF:
788 case AST_GENCASE:
789 break;
790
791 // remember the parameter, needed for example in techmap
792 case AST_PARAMETER:
793 current_module->avail_parameters.insert(str);
794 break;
795
796 // create an RTLIL::Wire for an AST_WIRE node
797 case AST_WIRE: {
798 if (current_module->wires_.count(str) != 0)
799 log_error("Re-definition of signal `%s' at %s:%d!\n",
800 str.c_str(), filename.c_str(), linenum);
801 if (!range_valid)
802 log_error("Signal `%s' with non-constant width at %s:%d!\n",
803 str.c_str(), filename.c_str(), linenum);
804
805 log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
806
807 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
808 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
809 wire->start_offset = range_right;
810 wire->port_id = port_id;
811 wire->port_input = is_input;
812 wire->port_output = is_output;
813 wire->upto = range_swapped;
814
815 for (auto &attr : attributes) {
816 if (attr.second->type != AST_CONSTANT)
817 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
818 attr.first.c_str(), filename.c_str(), linenum);
819 wire->attributes[attr.first] = attr.second->asAttrConst();
820 }
821 }
822 break;
823
824 // create an RTLIL::Memory for an AST_MEMORY node
825 case AST_MEMORY: {
826 if (current_module->memories.count(str) != 0)
827 log_error("Re-definition of memory `%s' at %s:%d!\n",
828 str.c_str(), filename.c_str(), linenum);
829
830 log_assert(children.size() >= 2);
831 log_assert(children[0]->type == AST_RANGE);
832 log_assert(children[1]->type == AST_RANGE);
833
834 if (!children[0]->range_valid || !children[1]->range_valid)
835 log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
836 str.c_str(), filename.c_str(), linenum);
837
838 RTLIL::Memory *memory = new RTLIL::Memory;
839 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
840 memory->name = str;
841 memory->width = children[0]->range_left - children[0]->range_right + 1;
842 memory->start_offset = children[0]->range_right;
843 memory->size = children[1]->range_left - children[1]->range_right;
844 current_module->memories[memory->name] = memory;
845
846 if (memory->size < 0)
847 memory->size *= -1;
848 memory->size += std::min(children[1]->range_left, children[1]->range_right) + 1;
849
850 for (auto &attr : attributes) {
851 if (attr.second->type != AST_CONSTANT)
852 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
853 attr.first.c_str(), filename.c_str(), linenum);
854 memory->attributes[attr.first] = attr.second->asAttrConst();
855 }
856 }
857 break;
858
859 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
860 case AST_CONSTANT:
861 {
862 if (width_hint < 0)
863 detectSignWidth(width_hint, sign_hint);
864
865 is_signed = sign_hint;
866 return RTLIL::SigSpec(bitsAsConst());
867 }
868
869 case AST_REALVALUE:
870 {
871 RTLIL::SigSpec sig = realAsConst(width_hint);
872 log("Warning: converting real value %e to binary %s at %s:%d.\n",
873 realvalue, log_signal(sig), filename.c_str(), linenum);
874 return sig;
875 }
876
877 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
878 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
879 // shifter cell is created and the output signal of this cell is returned
880 case AST_IDENTIFIER:
881 {
882 RTLIL::Wire *wire = NULL;
883 RTLIL::SigChunk chunk;
884
885 int add_undef_bits_msb = 0;
886 int add_undef_bits_lsb = 0;
887
888 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
889 RTLIL::Wire *wire = current_module->addWire(str);
890 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
891 wire->name = str;
892 if (flag_autowire)
893 log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
894 else
895 log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
896 }
897 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
898 if (id2ast->children[0]->type != AST_CONSTANT)
899 log_error("Parameter %s does not evaluate to constant value at %s:%d!\n",
900 str.c_str(), filename.c_str(), linenum);
901 chunk = RTLIL::Const(id2ast->children[0]->bits);
902 goto use_const_chunk;
903 }
904 else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
905 id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0)
906 log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
907 str.c_str(), filename.c_str(), linenum);
908
909 if (id2ast->type == AST_MEMORY)
910 log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
911 str.c_str(), filename.c_str(), linenum);
912
913 wire = current_module->wires_[str];
914 chunk.wire = wire;
915 chunk.width = wire->width;
916 chunk.offset = 0;
917
918 use_const_chunk:
919 if (children.size() != 0) {
920 log_assert(children[0]->type == AST_RANGE);
921 int source_width = id2ast->range_left - id2ast->range_right + 1;
922 int source_offset = id2ast->range_right;
923 if (!children[0]->range_valid) {
924 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
925 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
926 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
927 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
928 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
929 log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
930 str.c_str(), filename.c_str(), linenum);
931 int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
932 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
933 children[0]->children[1]->clone() : children[0]->children[0]->clone());
934 fake_ast->children[0]->delete_children();
935 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
936 if (id2ast->range_right != 0) {
937 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
938 fake_ast->children[1]->is_signed = true;
939 }
940 if (id2ast->range_swapped) {
941 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
942 fake_ast->children[1]->is_signed = true;
943 }
944 if (SIZE(shift_val) >= 32)
945 fake_ast->children[1]->is_signed = true;
946 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
947 delete left_at_zero_ast;
948 delete right_at_zero_ast;
949 delete fake_ast;
950 return sig;
951 } else {
952 chunk.width = children[0]->range_left - children[0]->range_right + 1;
953 chunk.offset = children[0]->range_right - source_offset;
954 if (id2ast->range_swapped)
955 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
956 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
957 if (chunk.width == 1)
958 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
959 str.c_str(), filename.c_str(), linenum);
960 else
961 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
962 str.c_str(), filename.c_str(), linenum, chunk.width);
963 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
964 } else {
965 if (chunk.width + chunk.offset > source_width) {
966 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
967 chunk.width -= add_undef_bits_msb;
968 }
969 if (chunk.offset < 0) {
970 add_undef_bits_lsb = -chunk.offset;
971 chunk.width -= add_undef_bits_lsb;
972 chunk.offset += add_undef_bits_lsb;
973 }
974 if (add_undef_bits_lsb)
975 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
976 str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
977 if (add_undef_bits_msb)
978 log("Warning: Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
979 str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
980 }
981 }
982 }
983
984 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
985
986 if (genRTLIL_subst_ptr)
987 sig.replace(*genRTLIL_subst_ptr);
988
989 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
990 return sig;
991 }
992
993 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
994 case AST_TO_SIGNED:
995 case AST_TO_UNSIGNED: {
996 RTLIL::SigSpec sig = children[0]->genRTLIL();
997 if (sig.size() < width_hint)
998 sig.extend_u0(width_hint, sign_hint);
999 is_signed = sign_hint;
1000 return sig;
1001 }
1002
1003 // concatenation of signals can be done directly using RTLIL::SigSpec
1004 case AST_CONCAT: {
1005 RTLIL::SigSpec sig;
1006 for (auto it = children.begin(); it != children.end(); it++)
1007 sig.append((*it)->genRTLIL());
1008 if (sig.size() < width_hint)
1009 sig.extend_u0(width_hint, false);
1010 return sig;
1011 }
1012
1013 // replication of signals can be done directly using RTLIL::SigSpec
1014 case AST_REPLICATE: {
1015 RTLIL::SigSpec left = children[0]->genRTLIL();
1016 RTLIL::SigSpec right = children[1]->genRTLIL();
1017 if (!left.is_fully_const())
1018 log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
1019 int count = left.as_int();
1020 RTLIL::SigSpec sig;
1021 for (int i = 0; i < count; i++)
1022 sig.append(right);
1023 if (sig.size() < width_hint)
1024 sig.extend_u0(width_hint, false);
1025 is_signed = false;
1026 return sig;
1027 }
1028
1029 // generate cells for unary operations: $not, $pos, $neg
1030 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1031 if (0) { case AST_POS: type_name = "$pos"; }
1032 if (0) { case AST_NEG: type_name = "$neg"; }
1033 {
1034 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1035 is_signed = children[0]->is_signed;
1036 int width = arg.size();
1037 if (width_hint > 0) {
1038 width = width_hint;
1039 widthExtend(this, arg, width, is_signed, "$pos");
1040 }
1041 return uniop2rtlil(this, type_name, width, arg);
1042 }
1043
1044 // generate cells for binary operations: $and, $or, $xor, $xnor
1045 if (0) { case AST_BIT_AND: type_name = "$and"; }
1046 if (0) { case AST_BIT_OR: type_name = "$or"; }
1047 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1048 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1049 {
1050 if (width_hint < 0)
1051 detectSignWidth(width_hint, sign_hint);
1052 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1053 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1054 int width = std::max(left.size(), right.size());
1055 if (width_hint > 0)
1056 width = width_hint;
1057 is_signed = children[0]->is_signed && children[1]->is_signed;
1058 return binop2rtlil(this, type_name, width, left, right);
1059 }
1060
1061 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1062 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1063 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1064 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1065 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1066 {
1067 RTLIL::SigSpec arg = children[0]->genRTLIL();
1068 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, std::max(width_hint, 1), arg);
1069 return sig;
1070 }
1071
1072 // generate cells for unary operations: $reduce_bool
1073 // (this is actually just an $reduce_or, but for clearity a different cell type is used)
1074 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1075 {
1076 RTLIL::SigSpec arg = children[0]->genRTLIL();
1077 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, std::max(width_hint, 1), arg) : arg;
1078 return sig;
1079 }
1080
1081 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1082 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1083 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1084 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1085 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1086 {
1087 if (width_hint < 0)
1088 detectSignWidth(width_hint, sign_hint);
1089 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1090 RTLIL::SigSpec right = children[1]->genRTLIL();
1091 int width = width_hint > 0 ? width_hint : left.size();
1092 is_signed = children[0]->is_signed;
1093 return binop2rtlil(this, type_name, width, left, right);
1094 }
1095
1096 // generate cells for binary operations: $pow
1097 case AST_POW:
1098 {
1099 int right_width;
1100 bool right_signed;
1101 children[1]->detectSignWidth(right_width, right_signed);
1102 if (width_hint < 0)
1103 detectSignWidth(width_hint, sign_hint);
1104 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1105 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1106 int width = width_hint > 0 ? width_hint : left.size();
1107 is_signed = children[0]->is_signed;
1108 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1109 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1110 return binop2rtlil(this, "$pow", width, left, right);
1111 }
1112
1113 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1114 if (0) { case AST_LT: type_name = "$lt"; }
1115 if (0) { case AST_LE: type_name = "$le"; }
1116 if (0) { case AST_EQ: type_name = "$eq"; }
1117 if (0) { case AST_NE: type_name = "$ne"; }
1118 if (0) { case AST_EQX: type_name = "$eqx"; }
1119 if (0) { case AST_NEX: type_name = "$nex"; }
1120 if (0) { case AST_GE: type_name = "$ge"; }
1121 if (0) { case AST_GT: type_name = "$gt"; }
1122 {
1123 int width = std::max(width_hint, 1);
1124 width_hint = -1, sign_hint = true;
1125 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1126 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1127 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1128 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1129 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1130 return sig;
1131 }
1132
1133 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1134 if (0) { case AST_ADD: type_name = "$add"; }
1135 if (0) { case AST_SUB: type_name = "$sub"; }
1136 if (0) { case AST_MUL: type_name = "$mul"; }
1137 if (0) { case AST_DIV: type_name = "$div"; }
1138 if (0) { case AST_MOD: type_name = "$mod"; }
1139 {
1140 if (width_hint < 0)
1141 detectSignWidth(width_hint, sign_hint);
1142 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1143 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1144 #if 0
1145 int width = std::max(left.size(), right.size());
1146 if (width > width_hint && width_hint > 0)
1147 width = width_hint;
1148 if (width < width_hint) {
1149 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1150 width++;
1151 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1152 width = width_hint;
1153 if (type == AST_MUL)
1154 width = std::min(left.size() + right.size(), width_hint);
1155 }
1156 #else
1157 int width = std::max(std::max(left.size(), right.size()), width_hint);
1158 #endif
1159 is_signed = children[0]->is_signed && children[1]->is_signed;
1160 return binop2rtlil(this, type_name, width, left, right);
1161 }
1162
1163 // generate cells for binary operations: $logic_and, $logic_or
1164 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1165 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1166 {
1167 RTLIL::SigSpec left = children[0]->genRTLIL();
1168 RTLIL::SigSpec right = children[1]->genRTLIL();
1169 return binop2rtlil(this, type_name, std::max(width_hint, 1), left, right);
1170 }
1171
1172 // generate cells for unary operations: $logic_not
1173 case AST_LOGIC_NOT:
1174 {
1175 RTLIL::SigSpec arg = children[0]->genRTLIL();
1176 return uniop2rtlil(this, "$logic_not", std::max(width_hint, 1), arg);
1177 }
1178
1179 // generate multiplexer for ternary operator (aka ?:-operator)
1180 case AST_TERNARY:
1181 {
1182 if (width_hint < 0)
1183 detectSignWidth(width_hint, sign_hint);
1184
1185 RTLIL::SigSpec cond = children[0]->genRTLIL();
1186 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1187 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1188
1189 if (cond.size() > 1)
1190 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1191
1192 int width = std::max(val1.size(), val2.size());
1193 is_signed = children[1]->is_signed && children[2]->is_signed;
1194 widthExtend(this, val1, width, is_signed, "$bu0");
1195 widthExtend(this, val2, width, is_signed, "$bu0");
1196
1197 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1198
1199 if (sig.size() < width_hint)
1200 sig.extend_u0(width_hint, sign_hint);
1201 return sig;
1202 }
1203
1204 // generate $memrd cells for memory read ports
1205 case AST_MEMRD:
1206 {
1207 std::stringstream sstr;
1208 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1209
1210 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1211 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1212
1213 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1214 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1215
1216 int addr_bits = 1;
1217 while ((1 << addr_bits) < current_module->memories[str]->size)
1218 addr_bits++;
1219
1220 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1221 cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
1222 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1223
1224 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1225 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1226 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1227
1228 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1229 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1230 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1231
1232 return RTLIL::SigSpec(wire);
1233 }
1234
1235 // generate $memwr cells for memory write ports
1236 case AST_MEMWR:
1237 {
1238 std::stringstream sstr;
1239 sstr << "$memwr$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1240
1241 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memwr");
1242 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1243
1244 int addr_bits = 1;
1245 while ((1 << addr_bits) < current_module->memories[str]->size)
1246 addr_bits++;
1247
1248 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1249 cell->setPort("\\ADDR", children[0]->genWidthRTLIL(addr_bits));
1250 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width));
1251 cell->setPort("\\EN", children[2]->genRTLIL());
1252
1253 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1254 cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
1255 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1256
1257 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1258 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1259
1260 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1261 }
1262 break;
1263
1264 // generate $assert cells
1265 case AST_ASSERT:
1266 {
1267 log_assert(children.size() == 2);
1268
1269 RTLIL::SigSpec check = children[0]->genRTLIL();
1270 log_assert(check.size() == 1);
1271
1272 RTLIL::SigSpec en = children[1]->genRTLIL();
1273 log_assert(en.size() == 1);
1274
1275 std::stringstream sstr;
1276 sstr << "$assert$" << filename << ":" << linenum << "$" << (autoidx++);
1277
1278 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$assert");
1279 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1280
1281 for (auto &attr : attributes) {
1282 if (attr.second->type != AST_CONSTANT)
1283 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1284 attr.first.c_str(), filename.c_str(), linenum);
1285 cell->attributes[attr.first] = attr.second->asAttrConst();
1286 }
1287
1288 cell->setPort("\\A", check);
1289 cell->setPort("\\EN", en);
1290 }
1291 break;
1292
1293 // add entries to current_module->connections for assignments (outside of always blocks)
1294 case AST_ASSIGN:
1295 {
1296 if (children[0]->type == AST_IDENTIFIER && children[0]->id2ast && children[0]->id2ast->type == AST_AUTOWIRE) {
1297 RTLIL::SigSpec right = children[1]->genRTLIL();
1298 RTLIL::SigSpec left = children[0]->genWidthRTLIL(right.size());
1299 current_module->connect(RTLIL::SigSig(left, right));
1300 } else {
1301 RTLIL::SigSpec left = children[0]->genRTLIL();
1302 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1303 current_module->connect(RTLIL::SigSig(left, right));
1304 }
1305 }
1306 break;
1307
1308 // create an RTLIL::Cell for an AST_CELL
1309 case AST_CELL:
1310 {
1311 int port_counter = 0, para_counter = 0;
1312
1313 if (current_module->count_id(str) != 0)
1314 log_error("Re-definition of cell `%s' at %s:%d!\n",
1315 str.c_str(), filename.c_str(), linenum);
1316
1317 RTLIL::Cell *cell = current_module->addCell(str, "");
1318 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1319
1320 for (auto it = children.begin(); it != children.end(); it++) {
1321 AstNode *child = *it;
1322 if (child->type == AST_CELLTYPE) {
1323 cell->type = child->str;
1324 if (flag_icells && cell->type.substr(0, 2) == "\\$")
1325 cell->type = cell->type.substr(1);
1326 continue;
1327 }
1328 if (child->type == AST_PARASET) {
1329 if (child->children[0]->type != AST_CONSTANT)
1330 log_error("Parameter `%s' with non-constant value at %s:%d!\n",
1331 child->str.c_str(), filename.c_str(), linenum);
1332 if (child->str.size() == 0) {
1333 char buf[100];
1334 snprintf(buf, 100, "$%d", ++para_counter);
1335 cell->parameters[buf] = child->children[0]->asParaConst();
1336 } else {
1337 cell->parameters[child->str] = child->children[0]->asParaConst();
1338 }
1339 continue;
1340 }
1341 if (child->type == AST_ARGUMENT) {
1342 RTLIL::SigSpec sig;
1343 if (child->children.size() > 0)
1344 sig = child->children[0]->genRTLIL();
1345 if (child->str.size() == 0) {
1346 char buf[100];
1347 snprintf(buf, 100, "$%d", ++port_counter);
1348 cell->setPort(buf, sig);
1349 } else {
1350 cell->setPort(child->str, sig);
1351 }
1352 continue;
1353 }
1354 log_abort();
1355 }
1356 for (auto &attr : attributes) {
1357 if (attr.second->type != AST_CONSTANT)
1358 log_error("Attribute `%s' with non-constant value at %s:%d!\n",
1359 attr.first.c_str(), filename.c_str(), linenum);
1360 cell->attributes[attr.first] = attr.second->asAttrConst();
1361 }
1362 }
1363 break;
1364
1365 // use ProcessGenerator for always blocks
1366 case AST_ALWAYS: {
1367 AstNode *always = this->clone();
1368 ProcessGenerator generator(always);
1369 ignoreThisSignalsInInitial.append(generator.outputSignals);
1370 delete always;
1371 } break;
1372
1373 case AST_INITIAL: {
1374 AstNode *always = this->clone();
1375 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1376 delete always;
1377 } break;
1378
1379 // everything should have been handled above -> print error if not.
1380 default:
1381 for (auto f : log_files)
1382 current_ast->dumpAst(f, "verilog-ast> ");
1383 type_name = type2str(type);
1384 log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
1385 type_name.c_str(), filename.c_str(), linenum);
1386 }
1387
1388 return RTLIL::SigSpec();
1389 }
1390
1391 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1392 // signals must be substituted before beeing used as input values (used by ProcessGenerator)
1393 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1394 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1395 {
1396 std::map<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1397
1398 if (new_subst_ptr)
1399 genRTLIL_subst_ptr = new_subst_ptr;
1400
1401 bool sign_hint = true;
1402 int width_hint = width;
1403 detectSignWidthWorker(width_hint, sign_hint);
1404 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1405
1406 genRTLIL_subst_ptr = backup_subst_ptr;
1407
1408 if (width >= 0)
1409 sig.extend_u0(width, is_signed);
1410
1411 return sig;
1412 }
1413
1414 YOSYS_NAMESPACE_END
1415