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Merge remote-tracking branch 'origin/master' into xc7srl
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "kernel/utils.h"
31 #include "libs/sha1/sha1.h"
32 #include "ast.h"
33
34 #include <sstream>
35 #include <stdarg.h>
36 #include <algorithm>
37
38 YOSYS_NAMESPACE_BEGIN
39
40 using namespace AST;
41 using namespace AST_INTERNAL;
42
43 // helper function for creating RTLIL code for unary operations
44 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
45 {
46 std::stringstream sstr;
47 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
48
49 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
51
52 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
54
55 if (gen_attributes)
56 for (auto &attr : that->attributes) {
57 if (attr.second->type != AST_CONSTANT)
58 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
59 cell->attributes[attr.first] = attr.second->asAttrConst();
60 }
61
62 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
63 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
64 cell->setPort("\\A", arg);
65
66 cell->parameters["\\Y_WIDTH"] = result_width;
67 cell->setPort("\\Y", wire);
68 return wire;
69 }
70
71 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
72 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
73 {
74 if (width <= sig.size()) {
75 sig.extend_u0(width, is_signed);
76 return;
77 }
78
79 std::stringstream sstr;
80 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
81
82 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
83 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
84
85 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
86 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
87
88 if (that != NULL)
89 for (auto &attr : that->attributes) {
90 if (attr.second->type != AST_CONSTANT)
91 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
92 cell->attributes[attr.first] = attr.second->asAttrConst();
93 }
94
95 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
96 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
97 cell->setPort("\\A", sig);
98
99 cell->parameters["\\Y_WIDTH"] = width;
100 cell->setPort("\\Y", wire);
101 sig = wire;
102 }
103
104 // helper function for creating RTLIL code for binary operations
105 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
106 {
107 std::stringstream sstr;
108 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
109
110 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
111 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
112
113 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
114 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
115
116 for (auto &attr : that->attributes) {
117 if (attr.second->type != AST_CONSTANT)
118 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
119 cell->attributes[attr.first] = attr.second->asAttrConst();
120 }
121
122 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
123 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
124
125 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
126 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
127
128 cell->setPort("\\A", left);
129 cell->setPort("\\B", right);
130
131 cell->parameters["\\Y_WIDTH"] = result_width;
132 cell->setPort("\\Y", wire);
133 return wire;
134 }
135
136 // helper function for creating RTLIL code for multiplexers
137 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
138 {
139 log_assert(cond.size() == 1);
140
141 std::stringstream sstr;
142 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
143
144 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
145 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
146
147 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
148 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
149
150 for (auto &attr : that->attributes) {
151 if (attr.second->type != AST_CONSTANT)
152 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
153 cell->attributes[attr.first] = attr.second->asAttrConst();
154 }
155
156 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
157
158 cell->setPort("\\A", right);
159 cell->setPort("\\B", left);
160 cell->setPort("\\S", cond);
161 cell->setPort("\\Y", wire);
162
163 return wire;
164 }
165
166 // helper class for converting AST always nodes to RTLIL processes
167 struct AST_INTERNAL::ProcessGenerator
168 {
169 // input and output structures
170 AstNode *always;
171 RTLIL::SigSpec initSyncSignals;
172 RTLIL::Process *proc;
173 RTLIL::SigSpec outputSignals;
174
175 // This always points to the RTLIL::CaseRule being filled at the moment
176 RTLIL::CaseRule *current_case;
177
178 // This map contains the replacement pattern to be used in the right hand side
179 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
180 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
181 // the value assigned in the first assignment. So when the first assignment is processed
182 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
183 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
184
185 // This map contains the replacement pattern to be used in the left hand side
186 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
187 // should not be connected to the signal foo. Instead it must be connected to the temporary
188 // signal that is used as input for the register that drives the signal foo.
189 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
190
191 // The code here generates a number of temporary signal for each output register. This
192 // map helps generating nice numbered names for all this temporary signals.
193 std::map<RTLIL::Wire*, int> new_temp_count;
194
195 // Buffer for generating the init action
196 RTLIL::SigSpec init_lvalue, init_rvalue;
197
198 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
199 {
200 // generate process and simple root case
201 proc = new RTLIL::Process;
202 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
203 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
204 for (auto &attr : always->attributes) {
205 if (attr.second->type != AST_CONSTANT)
206 log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
207 attr.first.c_str());
208 proc->attributes[attr.first] = attr.second->asAttrConst();
209 }
210 current_module->processes[proc->name] = proc;
211 current_case = &proc->root_case;
212
213 // create initial temporary signal for all output registers
214 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
215 collect_lvalues(subst_lvalue_from, always, true, true);
216 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
217 subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
218
219 bool found_global_syncs = false;
220 bool found_anyedge_syncs = false;
221 for (auto child : always->children)
222 {
223 if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
224 child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
225 found_global_syncs = true;
226 }
227 if (child->type == AST_EDGE) {
228 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock")
229 found_global_syncs = true;
230 else
231 found_anyedge_syncs = true;
232 }
233 }
234
235 if (found_anyedge_syncs) {
236 if (found_global_syncs)
237 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
238 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
239 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
240 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
241 }
242
243 // create syncs for the process
244 bool found_clocked_sync = false;
245 for (auto child : always->children)
246 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
247 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
248 child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
249 continue;
250 found_clocked_sync = true;
251 if (found_global_syncs || found_anyedge_syncs)
252 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
253 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
254 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
255 syncrule->signal = child->children[0]->genRTLIL();
256 if (GetSize(syncrule->signal) != 1)
257 log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
258 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
259 proc->syncs.push_back(syncrule);
260 }
261 if (proc->syncs.empty()) {
262 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
263 syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
264 syncrule->signal = RTLIL::SigSpec();
265 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
266 proc->syncs.push_back(syncrule);
267 }
268
269 // create initial assignments for the temporary signals
270 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
271 subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
272 } else {
273 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
274 }
275
276 // process the AST
277 for (auto child : always->children)
278 if (child->type == AST_BLOCK)
279 processAst(child);
280
281 if (initSyncSignals.size() > 0)
282 {
283 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
284 sync->type = RTLIL::SyncType::STi;
285 proc->syncs.push_back(sync);
286
287 log_assert(init_lvalue.size() == init_rvalue.size());
288
289 int offset = 0;
290 for (auto &init_lvalue_c : init_lvalue.chunks()) {
291 RTLIL::SigSpec lhs = init_lvalue_c;
292 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
293 remove_unwanted_lvalue_bits(lhs, rhs);
294 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
295 offset += lhs.size();
296 }
297 }
298
299 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
300 }
301
302 void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
303 {
304 RTLIL::SigSpec new_lhs, new_rhs;
305
306 log_assert(GetSize(lhs) == GetSize(rhs));
307 for (int i = 0; i < GetSize(lhs); i++) {
308 if (lhs[i].wire == nullptr)
309 continue;
310 new_lhs.append(lhs[i]);
311 new_rhs.append(rhs[i]);
312 }
313
314 lhs = new_lhs;
315 rhs = new_rhs;
316 }
317
318 // create new temporary signals
319 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
320 {
321 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
322
323 for (int i = 0; i < GetSize(chunks); i++)
324 {
325 RTLIL::SigChunk &chunk = chunks[i];
326 if (chunk.wire == NULL)
327 continue;
328
329 std::string wire_name;
330 do {
331 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
332 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
333 if (chunk.wire->name.str().find('$') != std::string::npos)
334 wire_name += stringf("$%d", autoidx++);
335 } while (current_module->wires_.count(wire_name) > 0);
336
337 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
338 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
339
340 chunk.wire = wire;
341 chunk.offset = 0;
342 }
343
344 return chunks;
345 }
346
347 // recursively traverse the AST an collect all assigned signals
348 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
349 {
350 switch (ast->type)
351 {
352 case AST_CASE:
353 for (auto child : ast->children)
354 if (child != ast->children[0]) {
355 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
356 collect_lvalues(reg, child, type_eq, type_le, false);
357 }
358 break;
359
360 case AST_COND:
361 case AST_CONDX:
362 case AST_CONDZ:
363 case AST_ALWAYS:
364 case AST_INITIAL:
365 for (auto child : ast->children)
366 if (child->type == AST_BLOCK)
367 collect_lvalues(reg, child, type_eq, type_le, false);
368 break;
369
370 case AST_BLOCK:
371 for (auto child : ast->children) {
372 if (child->type == AST_ASSIGN_EQ && type_eq)
373 reg.append(child->children[0]->genRTLIL());
374 if (child->type == AST_ASSIGN_LE && type_le)
375 reg.append(child->children[0]->genRTLIL());
376 if (child->type == AST_CASE || child->type == AST_BLOCK)
377 collect_lvalues(reg, child, type_eq, type_le, false);
378 }
379 break;
380
381 default:
382 log_abort();
383 }
384
385 if (run_sort_and_unify) {
386 std::set<RTLIL::SigBit> sorted_reg;
387 for (auto bit : reg)
388 if (bit.wire)
389 sorted_reg.insert(bit);
390 reg = RTLIL::SigSpec(sorted_reg);
391 }
392 }
393
394 // remove all assignments to the given signal pattern in a case and all its children.
395 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
396 // function is called to clean up the first two assignments as they are overwritten by
397 // the third assignment.
398 void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
399 {
400 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
401 it->first.remove2(pattern, &it->second);
402
403 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
404 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
405 removeSignalFromCaseTree(pattern, *it2);
406 }
407
408 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
409 // are avoided and the generated $mux cells have a more "natural" size.
410 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
411 {
412 if (inSyncRule && initSyncSignals.size() > 0) {
413 init_lvalue.append(lvalue.extract(initSyncSignals));
414 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
415 lvalue.remove2(initSyncSignals, &rvalue);
416 }
417 log_assert(lvalue.size() == rvalue.size());
418
419 int offset = 0;
420 for (auto &lvalue_c : lvalue.chunks()) {
421 RTLIL::SigSpec lhs = lvalue_c;
422 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
423 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
424 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
425 remove_unwanted_lvalue_bits(lhs, rhs);
426 actions.push_back(RTLIL::SigSig(lhs, rhs));
427 offset += lhs.size();
428 }
429 }
430
431 // recursively process the AST and fill the RTLIL::Process
432 void processAst(AstNode *ast)
433 {
434 switch (ast->type)
435 {
436 case AST_BLOCK:
437 for (auto child : ast->children)
438 processAst(child);
439 break;
440
441 case AST_ASSIGN_EQ:
442 case AST_ASSIGN_LE:
443 {
444 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
445 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
446
447 pool<SigBit> lvalue_sigbits;
448 for (int i = 0; i < GetSize(lvalue); i++) {
449 if (lvalue_sigbits.count(lvalue[i]) > 0) {
450 unmapped_lvalue.remove(i);
451 lvalue.remove(i);
452 rvalue.remove(i--);
453 } else
454 lvalue_sigbits.insert(lvalue[i]);
455 }
456
457 lvalue.replace(subst_lvalue_map.stdmap());
458
459 if (ast->type == AST_ASSIGN_EQ) {
460 for (int i = 0; i < GetSize(unmapped_lvalue); i++)
461 subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
462 }
463
464 removeSignalFromCaseTree(lvalue, current_case);
465 remove_unwanted_lvalue_bits(lvalue, rvalue);
466 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
467 }
468 break;
469
470 case AST_CASE:
471 {
472 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
473 sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
474 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
475 current_case->switches.push_back(sw);
476
477 for (auto &attr : ast->attributes) {
478 if (attr.second->type != AST_CONSTANT)
479 log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
480 sw->attributes[attr.first] = attr.second->asAttrConst();
481 }
482
483 RTLIL::SigSpec this_case_eq_lvalue;
484 collect_lvalues(this_case_eq_lvalue, ast, true, false);
485
486 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
487
488 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
489 this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
490
491 RTLIL::CaseRule *default_case = NULL;
492 RTLIL::CaseRule *last_generated_case = NULL;
493 for (auto child : ast->children)
494 {
495 if (child == ast->children[0])
496 continue;
497 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
498
499 subst_lvalue_map.save();
500 subst_rvalue_map.save();
501
502 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
503 subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
504
505 RTLIL::CaseRule *backup_case = current_case;
506 current_case = new RTLIL::CaseRule;
507 last_generated_case = current_case;
508 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
509 for (auto node : child->children) {
510 if (node->type == AST_DEFAULT)
511 default_case = current_case;
512 else if (node->type == AST_BLOCK)
513 processAst(node);
514 else
515 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
516 }
517 if (default_case != current_case)
518 sw->cases.push_back(current_case);
519 else
520 log_assert(current_case->compare.size() == 0);
521 current_case = backup_case;
522
523 subst_lvalue_map.restore();
524 subst_rvalue_map.restore();
525 }
526
527 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
528 last_generated_case->compare.clear();
529 } else {
530 if (default_case == NULL) {
531 default_case = new RTLIL::CaseRule;
532 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
533 }
534 sw->cases.push_back(default_case);
535 }
536
537 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
538 subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
539
540 this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
541 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
542 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
543 }
544 break;
545
546 case AST_WIRE:
547 log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
548 break;
549
550 case AST_ASSIGN:
551 log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
552 break;
553
554 case AST_PARAMETER:
555 case AST_LOCALPARAM:
556 log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
557 break;
558
559 case AST_NONE:
560 case AST_TCALL:
561 case AST_FOR:
562 break;
563
564 default:
565 // ast->dumpAst(NULL, "ast> ");
566 // current_ast_mod->dumpAst(NULL, "mod> ");
567 log_abort();
568 }
569 }
570 };
571
572 // detect sign and width of an expression
573 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
574 {
575 std::string type_name;
576 bool sub_sign_hint = true;
577 int sub_width_hint = -1;
578 int this_width = 0;
579 AstNode *range = NULL;
580 AstNode *id_ast = NULL;
581
582 bool local_found_real = false;
583 if (found_real == NULL)
584 found_real = &local_found_real;
585
586 switch (type)
587 {
588 case AST_CONSTANT:
589 width_hint = max(width_hint, int(bits.size()));
590 if (!is_signed)
591 sign_hint = false;
592 break;
593
594 case AST_REALVALUE:
595 *found_real = true;
596 width_hint = max(width_hint, 32);
597 break;
598
599 case AST_IDENTIFIER:
600 id_ast = id2ast;
601 if (id_ast == NULL && current_scope.count(str))
602 id_ast = current_scope.at(str);
603 if (!id_ast)
604 log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
605 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
606 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
607 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
608 } else
609 if (id_ast->children[0]->type != AST_CONSTANT)
610 while (id_ast->simplify(true, false, false, 1, -1, false, true)) { }
611 if (id_ast->children[0]->type == AST_CONSTANT)
612 this_width = id_ast->children[0]->bits.size();
613 else
614 log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
615 if (children.size() != 0)
616 range = children[0];
617 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
618 if (!id_ast->range_valid) {
619 if (id_ast->type == AST_AUTOWIRE)
620 this_width = 1;
621 else {
622 // current_ast_mod->dumpAst(NULL, "mod> ");
623 // log("---\n");
624 // id_ast->dumpAst(NULL, "decl> ");
625 // dumpAst(NULL, "ref> ");
626 log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
627 }
628 } else {
629 this_width = id_ast->range_left - id_ast->range_right + 1;
630 if (children.size() != 0)
631 range = children[0];
632 }
633 } else if (id_ast->type == AST_GENVAR) {
634 this_width = 32;
635 } else if (id_ast->type == AST_MEMORY) {
636 if (!id_ast->children[0]->range_valid)
637 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
638 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
639 } else
640 log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
641 if (range) {
642 if (range->children.size() == 1)
643 this_width = 1;
644 else if (!range->range_valid) {
645 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
646 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
647 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
648 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
649 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
650 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
651 this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
652 delete left_at_zero_ast;
653 delete right_at_zero_ast;
654 } else
655 this_width = range->range_left - range->range_right + 1;
656 sign_hint = false;
657 }
658 width_hint = max(width_hint, this_width);
659 if (!id_ast->is_signed)
660 sign_hint = false;
661 break;
662
663 case AST_TO_BITS:
664 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
665 if (children[0]->type != AST_CONSTANT)
666 log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
667 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
668 width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
669 break;
670
671 case AST_TO_SIGNED:
672 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
673 break;
674
675 case AST_TO_UNSIGNED:
676 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
677 sign_hint = false;
678 break;
679
680 case AST_CONCAT:
681 for (auto child : children) {
682 sub_width_hint = 0;
683 sub_sign_hint = true;
684 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
685 this_width += sub_width_hint;
686 }
687 width_hint = max(width_hint, this_width);
688 sign_hint = false;
689 break;
690
691 case AST_REPLICATE:
692 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
693 if (children[0]->type != AST_CONSTANT)
694 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
695 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
696 width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
697 sign_hint = false;
698 break;
699
700 case AST_NEG:
701 case AST_BIT_NOT:
702 case AST_POS:
703 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
704 break;
705
706 case AST_BIT_AND:
707 case AST_BIT_OR:
708 case AST_BIT_XOR:
709 case AST_BIT_XNOR:
710 for (auto child : children)
711 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
712 break;
713
714 case AST_REDUCE_AND:
715 case AST_REDUCE_OR:
716 case AST_REDUCE_XOR:
717 case AST_REDUCE_XNOR:
718 case AST_REDUCE_BOOL:
719 width_hint = max(width_hint, 1);
720 sign_hint = false;
721 break;
722
723 case AST_SHIFT_LEFT:
724 case AST_SHIFT_RIGHT:
725 case AST_SHIFT_SLEFT:
726 case AST_SHIFT_SRIGHT:
727 case AST_POW:
728 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
729 break;
730
731 case AST_LT:
732 case AST_LE:
733 case AST_EQ:
734 case AST_NE:
735 case AST_EQX:
736 case AST_NEX:
737 case AST_GE:
738 case AST_GT:
739 width_hint = max(width_hint, 1);
740 sign_hint = false;
741 break;
742
743 case AST_ADD:
744 case AST_SUB:
745 case AST_MUL:
746 case AST_DIV:
747 case AST_MOD:
748 for (auto child : children)
749 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
750 break;
751
752 case AST_LOGIC_AND:
753 case AST_LOGIC_OR:
754 case AST_LOGIC_NOT:
755 width_hint = max(width_hint, 1);
756 sign_hint = false;
757 break;
758
759 case AST_TERNARY:
760 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
761 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
762 break;
763
764 case AST_MEMRD:
765 if (!id2ast->is_signed)
766 sign_hint = false;
767 if (!id2ast->children[0]->range_valid)
768 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
769 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
770 width_hint = max(width_hint, this_width);
771 break;
772
773 case AST_FCALL:
774 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
775 if (GetSize(children) == 1) {
776 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
777 if (children[0]->type != AST_CONSTANT)
778 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
779 RTLIL::unescape_id(str).c_str());
780 width_hint = max(width_hint, int(children[0]->asInt(true)));
781 }
782 break;
783 }
784 if (str == "\\$past") {
785 if (GetSize(children) > 0) {
786 sub_width_hint = 0;
787 sub_sign_hint = true;
788 children.at(0)->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
789 width_hint = max(width_hint, sub_width_hint);
790 sign_hint = false;
791 }
792 break;
793 }
794 /* fall through */
795
796 // everything should have been handled above -> print error if not.
797 default:
798 for (auto f : log_files)
799 current_ast_mod->dumpAst(f, "verilog-ast> ");
800 log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
801 }
802
803 if (*found_real)
804 sign_hint = true;
805 }
806
807 // detect sign and width of an expression
808 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
809 {
810 width_hint = -1;
811 sign_hint = true;
812 if (found_real)
813 *found_real = false;
814 detectSignWidthWorker(width_hint, sign_hint, found_real);
815 }
816
817 // create RTLIL from an AST node
818 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
819 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
820 //
821 // note that this function is influenced by a number of global variables that might be set when
822 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
823 // larger expressions into a netlist of cells.
824 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
825 {
826 // in the following big switch() statement there are some uses of
827 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
828 // cases this variable is used to hold the type of the cell that should
829 // be instantiated for this type of AST node.
830 std::string type_name;
831
832 current_filename = filename;
833 set_line_num(linenum);
834
835 switch (type)
836 {
837 // simply ignore this nodes.
838 // they are either leftovers from simplify() or are referenced by other nodes
839 // and are only accessed here thru this references
840 case AST_NONE:
841 case AST_TASK:
842 case AST_FUNCTION:
843 case AST_DPI_FUNCTION:
844 case AST_AUTOWIRE:
845 case AST_LOCALPARAM:
846 case AST_DEFPARAM:
847 case AST_GENVAR:
848 case AST_GENFOR:
849 case AST_GENBLOCK:
850 case AST_GENIF:
851 case AST_GENCASE:
852 case AST_PACKAGE:
853 case AST_MODPORT:
854 case AST_MODPORTMEMBER:
855 break;
856 case AST_INTERFACEPORT: {
857 // If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
858 // This is used by the hierarchy pass to know when it can replace interface connection with the individual
859 // signals.
860 RTLIL::Wire *wire = current_module->addWire(str, 1);
861 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
862 wire->start_offset = 0;
863 wire->port_id = port_id;
864 wire->port_input = true;
865 wire->port_output = true;
866 wire->set_bool_attribute("\\is_interface");
867 if (children.size() > 0) {
868 for(size_t i=0; i<children.size();i++) {
869 if(children[i]->type == AST_INTERFACEPORTTYPE) {
870 std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
871 wire->attributes["\\interface_type"] = res.first;
872 if (res.second != "")
873 wire->attributes["\\interface_modport"] = res.second;
874 break;
875 }
876 }
877 }
878 wire->upto = 0;
879 }
880 break;
881 case AST_INTERFACEPORTTYPE:
882 break;
883
884 // remember the parameter, needed for example in techmap
885 case AST_PARAMETER:
886 current_module->avail_parameters.insert(str);
887 break;
888
889 // create an RTLIL::Wire for an AST_WIRE node
890 case AST_WIRE: {
891 if (current_module->wires_.count(str) != 0)
892 log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str());
893 if (!range_valid)
894 log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
895
896 log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
897
898 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
899 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
900 wire->start_offset = range_right;
901 wire->port_id = port_id;
902 wire->port_input = is_input;
903 wire->port_output = is_output;
904 wire->upto = range_swapped;
905
906 for (auto &attr : attributes) {
907 if (attr.second->type != AST_CONSTANT)
908 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
909 wire->attributes[attr.first] = attr.second->asAttrConst();
910 }
911 }
912 break;
913
914 // create an RTLIL::Memory for an AST_MEMORY node
915 case AST_MEMORY: {
916 if (current_module->memories.count(str) != 0)
917 log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str());
918
919 log_assert(children.size() >= 2);
920 log_assert(children[0]->type == AST_RANGE);
921 log_assert(children[1]->type == AST_RANGE);
922
923 if (!children[0]->range_valid || !children[1]->range_valid)
924 log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str());
925
926 RTLIL::Memory *memory = new RTLIL::Memory;
927 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
928 memory->name = str;
929 memory->width = children[0]->range_left - children[0]->range_right + 1;
930 if (children[1]->range_right < children[1]->range_left) {
931 memory->start_offset = children[1]->range_right;
932 memory->size = children[1]->range_left - children[1]->range_right + 1;
933 } else {
934 memory->start_offset = children[1]->range_left;
935 memory->size = children[1]->range_right - children[1]->range_left + 1;
936 }
937 current_module->memories[memory->name] = memory;
938
939 for (auto &attr : attributes) {
940 if (attr.second->type != AST_CONSTANT)
941 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
942 memory->attributes[attr.first] = attr.second->asAttrConst();
943 }
944 }
945 break;
946
947 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
948 case AST_CONSTANT:
949 case AST_REALVALUE:
950 {
951 if (width_hint < 0)
952 detectSignWidth(width_hint, sign_hint);
953 is_signed = sign_hint;
954
955 if (type == AST_CONSTANT)
956 return RTLIL::SigSpec(bitsAsConst());
957
958 RTLIL::SigSpec sig = realAsConst(width_hint);
959 log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
960 return sig;
961 }
962
963 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
964 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
965 // shifter cell is created and the output signal of this cell is returned
966 case AST_IDENTIFIER:
967 {
968 RTLIL::Wire *wire = NULL;
969 RTLIL::SigChunk chunk;
970 bool is_interface = false;
971
972 int add_undef_bits_msb = 0;
973 int add_undef_bits_lsb = 0;
974
975 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
976 RTLIL::Wire *wire = current_module->addWire(str);
977 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
978 wire->name = str;
979 if (flag_autowire)
980 log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
981 else
982 log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
983 }
984 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
985 if (id2ast->children[0]->type != AST_CONSTANT)
986 log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str());
987 chunk = RTLIL::Const(id2ast->children[0]->bits);
988 goto use_const_chunk;
989 }
990 else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
991 RTLIL::Wire *current_wire = current_module->wire(str);
992 if (current_wire->get_bool_attribute("\\is_interface"))
993 is_interface = true;
994 // Ignore
995 }
996 // If an identifier is found that is not already known, assume that it is an interface:
997 else if (1) { // FIXME: Check if sv_mode first?
998 is_interface = true;
999 }
1000 else {
1001 log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
1002 }
1003
1004 if (id2ast->type == AST_MEMORY)
1005 log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
1006
1007 // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
1008 // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
1009 // with the individual signals:
1010 if (is_interface) {
1011 RTLIL::Wire *dummy_wire;
1012 std::string dummy_wire_name = "$dummywireforinterface" + str;
1013 if (current_module->wires_.count(dummy_wire_name))
1014 dummy_wire = current_module->wires_[dummy_wire_name];
1015 else {
1016 dummy_wire = current_module->addWire(dummy_wire_name);
1017 dummy_wire->set_bool_attribute("\\is_interface");
1018 }
1019 RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
1020 return tmp;
1021 }
1022
1023 wire = current_module->wires_[str];
1024 chunk.wire = wire;
1025 chunk.width = wire->width;
1026 chunk.offset = 0;
1027
1028 use_const_chunk:
1029 if (children.size() != 0) {
1030 if (children[0]->type != AST_RANGE)
1031 log_file_error(filename, linenum, "Single range expected.\n");
1032 int source_width = id2ast->range_left - id2ast->range_right + 1;
1033 int source_offset = id2ast->range_right;
1034 if (!children[0]->range_valid) {
1035 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
1036 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
1037 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1038 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1039 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
1040 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
1041 int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
1042 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
1043 children[0]->children[1]->clone() : children[0]->children[0]->clone());
1044 fake_ast->children[0]->delete_children();
1045 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
1046 if (id2ast->range_right != 0) {
1047 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
1048 fake_ast->children[1]->is_signed = true;
1049 }
1050 if (id2ast->range_swapped) {
1051 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
1052 fake_ast->children[1]->is_signed = true;
1053 }
1054 if (GetSize(shift_val) >= 32)
1055 fake_ast->children[1]->is_signed = true;
1056 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
1057 delete left_at_zero_ast;
1058 delete right_at_zero_ast;
1059 delete fake_ast;
1060 return sig;
1061 } else {
1062 chunk.width = children[0]->range_left - children[0]->range_right + 1;
1063 chunk.offset = children[0]->range_right - source_offset;
1064 if (id2ast->range_swapped)
1065 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
1066 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
1067 if (chunk.width == 1)
1068 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
1069 str.c_str());
1070 else
1071 log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
1072 children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
1073 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
1074 } else {
1075 if (chunk.width + chunk.offset > source_width) {
1076 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
1077 chunk.width -= add_undef_bits_msb;
1078 }
1079 if (chunk.offset < 0) {
1080 add_undef_bits_lsb = -chunk.offset;
1081 chunk.width -= add_undef_bits_lsb;
1082 chunk.offset += add_undef_bits_lsb;
1083 }
1084 if (add_undef_bits_lsb)
1085 log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
1086 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
1087 if (add_undef_bits_msb)
1088 log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
1089 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
1090 }
1091 }
1092 }
1093
1094 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
1095
1096 if (genRTLIL_subst_ptr)
1097 sig.replace(*genRTLIL_subst_ptr);
1098
1099 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
1100 return sig;
1101 }
1102
1103 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
1104 case AST_TO_SIGNED:
1105 case AST_TO_UNSIGNED: {
1106 RTLIL::SigSpec sig = children[0]->genRTLIL();
1107 if (sig.size() < width_hint)
1108 sig.extend_u0(width_hint, sign_hint);
1109 is_signed = sign_hint;
1110 return sig;
1111 }
1112
1113 // concatenation of signals can be done directly using RTLIL::SigSpec
1114 case AST_CONCAT: {
1115 RTLIL::SigSpec sig;
1116 for (auto it = children.begin(); it != children.end(); it++)
1117 sig.append((*it)->genRTLIL());
1118 if (sig.size() < width_hint)
1119 sig.extend_u0(width_hint, false);
1120 return sig;
1121 }
1122
1123 // replication of signals can be done directly using RTLIL::SigSpec
1124 case AST_REPLICATE: {
1125 RTLIL::SigSpec left = children[0]->genRTLIL();
1126 RTLIL::SigSpec right = children[1]->genRTLIL();
1127 if (!left.is_fully_const())
1128 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
1129 int count = left.as_int();
1130 RTLIL::SigSpec sig;
1131 for (int i = 0; i < count; i++)
1132 sig.append(right);
1133 if (sig.size() < width_hint)
1134 sig.extend_u0(width_hint, false);
1135 is_signed = false;
1136 return sig;
1137 }
1138
1139 // generate cells for unary operations: $not, $pos, $neg
1140 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1141 if (0) { case AST_POS: type_name = "$pos"; }
1142 if (0) { case AST_NEG: type_name = "$neg"; }
1143 {
1144 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1145 is_signed = children[0]->is_signed;
1146 int width = arg.size();
1147 if (width_hint > 0) {
1148 width = width_hint;
1149 widthExtend(this, arg, width, is_signed);
1150 }
1151 return uniop2rtlil(this, type_name, width, arg);
1152 }
1153
1154 // generate cells for binary operations: $and, $or, $xor, $xnor
1155 if (0) { case AST_BIT_AND: type_name = "$and"; }
1156 if (0) { case AST_BIT_OR: type_name = "$or"; }
1157 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1158 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1159 {
1160 if (width_hint < 0)
1161 detectSignWidth(width_hint, sign_hint);
1162 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1163 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1164 int width = max(left.size(), right.size());
1165 if (width_hint > 0)
1166 width = width_hint;
1167 is_signed = children[0]->is_signed && children[1]->is_signed;
1168 return binop2rtlil(this, type_name, width, left, right);
1169 }
1170
1171 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1172 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1173 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1174 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1175 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1176 {
1177 RTLIL::SigSpec arg = children[0]->genRTLIL();
1178 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
1179 return sig;
1180 }
1181
1182 // generate cells for unary operations: $reduce_bool
1183 // (this is actually just an $reduce_or, but for clarity a different cell type is used)
1184 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1185 {
1186 RTLIL::SigSpec arg = children[0]->genRTLIL();
1187 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
1188 return sig;
1189 }
1190
1191 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1192 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1193 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1194 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1195 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1196 {
1197 if (width_hint < 0)
1198 detectSignWidth(width_hint, sign_hint);
1199 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1200 RTLIL::SigSpec right = children[1]->genRTLIL();
1201 int width = width_hint > 0 ? width_hint : left.size();
1202 is_signed = children[0]->is_signed;
1203 return binop2rtlil(this, type_name, width, left, right);
1204 }
1205
1206 // generate cells for binary operations: $pow
1207 case AST_POW:
1208 {
1209 int right_width;
1210 bool right_signed;
1211 children[1]->detectSignWidth(right_width, right_signed);
1212 if (width_hint < 0)
1213 detectSignWidth(width_hint, sign_hint);
1214 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1215 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1216 int width = width_hint > 0 ? width_hint : left.size();
1217 is_signed = children[0]->is_signed;
1218 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1219 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1220 return binop2rtlil(this, "$pow", width, left, right);
1221 }
1222
1223 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1224 if (0) { case AST_LT: type_name = "$lt"; }
1225 if (0) { case AST_LE: type_name = "$le"; }
1226 if (0) { case AST_EQ: type_name = "$eq"; }
1227 if (0) { case AST_NE: type_name = "$ne"; }
1228 if (0) { case AST_EQX: type_name = "$eqx"; }
1229 if (0) { case AST_NEX: type_name = "$nex"; }
1230 if (0) { case AST_GE: type_name = "$ge"; }
1231 if (0) { case AST_GT: type_name = "$gt"; }
1232 {
1233 int width = max(width_hint, 1);
1234 width_hint = -1, sign_hint = true;
1235 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1236 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1237 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1238 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1239 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1240 return sig;
1241 }
1242
1243 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1244 if (0) { case AST_ADD: type_name = "$add"; }
1245 if (0) { case AST_SUB: type_name = "$sub"; }
1246 if (0) { case AST_MUL: type_name = "$mul"; }
1247 if (0) { case AST_DIV: type_name = "$div"; }
1248 if (0) { case AST_MOD: type_name = "$mod"; }
1249 {
1250 if (width_hint < 0)
1251 detectSignWidth(width_hint, sign_hint);
1252 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1253 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1254 #if 0
1255 int width = max(left.size(), right.size());
1256 if (width > width_hint && width_hint > 0)
1257 width = width_hint;
1258 if (width < width_hint) {
1259 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1260 width++;
1261 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1262 width = width_hint;
1263 if (type == AST_MUL)
1264 width = min(left.size() + right.size(), width_hint);
1265 }
1266 #else
1267 int width = max(max(left.size(), right.size()), width_hint);
1268 #endif
1269 is_signed = children[0]->is_signed && children[1]->is_signed;
1270 return binop2rtlil(this, type_name, width, left, right);
1271 }
1272
1273 // generate cells for binary operations: $logic_and, $logic_or
1274 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1275 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1276 {
1277 RTLIL::SigSpec left = children[0]->genRTLIL();
1278 RTLIL::SigSpec right = children[1]->genRTLIL();
1279 return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
1280 }
1281
1282 // generate cells for unary operations: $logic_not
1283 case AST_LOGIC_NOT:
1284 {
1285 RTLIL::SigSpec arg = children[0]->genRTLIL();
1286 return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
1287 }
1288
1289 // generate multiplexer for ternary operator (aka ?:-operator)
1290 case AST_TERNARY:
1291 {
1292 if (width_hint < 0)
1293 detectSignWidth(width_hint, sign_hint);
1294
1295 RTLIL::SigSpec cond = children[0]->genRTLIL();
1296 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1297 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1298
1299 if (cond.size() > 1)
1300 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1301
1302 int width = max(val1.size(), val2.size());
1303 is_signed = children[1]->is_signed && children[2]->is_signed;
1304 widthExtend(this, val1, width, is_signed);
1305 widthExtend(this, val2, width, is_signed);
1306
1307 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1308
1309 if (sig.size() < width_hint)
1310 sig.extend_u0(width_hint, sign_hint);
1311 return sig;
1312 }
1313
1314 // generate $memrd cells for memory read ports
1315 case AST_MEMRD:
1316 {
1317 std::stringstream sstr;
1318 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1319
1320 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1321 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1322
1323 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1324 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1325
1326 int mem_width, mem_size, addr_bits;
1327 is_signed = id2ast->is_signed;
1328 id2ast->meminfo(mem_width, mem_size, addr_bits);
1329
1330 RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
1331
1332 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1333 cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1334 cell->setPort("\\ADDR", addr_sig);
1335 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1336
1337 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1338 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1339 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1340
1341 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1342 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1343 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1344
1345 if (!sign_hint)
1346 is_signed = false;
1347
1348 return RTLIL::SigSpec(wire);
1349 }
1350
1351 // generate $memwr cells for memory write ports
1352 case AST_MEMWR:
1353 case AST_MEMINIT:
1354 {
1355 std::stringstream sstr;
1356 sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1357
1358 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
1359 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1360
1361 int mem_width, mem_size, addr_bits;
1362 id2ast->meminfo(mem_width, mem_size, addr_bits);
1363
1364 int num_words = 1;
1365 if (type == AST_MEMINIT) {
1366 if (children[2]->type != AST_CONSTANT)
1367 log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
1368 num_words = int(children[2]->asInt(false));
1369 cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
1370 }
1371
1372 SigSpec addr_sig = children[0]->genRTLIL();
1373
1374 cell->setPort("\\ADDR", addr_sig);
1375 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
1376
1377 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1378 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1379 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1380
1381 if (type == AST_MEMWR) {
1382 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1383 cell->setPort("\\EN", children[2]->genRTLIL());
1384 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1385 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1386 }
1387
1388 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1389 }
1390 break;
1391
1392 // generate $assert cells
1393 case AST_ASSERT:
1394 case AST_ASSUME:
1395 case AST_LIVE:
1396 case AST_FAIR:
1397 case AST_COVER:
1398 {
1399 const char *celltype = nullptr;
1400 if (type == AST_ASSERT) celltype = "$assert";
1401 if (type == AST_ASSUME) celltype = "$assume";
1402 if (type == AST_LIVE) celltype = "$live";
1403 if (type == AST_FAIR) celltype = "$fair";
1404 if (type == AST_COVER) celltype = "$cover";
1405
1406 log_assert(children.size() == 2);
1407
1408 RTLIL::SigSpec check = children[0]->genRTLIL();
1409 if (GetSize(check) != 1)
1410 check = current_module->ReduceBool(NEW_ID, check);
1411
1412 RTLIL::SigSpec en = children[1]->genRTLIL();
1413 if (GetSize(en) != 1)
1414 en = current_module->ReduceBool(NEW_ID, en);
1415
1416 IdString cellname;
1417 if (str.empty()) {
1418 std::stringstream sstr;
1419 sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
1420 cellname = sstr.str();
1421 } else {
1422 cellname = str;
1423 }
1424
1425 RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
1426 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1427
1428 for (auto &attr : attributes) {
1429 if (attr.second->type != AST_CONSTANT)
1430 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
1431 cell->attributes[attr.first] = attr.second->asAttrConst();
1432 }
1433
1434 cell->setPort("\\A", check);
1435 cell->setPort("\\EN", en);
1436 }
1437 break;
1438
1439 // add entries to current_module->connections for assignments (outside of always blocks)
1440 case AST_ASSIGN:
1441 {
1442 RTLIL::SigSpec left = children[0]->genRTLIL();
1443 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1444 if (left.has_const()) {
1445 RTLIL::SigSpec new_left, new_right;
1446 for (int i = 0; i < GetSize(left); i++)
1447 if (left[i].wire) {
1448 new_left.append(left[i]);
1449 new_right.append(right[i]);
1450 }
1451 log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
1452 " old assignment: %s = %s\n new assignment: %s = %s.\n",
1453 log_signal(left), log_signal(right),
1454 log_signal(new_left), log_signal(new_right));
1455 left = new_left;
1456 right = new_right;
1457 }
1458 current_module->connect(RTLIL::SigSig(left, right));
1459 }
1460 break;
1461
1462 // create an RTLIL::Cell for an AST_CELL
1463 case AST_CELL:
1464 {
1465 int port_counter = 0, para_counter = 0;
1466
1467 if (current_module->count_id(str) != 0)
1468 log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
1469
1470 RTLIL::Cell *cell = current_module->addCell(str, "");
1471 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1472 // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
1473 cell->set_bool_attribute("\\module_not_derived");
1474
1475 for (auto it = children.begin(); it != children.end(); it++) {
1476 AstNode *child = *it;
1477 if (child->type == AST_CELLTYPE) {
1478 cell->type = child->str;
1479 if (flag_icells && cell->type.substr(0, 2) == "\\$")
1480 cell->type = cell->type.substr(1);
1481 continue;
1482 }
1483 if (child->type == AST_PARASET) {
1484 IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
1485 if (child->children[0]->type == AST_REALVALUE) {
1486 log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
1487 log_id(cell), log_id(paraname), child->children[0]->realvalue);
1488 auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
1489 strnode->cloneInto(child->children[0]);
1490 delete strnode;
1491 }
1492 if (child->children[0]->type != AST_CONSTANT)
1493 log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
1494 log_id(cell), log_id(paraname));
1495 cell->parameters[paraname] = child->children[0]->asParaConst();
1496 continue;
1497 }
1498 if (child->type == AST_ARGUMENT) {
1499 RTLIL::SigSpec sig;
1500 if (child->children.size() > 0)
1501 sig = child->children[0]->genRTLIL();
1502 if (child->str.size() == 0) {
1503 char buf[100];
1504 snprintf(buf, 100, "$%d", ++port_counter);
1505 cell->setPort(buf, sig);
1506 } else {
1507 cell->setPort(child->str, sig);
1508 }
1509 continue;
1510 }
1511 log_abort();
1512 }
1513 for (auto &attr : attributes) {
1514 if (attr.second->type != AST_CONSTANT)
1515 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
1516 cell->attributes[attr.first] = attr.second->asAttrConst();
1517 }
1518 }
1519 break;
1520
1521 // use ProcessGenerator for always blocks
1522 case AST_ALWAYS: {
1523 AstNode *always = this->clone();
1524 ProcessGenerator generator(always);
1525 ignoreThisSignalsInInitial.append(generator.outputSignals);
1526 delete always;
1527 } break;
1528
1529 case AST_INITIAL: {
1530 AstNode *always = this->clone();
1531 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1532 delete always;
1533 } break;
1534
1535 case AST_FCALL: {
1536 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
1537 {
1538 string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
1539 int width = width_hint;
1540
1541 if (GetSize(children) > 1)
1542 log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
1543 RTLIL::unescape_id(str).c_str(), GetSize(children));
1544
1545 if (GetSize(children) == 1) {
1546 if (children[0]->type != AST_CONSTANT)
1547 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
1548 RTLIL::unescape_id(str).c_str());
1549 width = children[0]->asInt(true);
1550 }
1551
1552 if (width <= 0)
1553 log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
1554
1555 Cell *cell = current_module->addCell(myid, str.substr(1));
1556 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1557 cell->parameters["\\WIDTH"] = width;
1558
1559 if (attributes.count("\\reg")) {
1560 auto &attr = attributes.at("\\reg");
1561 if (attr->type != AST_CONSTANT)
1562 log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
1563 cell->attributes["\\reg"] = attr->asAttrConst();
1564 }
1565
1566 Wire *wire = current_module->addWire(myid + "_wire", width);
1567 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1568 cell->setPort("\\Y", wire);
1569
1570 is_signed = sign_hint;
1571 return SigSpec(wire);
1572 }
1573 } /* fall through */
1574
1575 // everything should have been handled above -> print error if not.
1576 default:
1577 for (auto f : log_files)
1578 current_ast_mod->dumpAst(f, "verilog-ast> ");
1579 type_name = type2str(type);
1580 log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
1581 }
1582
1583 return RTLIL::SigSpec();
1584 }
1585
1586 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1587 // signals must be substituted before being used as input values (used by ProcessGenerator)
1588 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1589 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1590 {
1591 const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1592
1593 if (new_subst_ptr)
1594 genRTLIL_subst_ptr = new_subst_ptr;
1595
1596 bool sign_hint = true;
1597 int width_hint = width;
1598 detectSignWidthWorker(width_hint, sign_hint);
1599 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1600
1601 genRTLIL_subst_ptr = backup_subst_ptr;
1602
1603 if (width >= 0)
1604 sig.extend_u0(width, is_signed);
1605
1606 return sig;
1607 }
1608
1609 YOSYS_NAMESPACE_END