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Merge pull request #674 from rubund/feature/svinterface_at_top
[yosys.git] / frontends / ast / genrtlil.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * ---
19 *
20 * This is the AST frontend library.
21 *
22 * The AST frontend library is not a frontend on it's own but provides a
23 * generic abstract syntax tree (AST) abstraction for HDL code and can be
24 * used by HDL frontends. See "ast.h" for an overview of the API and the
25 * Verilog frontend for an usage example.
26 *
27 */
28
29 #include "kernel/log.h"
30 #include "kernel/utils.h"
31 #include "libs/sha1/sha1.h"
32 #include "ast.h"
33
34 #include <sstream>
35 #include <stdarg.h>
36 #include <algorithm>
37
38 YOSYS_NAMESPACE_BEGIN
39
40 using namespace AST;
41 using namespace AST_INTERNAL;
42
43 // helper function for creating RTLIL code for unary operations
44 static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
45 {
46 std::stringstream sstr;
47 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
48
49 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
50 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
51
52 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
53 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
54
55 if (gen_attributes)
56 for (auto &attr : that->attributes) {
57 if (attr.second->type != AST_CONSTANT)
58 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
59 attr.first.c_str());
60 cell->attributes[attr.first] = attr.second->asAttrConst();
61 }
62
63 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
64 cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size());
65 cell->setPort("\\A", arg);
66
67 cell->parameters["\\Y_WIDTH"] = result_width;
68 cell->setPort("\\Y", wire);
69 return wire;
70 }
71
72 // helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
73 static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_signed)
74 {
75 if (width <= sig.size()) {
76 sig.extend_u0(width, is_signed);
77 return;
78 }
79
80 std::stringstream sstr;
81 sstr << "$extend" << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
82
83 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
84 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
85
86 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
87 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
88
89 if (that != NULL)
90 for (auto &attr : that->attributes) {
91 if (attr.second->type != AST_CONSTANT)
92 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
93 attr.first.c_str());
94 cell->attributes[attr.first] = attr.second->asAttrConst();
95 }
96
97 cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed);
98 cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size());
99 cell->setPort("\\A", sig);
100
101 cell->parameters["\\Y_WIDTH"] = width;
102 cell->setPort("\\Y", wire);
103 sig = wire;
104 }
105
106 // helper function for creating RTLIL code for binary operations
107 static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
108 {
109 std::stringstream sstr;
110 sstr << type << "$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
111
112 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
113 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
114
115 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
116 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
117
118 for (auto &attr : that->attributes) {
119 if (attr.second->type != AST_CONSTANT)
120 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
121 attr.first.c_str());
122 cell->attributes[attr.first] = attr.second->asAttrConst();
123 }
124
125 cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed);
126 cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed);
127
128 cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size());
129 cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size());
130
131 cell->setPort("\\A", left);
132 cell->setPort("\\B", right);
133
134 cell->parameters["\\Y_WIDTH"] = result_width;
135 cell->setPort("\\Y", wire);
136 return wire;
137 }
138
139 // helper function for creating RTLIL code for multiplexers
140 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
141 {
142 log_assert(cond.size() == 1);
143
144 std::stringstream sstr;
145 sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (autoidx++);
146
147 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
148 cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
149
150 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
151 wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
152
153 for (auto &attr : that->attributes) {
154 if (attr.second->type != AST_CONSTANT)
155 log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
156 attr.first.c_str());
157 cell->attributes[attr.first] = attr.second->asAttrConst();
158 }
159
160 cell->parameters["\\WIDTH"] = RTLIL::Const(left.size());
161
162 cell->setPort("\\A", right);
163 cell->setPort("\\B", left);
164 cell->setPort("\\S", cond);
165 cell->setPort("\\Y", wire);
166
167 return wire;
168 }
169
170 // helper class for converting AST always nodes to RTLIL processes
171 struct AST_INTERNAL::ProcessGenerator
172 {
173 // input and output structures
174 AstNode *always;
175 RTLIL::SigSpec initSyncSignals;
176 RTLIL::Process *proc;
177 RTLIL::SigSpec outputSignals;
178
179 // This always points to the RTLIL::CaseRule being filled at the moment
180 RTLIL::CaseRule *current_case;
181
182 // This map contains the replacement pattern to be used in the right hand side
183 // of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
184 // hand side of the 2nd assignment needs to be replace with the temporary signal holding
185 // the value assigned in the first assignment. So when the first assignment is processed
186 // the according information is appended to subst_rvalue_from and subst_rvalue_to.
187 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
188
189 // This map contains the replacement pattern to be used in the left hand side
190 // of an assignment. E.g. in the code "always @(posedge clk) foo <= bar" the signal bar
191 // should not be connected to the signal foo. Instead it must be connected to the temporary
192 // signal that is used as input for the register that drives the signal foo.
193 stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
194
195 // The code here generates a number of temporary signal for each output register. This
196 // map helps generating nice numbered names for all this temporary signals.
197 std::map<RTLIL::Wire*, int> new_temp_count;
198
199 // Buffer for generating the init action
200 RTLIL::SigSpec init_lvalue, init_rvalue;
201
202 ProcessGenerator(AstNode *always, RTLIL::SigSpec initSyncSignalsArg = RTLIL::SigSpec()) : always(always), initSyncSignals(initSyncSignalsArg)
203 {
204 // generate process and simple root case
205 proc = new RTLIL::Process;
206 proc->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
207 proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
208 for (auto &attr : always->attributes) {
209 if (attr.second->type != AST_CONSTANT)
210 log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
211 attr.first.c_str());
212 proc->attributes[attr.first] = attr.second->asAttrConst();
213 }
214 current_module->processes[proc->name] = proc;
215 current_case = &proc->root_case;
216
217 // create initial temporary signal for all output registers
218 RTLIL::SigSpec subst_lvalue_from, subst_lvalue_to;
219 collect_lvalues(subst_lvalue_from, always, true, true);
220 subst_lvalue_to = new_temp_signal(subst_lvalue_from);
221 subst_lvalue_map = subst_lvalue_from.to_sigbit_map(subst_lvalue_to);
222
223 bool found_global_syncs = false;
224 bool found_anyedge_syncs = false;
225 for (auto child : always->children)
226 {
227 if ((child->type == AST_POSEDGE || child->type == AST_NEGEDGE) && GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER &&
228 child->children.at(0)->id2ast && child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk")) {
229 found_global_syncs = true;
230 }
231 if (child->type == AST_EDGE) {
232 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->str == "\\$global_clock")
233 found_global_syncs = true;
234 else
235 found_anyedge_syncs = true;
236 }
237 }
238
239 if (found_anyedge_syncs) {
240 if (found_global_syncs)
241 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
242 log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
243 log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
244 log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
245 }
246
247 // create syncs for the process
248 bool found_clocked_sync = false;
249 for (auto child : always->children)
250 if (child->type == AST_POSEDGE || child->type == AST_NEGEDGE) {
251 if (GetSize(child->children) == 1 && child->children.at(0)->type == AST_IDENTIFIER && child->children.at(0)->id2ast &&
252 child->children.at(0)->id2ast->type == AST_WIRE && child->children.at(0)->id2ast->get_bool_attribute("\\gclk"))
253 continue;
254 found_clocked_sync = true;
255 if (found_global_syncs || found_anyedge_syncs)
256 log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
257 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
258 syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
259 syncrule->signal = child->children[0]->genRTLIL();
260 if (GetSize(syncrule->signal) != 1)
261 log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
262 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
263 proc->syncs.push_back(syncrule);
264 }
265 if (proc->syncs.empty()) {
266 RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
267 syncrule->type = found_global_syncs ? RTLIL::STg : RTLIL::STa;
268 syncrule->signal = RTLIL::SigSpec();
269 addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
270 proc->syncs.push_back(syncrule);
271 }
272
273 // create initial assignments for the temporary signals
274 if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
275 subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
276 } else {
277 addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
278 }
279
280 // process the AST
281 for (auto child : always->children)
282 if (child->type == AST_BLOCK)
283 processAst(child);
284
285 if (initSyncSignals.size() > 0)
286 {
287 RTLIL::SyncRule *sync = new RTLIL::SyncRule;
288 sync->type = RTLIL::SyncType::STi;
289 proc->syncs.push_back(sync);
290
291 log_assert(init_lvalue.size() == init_rvalue.size());
292
293 int offset = 0;
294 for (auto &init_lvalue_c : init_lvalue.chunks()) {
295 RTLIL::SigSpec lhs = init_lvalue_c;
296 RTLIL::SigSpec rhs = init_rvalue.extract(offset, init_lvalue_c.width);
297 remove_unwanted_lvalue_bits(lhs, rhs);
298 sync->actions.push_back(RTLIL::SigSig(lhs, rhs));
299 offset += lhs.size();
300 }
301 }
302
303 outputSignals = RTLIL::SigSpec(subst_lvalue_from);
304 }
305
306 void remove_unwanted_lvalue_bits(RTLIL::SigSpec &lhs, RTLIL::SigSpec &rhs)
307 {
308 RTLIL::SigSpec new_lhs, new_rhs;
309
310 log_assert(GetSize(lhs) == GetSize(rhs));
311 for (int i = 0; i < GetSize(lhs); i++) {
312 if (lhs[i].wire == nullptr)
313 continue;
314 new_lhs.append(lhs[i]);
315 new_rhs.append(rhs[i]);
316 }
317
318 lhs = new_lhs;
319 rhs = new_rhs;
320 }
321
322 // create new temporary signals
323 RTLIL::SigSpec new_temp_signal(RTLIL::SigSpec sig)
324 {
325 std::vector<RTLIL::SigChunk> chunks = sig.chunks();
326
327 for (int i = 0; i < GetSize(chunks); i++)
328 {
329 RTLIL::SigChunk &chunk = chunks[i];
330 if (chunk.wire == NULL)
331 continue;
332
333 std::string wire_name;
334 do {
335 wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
336 chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
337 if (chunk.wire->name.str().find('$') != std::string::npos)
338 wire_name += stringf("$%d", autoidx++);
339 } while (current_module->wires_.count(wire_name) > 0);
340
341 RTLIL::Wire *wire = current_module->addWire(wire_name, chunk.width);
342 wire->attributes["\\src"] = stringf("%s:%d", always->filename.c_str(), always->linenum);
343
344 chunk.wire = wire;
345 chunk.offset = 0;
346 }
347
348 return chunks;
349 }
350
351 // recursively traverse the AST an collect all assigned signals
352 void collect_lvalues(RTLIL::SigSpec &reg, AstNode *ast, bool type_eq, bool type_le, bool run_sort_and_unify = true)
353 {
354 switch (ast->type)
355 {
356 case AST_CASE:
357 for (auto child : ast->children)
358 if (child != ast->children[0]) {
359 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
360 collect_lvalues(reg, child, type_eq, type_le, false);
361 }
362 break;
363
364 case AST_COND:
365 case AST_CONDX:
366 case AST_CONDZ:
367 case AST_ALWAYS:
368 case AST_INITIAL:
369 for (auto child : ast->children)
370 if (child->type == AST_BLOCK)
371 collect_lvalues(reg, child, type_eq, type_le, false);
372 break;
373
374 case AST_BLOCK:
375 for (auto child : ast->children) {
376 if (child->type == AST_ASSIGN_EQ && type_eq)
377 reg.append(child->children[0]->genRTLIL());
378 if (child->type == AST_ASSIGN_LE && type_le)
379 reg.append(child->children[0]->genRTLIL());
380 if (child->type == AST_CASE || child->type == AST_BLOCK)
381 collect_lvalues(reg, child, type_eq, type_le, false);
382 }
383 break;
384
385 default:
386 log_abort();
387 }
388
389 if (run_sort_and_unify) {
390 std::set<RTLIL::SigBit> sorted_reg;
391 for (auto bit : reg)
392 if (bit.wire)
393 sorted_reg.insert(bit);
394 reg = RTLIL::SigSpec(sorted_reg);
395 }
396 }
397
398 // remove all assignments to the given signal pattern in a case and all its children.
399 // e.g. when the last statement in the code "a = 23; if (b) a = 42; a = 0;" is processed this
400 // function is called to clean up the first two assignments as they are overwritten by
401 // the third assignment.
402 void removeSignalFromCaseTree(const RTLIL::SigSpec &pattern, RTLIL::CaseRule *cs)
403 {
404 for (auto it = cs->actions.begin(); it != cs->actions.end(); it++)
405 it->first.remove2(pattern, &it->second);
406
407 for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
408 for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
409 removeSignalFromCaseTree(pattern, *it2);
410 }
411
412 // add an assignment (aka "action") but split it up in chunks. this way huge assignments
413 // are avoided and the generated $mux cells have a more "natural" size.
414 void addChunkActions(std::vector<RTLIL::SigSig> &actions, RTLIL::SigSpec lvalue, RTLIL::SigSpec rvalue, bool inSyncRule = false)
415 {
416 if (inSyncRule && initSyncSignals.size() > 0) {
417 init_lvalue.append(lvalue.extract(initSyncSignals));
418 init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
419 lvalue.remove2(initSyncSignals, &rvalue);
420 }
421 log_assert(lvalue.size() == rvalue.size());
422
423 int offset = 0;
424 for (auto &lvalue_c : lvalue.chunks()) {
425 RTLIL::SigSpec lhs = lvalue_c;
426 RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
427 if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync"))
428 rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
429 remove_unwanted_lvalue_bits(lhs, rhs);
430 actions.push_back(RTLIL::SigSig(lhs, rhs));
431 offset += lhs.size();
432 }
433 }
434
435 // recursively process the AST and fill the RTLIL::Process
436 void processAst(AstNode *ast)
437 {
438 switch (ast->type)
439 {
440 case AST_BLOCK:
441 for (auto child : ast->children)
442 processAst(child);
443 break;
444
445 case AST_ASSIGN_EQ:
446 case AST_ASSIGN_LE:
447 {
448 RTLIL::SigSpec unmapped_lvalue = ast->children[0]->genRTLIL(), lvalue = unmapped_lvalue;
449 RTLIL::SigSpec rvalue = ast->children[1]->genWidthRTLIL(lvalue.size(), &subst_rvalue_map.stdmap());
450
451 pool<SigBit> lvalue_sigbits;
452 for (int i = 0; i < GetSize(lvalue); i++) {
453 if (lvalue_sigbits.count(lvalue[i]) > 0) {
454 unmapped_lvalue.remove(i);
455 lvalue.remove(i);
456 rvalue.remove(i--);
457 } else
458 lvalue_sigbits.insert(lvalue[i]);
459 }
460
461 lvalue.replace(subst_lvalue_map.stdmap());
462
463 if (ast->type == AST_ASSIGN_EQ) {
464 for (int i = 0; i < GetSize(unmapped_lvalue); i++)
465 subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
466 }
467
468 removeSignalFromCaseTree(lvalue, current_case);
469 remove_unwanted_lvalue_bits(lvalue, rvalue);
470 current_case->actions.push_back(RTLIL::SigSig(lvalue, rvalue));
471 }
472 break;
473
474 case AST_CASE:
475 {
476 RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
477 sw->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
478 sw->signal = ast->children[0]->genWidthRTLIL(-1, &subst_rvalue_map.stdmap());
479 current_case->switches.push_back(sw);
480
481 for (auto &attr : ast->attributes) {
482 if (attr.second->type != AST_CONSTANT)
483 log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
484 attr.first.c_str());
485 sw->attributes[attr.first] = attr.second->asAttrConst();
486 }
487
488 RTLIL::SigSpec this_case_eq_lvalue;
489 collect_lvalues(this_case_eq_lvalue, ast, true, false);
490
491 RTLIL::SigSpec this_case_eq_ltemp = new_temp_signal(this_case_eq_lvalue);
492
493 RTLIL::SigSpec this_case_eq_rvalue = this_case_eq_lvalue;
494 this_case_eq_rvalue.replace(subst_rvalue_map.stdmap());
495
496 RTLIL::CaseRule *default_case = NULL;
497 RTLIL::CaseRule *last_generated_case = NULL;
498 for (auto child : ast->children)
499 {
500 if (child == ast->children[0])
501 continue;
502 log_assert(child->type == AST_COND || child->type == AST_CONDX || child->type == AST_CONDZ);
503
504 subst_lvalue_map.save();
505 subst_rvalue_map.save();
506
507 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
508 subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
509
510 RTLIL::CaseRule *backup_case = current_case;
511 current_case = new RTLIL::CaseRule;
512 last_generated_case = current_case;
513 addChunkActions(current_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
514 for (auto node : child->children) {
515 if (node->type == AST_DEFAULT)
516 default_case = current_case;
517 else if (node->type == AST_BLOCK)
518 processAst(node);
519 else
520 current_case->compare.push_back(node->genWidthRTLIL(sw->signal.size(), &subst_rvalue_map.stdmap()));
521 }
522 if (default_case != current_case)
523 sw->cases.push_back(current_case);
524 else
525 log_assert(current_case->compare.size() == 0);
526 current_case = backup_case;
527
528 subst_lvalue_map.restore();
529 subst_rvalue_map.restore();
530 }
531
532 if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
533 last_generated_case->compare.clear();
534 } else {
535 if (default_case == NULL) {
536 default_case = new RTLIL::CaseRule;
537 addChunkActions(default_case->actions, this_case_eq_ltemp, this_case_eq_rvalue);
538 }
539 sw->cases.push_back(default_case);
540 }
541
542 for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
543 subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
544
545 this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
546 removeSignalFromCaseTree(this_case_eq_lvalue, current_case);
547 addChunkActions(current_case->actions, this_case_eq_lvalue, this_case_eq_ltemp);
548 }
549 break;
550
551 case AST_WIRE:
552 log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
553 break;
554
555 case AST_PARAMETER:
556 case AST_LOCALPARAM:
557 log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
558 break;
559
560 case AST_NONE:
561 case AST_TCALL:
562 case AST_FOR:
563 break;
564
565 default:
566 // ast->dumpAst(NULL, "ast> ");
567 // current_ast_mod->dumpAst(NULL, "mod> ");
568 log_abort();
569 }
570 }
571 };
572
573 // detect sign and width of an expression
574 void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *found_real)
575 {
576 std::string type_name;
577 bool sub_sign_hint = true;
578 int sub_width_hint = -1;
579 int this_width = 0;
580 AstNode *range = NULL;
581 AstNode *id_ast = NULL;
582
583 bool local_found_real = false;
584 if (found_real == NULL)
585 found_real = &local_found_real;
586
587 switch (type)
588 {
589 case AST_CONSTANT:
590 width_hint = max(width_hint, int(bits.size()));
591 if (!is_signed)
592 sign_hint = false;
593 break;
594
595 case AST_REALVALUE:
596 *found_real = true;
597 width_hint = max(width_hint, 32);
598 break;
599
600 case AST_IDENTIFIER:
601 id_ast = id2ast;
602 if (id_ast == NULL && current_scope.count(str))
603 id_ast = current_scope.at(str);
604 if (!id_ast)
605 log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
606 if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
607 if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
608 this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
609 } else
610 if (id_ast->children[0]->type != AST_CONSTANT)
611 while (id_ast->simplify(true, false, false, 1, -1, false, true)) { }
612 if (id_ast->children[0]->type == AST_CONSTANT)
613 this_width = id_ast->children[0]->bits.size();
614 else
615 log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
616 if (children.size() != 0)
617 range = children[0];
618 } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
619 if (!id_ast->range_valid) {
620 if (id_ast->type == AST_AUTOWIRE)
621 this_width = 1;
622 else {
623 // current_ast_mod->dumpAst(NULL, "mod> ");
624 // log("---\n");
625 // id_ast->dumpAst(NULL, "decl> ");
626 // dumpAst(NULL, "ref> ");
627 log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
628 }
629 } else {
630 this_width = id_ast->range_left - id_ast->range_right + 1;
631 if (children.size() != 0)
632 range = children[0];
633 }
634 } else if (id_ast->type == AST_GENVAR) {
635 this_width = 32;
636 } else if (id_ast->type == AST_MEMORY) {
637 if (!id_ast->children[0]->range_valid)
638 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
639 this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
640 } else
641 log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
642 if (range) {
643 if (range->children.size() == 1)
644 this_width = 1;
645 else if (!range->range_valid) {
646 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
647 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
648 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
649 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
650 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
651 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
652 str.c_str());
653 this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
654 delete left_at_zero_ast;
655 delete right_at_zero_ast;
656 } else
657 this_width = range->range_left - range->range_right + 1;
658 sign_hint = false;
659 }
660 width_hint = max(width_hint, this_width);
661 if (!id_ast->is_signed)
662 sign_hint = false;
663 break;
664
665 case AST_TO_BITS:
666 while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
667 if (children[0]->type != AST_CONSTANT)
668 log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
669 children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
670 width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
671 break;
672
673 case AST_TO_SIGNED:
674 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
675 break;
676
677 case AST_TO_UNSIGNED:
678 children.at(0)->detectSignWidthWorker(width_hint, sub_sign_hint);
679 sign_hint = false;
680 break;
681
682 case AST_CONCAT:
683 for (auto child : children) {
684 sub_width_hint = 0;
685 sub_sign_hint = true;
686 child->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
687 this_width += sub_width_hint;
688 }
689 width_hint = max(width_hint, this_width);
690 sign_hint = false;
691 break;
692
693 case AST_REPLICATE:
694 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
695 if (children[0]->type != AST_CONSTANT)
696 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
697 children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
698 width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
699 sign_hint = false;
700 break;
701
702 case AST_NEG:
703 case AST_BIT_NOT:
704 case AST_POS:
705 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
706 break;
707
708 case AST_BIT_AND:
709 case AST_BIT_OR:
710 case AST_BIT_XOR:
711 case AST_BIT_XNOR:
712 for (auto child : children)
713 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
714 break;
715
716 case AST_REDUCE_AND:
717 case AST_REDUCE_OR:
718 case AST_REDUCE_XOR:
719 case AST_REDUCE_XNOR:
720 case AST_REDUCE_BOOL:
721 width_hint = max(width_hint, 1);
722 sign_hint = false;
723 break;
724
725 case AST_SHIFT_LEFT:
726 case AST_SHIFT_RIGHT:
727 case AST_SHIFT_SLEFT:
728 case AST_SHIFT_SRIGHT:
729 case AST_POW:
730 children[0]->detectSignWidthWorker(width_hint, sign_hint, found_real);
731 break;
732
733 case AST_LT:
734 case AST_LE:
735 case AST_EQ:
736 case AST_NE:
737 case AST_EQX:
738 case AST_NEX:
739 case AST_GE:
740 case AST_GT:
741 width_hint = max(width_hint, 1);
742 sign_hint = false;
743 break;
744
745 case AST_ADD:
746 case AST_SUB:
747 case AST_MUL:
748 case AST_DIV:
749 case AST_MOD:
750 for (auto child : children)
751 child->detectSignWidthWorker(width_hint, sign_hint, found_real);
752 break;
753
754 case AST_LOGIC_AND:
755 case AST_LOGIC_OR:
756 case AST_LOGIC_NOT:
757 width_hint = max(width_hint, 1);
758 sign_hint = false;
759 break;
760
761 case AST_TERNARY:
762 children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
763 children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
764 break;
765
766 case AST_MEMRD:
767 if (!id2ast->is_signed)
768 sign_hint = false;
769 if (!id2ast->children[0]->range_valid)
770 log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
771 this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
772 width_hint = max(width_hint, this_width);
773 break;
774
775 case AST_FCALL:
776 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
777 if (GetSize(children) == 1) {
778 while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
779 if (children[0]->type != AST_CONSTANT)
780 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
781 RTLIL::unescape_id(str).c_str());
782 width_hint = max(width_hint, int(children[0]->asInt(true)));
783 }
784 break;
785 }
786 if (str == "\\$past") {
787 if (GetSize(children) > 0) {
788 sub_width_hint = 0;
789 sub_sign_hint = true;
790 children.at(0)->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
791 width_hint = max(width_hint, sub_width_hint);
792 sign_hint = false;
793 }
794 break;
795 }
796 /* fall through */
797
798 // everything should have been handled above -> print error if not.
799 default:
800 for (auto f : log_files)
801 current_ast->dumpAst(f, "verilog-ast> ");
802 log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n",
803 type2str(type).c_str());
804 }
805
806 if (*found_real)
807 sign_hint = true;
808 }
809
810 // detect sign and width of an expression
811 void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real)
812 {
813 width_hint = -1;
814 sign_hint = true;
815 if (found_real)
816 *found_real = false;
817 detectSignWidthWorker(width_hint, sign_hint, found_real);
818 }
819
820 // create RTLIL from an AST node
821 // all generated cells, wires and processes are added to the module pointed to by 'current_module'
822 // when the AST node is an expression (AST_ADD, AST_BIT_XOR, etc.), the result signal is returned.
823 //
824 // note that this function is influenced by a number of global variables that might be set when
825 // called from genWidthRTLIL(). also note that this function recursively calls itself to transform
826 // larger expressions into a netlist of cells.
827 RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
828 {
829 // in the following big switch() statement there are some uses of
830 // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
831 // cases this variable is used to hold the type of the cell that should
832 // be instantiated for this type of AST node.
833 std::string type_name;
834
835 current_filename = filename;
836 set_line_num(linenum);
837
838 switch (type)
839 {
840 // simply ignore this nodes.
841 // they are either leftovers from simplify() or are referenced by other nodes
842 // and are only accessed here thru this references
843 case AST_NONE:
844 case AST_TASK:
845 case AST_FUNCTION:
846 case AST_DPI_FUNCTION:
847 case AST_AUTOWIRE:
848 case AST_LOCALPARAM:
849 case AST_DEFPARAM:
850 case AST_GENVAR:
851 case AST_GENFOR:
852 case AST_GENBLOCK:
853 case AST_GENIF:
854 case AST_GENCASE:
855 case AST_PACKAGE:
856 case AST_MODPORT:
857 case AST_MODPORTMEMBER:
858 break;
859 case AST_INTERFACEPORT: {
860 // If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
861 // This is used by the hierarchy pass to know when it can replace interface connection with the individual
862 // signals.
863 RTLIL::Wire *wire = current_module->addWire(str, 1);
864 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
865 wire->start_offset = 0;
866 wire->port_id = port_id;
867 wire->port_input = true;
868 wire->port_output = true;
869 wire->set_bool_attribute("\\is_interface");
870 if (children.size() > 0) {
871 for(size_t i=0; i<children.size();i++) {
872 if(children[i]->type == AST_INTERFACEPORTTYPE) {
873 std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
874 wire->attributes["\\interface_type"] = res.first;
875 if (res.second != "")
876 wire->attributes["\\interface_modport"] = res.second;
877 break;
878 }
879 }
880 }
881 wire->upto = 0;
882 }
883 break;
884 case AST_INTERFACEPORTTYPE:
885 break;
886
887 // remember the parameter, needed for example in techmap
888 case AST_PARAMETER:
889 current_module->avail_parameters.insert(str);
890 break;
891
892 // create an RTLIL::Wire for an AST_WIRE node
893 case AST_WIRE: {
894 if (current_module->wires_.count(str) != 0)
895 log_file_error(filename, linenum, "Re-definition of signal `%s'!\n",
896 str.c_str());
897 if (!range_valid)
898 log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n",
899 str.c_str());
900
901 log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
902
903 RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1);
904 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
905 wire->start_offset = range_right;
906 wire->port_id = port_id;
907 wire->port_input = is_input;
908 wire->port_output = is_output;
909 wire->upto = range_swapped;
910
911 for (auto &attr : attributes) {
912 if (attr.second->type != AST_CONSTANT)
913 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
914 attr.first.c_str());
915 wire->attributes[attr.first] = attr.second->asAttrConst();
916 }
917 }
918 break;
919
920 // create an RTLIL::Memory for an AST_MEMORY node
921 case AST_MEMORY: {
922 if (current_module->memories.count(str) != 0)
923 log_file_error(filename, linenum, "Re-definition of memory `%s'!\n",
924 str.c_str());
925
926 log_assert(children.size() >= 2);
927 log_assert(children[0]->type == AST_RANGE);
928 log_assert(children[1]->type == AST_RANGE);
929
930 if (!children[0]->range_valid || !children[1]->range_valid)
931 log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n",
932 str.c_str());
933
934 RTLIL::Memory *memory = new RTLIL::Memory;
935 memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
936 memory->name = str;
937 memory->width = children[0]->range_left - children[0]->range_right + 1;
938 if (children[1]->range_right < children[1]->range_left) {
939 memory->start_offset = children[1]->range_right;
940 memory->size = children[1]->range_left - children[1]->range_right + 1;
941 } else {
942 memory->start_offset = children[1]->range_left;
943 memory->size = children[1]->range_right - children[1]->range_left + 1;
944 }
945 current_module->memories[memory->name] = memory;
946
947 for (auto &attr : attributes) {
948 if (attr.second->type != AST_CONSTANT)
949 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
950 attr.first.c_str());
951 memory->attributes[attr.first] = attr.second->asAttrConst();
952 }
953 }
954 break;
955
956 // simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
957 case AST_CONSTANT:
958 {
959 if (width_hint < 0)
960 detectSignWidth(width_hint, sign_hint);
961
962 is_signed = sign_hint;
963 return RTLIL::SigSpec(bitsAsConst());
964 }
965
966 case AST_REALVALUE:
967 {
968 RTLIL::SigSpec sig = realAsConst(width_hint);
969 log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
970 realvalue, log_signal(sig));
971 return sig;
972 }
973
974 // simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
975 // for identifiers with dynamic bit ranges (e.g. "foo[bar]" or "foo[bar+3:bar]") a
976 // shifter cell is created and the output signal of this cell is returned
977 case AST_IDENTIFIER:
978 {
979 RTLIL::Wire *wire = NULL;
980 RTLIL::SigChunk chunk;
981 bool is_interface = false;
982
983 int add_undef_bits_msb = 0;
984 int add_undef_bits_lsb = 0;
985
986 if (id2ast && id2ast->type == AST_AUTOWIRE && current_module->wires_.count(str) == 0) {
987 RTLIL::Wire *wire = current_module->addWire(str);
988 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
989 wire->name = str;
990 if (flag_autowire)
991 log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
992 else
993 log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
994 }
995 else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
996 if (id2ast->children[0]->type != AST_CONSTANT)
997 log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n",
998 str.c_str());
999 chunk = RTLIL::Const(id2ast->children[0]->bits);
1000 goto use_const_chunk;
1001 }
1002 else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
1003 RTLIL::Wire *current_wire = current_module->wire(str);
1004 if (current_wire->get_bool_attribute("\\is_interface"))
1005 is_interface = true;
1006 // Ignore
1007 }
1008 // If an identifier is found that is not already known, assume that it is an interface:
1009 else if (1) { // FIXME: Check if sv_mode first?
1010 is_interface = true;
1011 }
1012 else {
1013 log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
1014 str.c_str());
1015 }
1016
1017 if (id2ast->type == AST_MEMORY)
1018 log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
1019 str.c_str());
1020
1021 // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
1022 // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
1023 // with the individual signals:
1024 if (is_interface) {
1025 RTLIL::Wire *dummy_wire;
1026 std::string dummy_wire_name = "$dummywireforinterface" + str;
1027 if (current_module->wires_.count(dummy_wire_name))
1028 dummy_wire = current_module->wires_[dummy_wire_name];
1029 else {
1030 dummy_wire = current_module->addWire(dummy_wire_name);
1031 dummy_wire->set_bool_attribute("\\is_interface");
1032 }
1033 RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
1034 return tmp;
1035 }
1036
1037 wire = current_module->wires_[str];
1038 chunk.wire = wire;
1039 chunk.width = wire->width;
1040 chunk.offset = 0;
1041
1042 use_const_chunk:
1043 if (children.size() != 0) {
1044 if (children[0]->type != AST_RANGE)
1045 log_file_error(filename, linenum, "Single range expected.\n");
1046 int source_width = id2ast->range_left - id2ast->range_right + 1;
1047 int source_offset = id2ast->range_right;
1048 if (!children[0]->range_valid) {
1049 AstNode *left_at_zero_ast = children[0]->children[0]->clone();
1050 AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
1051 while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1052 while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
1053 if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
1054 log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
1055 str.c_str());
1056 int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
1057 AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
1058 children[0]->children[1]->clone() : children[0]->children[0]->clone());
1059 fake_ast->children[0]->delete_children();
1060 RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
1061 if (id2ast->range_right != 0) {
1062 shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast->children[1]->is_signed);
1063 fake_ast->children[1]->is_signed = true;
1064 }
1065 if (id2ast->range_swapped) {
1066 shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
1067 fake_ast->children[1]->is_signed = true;
1068 }
1069 if (GetSize(shift_val) >= 32)
1070 fake_ast->children[1]->is_signed = true;
1071 RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
1072 delete left_at_zero_ast;
1073 delete right_at_zero_ast;
1074 delete fake_ast;
1075 return sig;
1076 } else {
1077 chunk.width = children[0]->range_left - children[0]->range_right + 1;
1078 chunk.offset = children[0]->range_right - source_offset;
1079 if (id2ast->range_swapped)
1080 chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
1081 if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
1082 if (chunk.width == 1)
1083 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
1084 str.c_str());
1085 else
1086 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n",
1087 str.c_str(), chunk.width);
1088 chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
1089 } else {
1090 if (chunk.width + chunk.offset > source_width) {
1091 add_undef_bits_msb = (chunk.width + chunk.offset) - source_width;
1092 chunk.width -= add_undef_bits_msb;
1093 }
1094 if (chunk.offset < 0) {
1095 add_undef_bits_lsb = -chunk.offset;
1096 chunk.width -= add_undef_bits_lsb;
1097 chunk.offset += add_undef_bits_lsb;
1098 }
1099 if (add_undef_bits_lsb)
1100 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
1101 str.c_str(), add_undef_bits_lsb);
1102 if (add_undef_bits_msb)
1103 log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
1104 str.c_str(), add_undef_bits_msb);
1105 }
1106 }
1107 }
1108
1109 RTLIL::SigSpec sig = { RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_msb), chunk, RTLIL::SigSpec(RTLIL::State::Sx, add_undef_bits_lsb) };
1110
1111 if (genRTLIL_subst_ptr)
1112 sig.replace(*genRTLIL_subst_ptr);
1113
1114 is_signed = children.size() > 0 ? false : id2ast->is_signed && sign_hint;
1115 return sig;
1116 }
1117
1118 // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly
1119 case AST_TO_SIGNED:
1120 case AST_TO_UNSIGNED: {
1121 RTLIL::SigSpec sig = children[0]->genRTLIL();
1122 if (sig.size() < width_hint)
1123 sig.extend_u0(width_hint, sign_hint);
1124 is_signed = sign_hint;
1125 return sig;
1126 }
1127
1128 // concatenation of signals can be done directly using RTLIL::SigSpec
1129 case AST_CONCAT: {
1130 RTLIL::SigSpec sig;
1131 for (auto it = children.begin(); it != children.end(); it++)
1132 sig.append((*it)->genRTLIL());
1133 if (sig.size() < width_hint)
1134 sig.extend_u0(width_hint, false);
1135 return sig;
1136 }
1137
1138 // replication of signals can be done directly using RTLIL::SigSpec
1139 case AST_REPLICATE: {
1140 RTLIL::SigSpec left = children[0]->genRTLIL();
1141 RTLIL::SigSpec right = children[1]->genRTLIL();
1142 if (!left.is_fully_const())
1143 log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
1144 int count = left.as_int();
1145 RTLIL::SigSpec sig;
1146 for (int i = 0; i < count; i++)
1147 sig.append(right);
1148 if (sig.size() < width_hint)
1149 sig.extend_u0(width_hint, false);
1150 is_signed = false;
1151 return sig;
1152 }
1153
1154 // generate cells for unary operations: $not, $pos, $neg
1155 if (0) { case AST_BIT_NOT: type_name = "$not"; }
1156 if (0) { case AST_POS: type_name = "$pos"; }
1157 if (0) { case AST_NEG: type_name = "$neg"; }
1158 {
1159 RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
1160 is_signed = children[0]->is_signed;
1161 int width = arg.size();
1162 if (width_hint > 0) {
1163 width = width_hint;
1164 widthExtend(this, arg, width, is_signed);
1165 }
1166 return uniop2rtlil(this, type_name, width, arg);
1167 }
1168
1169 // generate cells for binary operations: $and, $or, $xor, $xnor
1170 if (0) { case AST_BIT_AND: type_name = "$and"; }
1171 if (0) { case AST_BIT_OR: type_name = "$or"; }
1172 if (0) { case AST_BIT_XOR: type_name = "$xor"; }
1173 if (0) { case AST_BIT_XNOR: type_name = "$xnor"; }
1174 {
1175 if (width_hint < 0)
1176 detectSignWidth(width_hint, sign_hint);
1177 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1178 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1179 int width = max(left.size(), right.size());
1180 if (width_hint > 0)
1181 width = width_hint;
1182 is_signed = children[0]->is_signed && children[1]->is_signed;
1183 return binop2rtlil(this, type_name, width, left, right);
1184 }
1185
1186 // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
1187 if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; }
1188 if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; }
1189 if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; }
1190 if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; }
1191 {
1192 RTLIL::SigSpec arg = children[0]->genRTLIL();
1193 RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
1194 return sig;
1195 }
1196
1197 // generate cells for unary operations: $reduce_bool
1198 // (this is actually just an $reduce_or, but for clarity a different cell type is used)
1199 if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
1200 {
1201 RTLIL::SigSpec arg = children[0]->genRTLIL();
1202 RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
1203 return sig;
1204 }
1205
1206 // generate cells for binary operations: $shl, $shr, $sshl, $sshr
1207 if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; }
1208 if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; }
1209 if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; }
1210 if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; }
1211 {
1212 if (width_hint < 0)
1213 detectSignWidth(width_hint, sign_hint);
1214 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1215 RTLIL::SigSpec right = children[1]->genRTLIL();
1216 int width = width_hint > 0 ? width_hint : left.size();
1217 is_signed = children[0]->is_signed;
1218 return binop2rtlil(this, type_name, width, left, right);
1219 }
1220
1221 // generate cells for binary operations: $pow
1222 case AST_POW:
1223 {
1224 int right_width;
1225 bool right_signed;
1226 children[1]->detectSignWidth(right_width, right_signed);
1227 if (width_hint < 0)
1228 detectSignWidth(width_hint, sign_hint);
1229 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1230 RTLIL::SigSpec right = children[1]->genRTLIL(right_width, right_signed);
1231 int width = width_hint > 0 ? width_hint : left.size();
1232 is_signed = children[0]->is_signed;
1233 if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
1234 return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right);
1235 return binop2rtlil(this, "$pow", width, left, right);
1236 }
1237
1238 // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
1239 if (0) { case AST_LT: type_name = "$lt"; }
1240 if (0) { case AST_LE: type_name = "$le"; }
1241 if (0) { case AST_EQ: type_name = "$eq"; }
1242 if (0) { case AST_NE: type_name = "$ne"; }
1243 if (0) { case AST_EQX: type_name = "$eqx"; }
1244 if (0) { case AST_NEX: type_name = "$nex"; }
1245 if (0) { case AST_GE: type_name = "$ge"; }
1246 if (0) { case AST_GT: type_name = "$gt"; }
1247 {
1248 int width = max(width_hint, 1);
1249 width_hint = -1, sign_hint = true;
1250 children[0]->detectSignWidthWorker(width_hint, sign_hint);
1251 children[1]->detectSignWidthWorker(width_hint, sign_hint);
1252 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1253 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1254 RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
1255 return sig;
1256 }
1257
1258 // generate cells for binary operations: $add, $sub, $mul, $div, $mod
1259 if (0) { case AST_ADD: type_name = "$add"; }
1260 if (0) { case AST_SUB: type_name = "$sub"; }
1261 if (0) { case AST_MUL: type_name = "$mul"; }
1262 if (0) { case AST_DIV: type_name = "$div"; }
1263 if (0) { case AST_MOD: type_name = "$mod"; }
1264 {
1265 if (width_hint < 0)
1266 detectSignWidth(width_hint, sign_hint);
1267 RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
1268 RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
1269 #if 0
1270 int width = max(left.size(), right.size());
1271 if (width > width_hint && width_hint > 0)
1272 width = width_hint;
1273 if (width < width_hint) {
1274 if (type == AST_ADD || type == AST_SUB || type == AST_DIV)
1275 width++;
1276 if (type == AST_SUB && (!children[0]->is_signed || !children[1]->is_signed))
1277 width = width_hint;
1278 if (type == AST_MUL)
1279 width = min(left.size() + right.size(), width_hint);
1280 }
1281 #else
1282 int width = max(max(left.size(), right.size()), width_hint);
1283 #endif
1284 is_signed = children[0]->is_signed && children[1]->is_signed;
1285 return binop2rtlil(this, type_name, width, left, right);
1286 }
1287
1288 // generate cells for binary operations: $logic_and, $logic_or
1289 if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; }
1290 if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; }
1291 {
1292 RTLIL::SigSpec left = children[0]->genRTLIL();
1293 RTLIL::SigSpec right = children[1]->genRTLIL();
1294 return binop2rtlil(this, type_name, max(width_hint, 1), left, right);
1295 }
1296
1297 // generate cells for unary operations: $logic_not
1298 case AST_LOGIC_NOT:
1299 {
1300 RTLIL::SigSpec arg = children[0]->genRTLIL();
1301 return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg);
1302 }
1303
1304 // generate multiplexer for ternary operator (aka ?:-operator)
1305 case AST_TERNARY:
1306 {
1307 if (width_hint < 0)
1308 detectSignWidth(width_hint, sign_hint);
1309
1310 RTLIL::SigSpec cond = children[0]->genRTLIL();
1311 RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
1312 RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
1313
1314 if (cond.size() > 1)
1315 cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
1316
1317 int width = max(val1.size(), val2.size());
1318 is_signed = children[1]->is_signed && children[2]->is_signed;
1319 widthExtend(this, val1, width, is_signed);
1320 widthExtend(this, val2, width, is_signed);
1321
1322 RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
1323
1324 if (sig.size() < width_hint)
1325 sig.extend_u0(width_hint, sign_hint);
1326 return sig;
1327 }
1328
1329 // generate $memrd cells for memory read ports
1330 case AST_MEMRD:
1331 {
1332 std::stringstream sstr;
1333 sstr << "$memrd$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1334
1335 RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
1336 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1337
1338 RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
1339 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1340
1341 int mem_width, mem_size, addr_bits;
1342 is_signed = id2ast->is_signed;
1343 id2ast->meminfo(mem_width, mem_size, addr_bits);
1344
1345 RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
1346
1347 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1348 cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1349 cell->setPort("\\ADDR", addr_sig);
1350 cell->setPort("\\DATA", RTLIL::SigSpec(wire));
1351
1352 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1353 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1354 cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width);
1355
1356 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1357 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1358 cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
1359
1360 if (!sign_hint)
1361 is_signed = false;
1362
1363 return RTLIL::SigSpec(wire);
1364 }
1365
1366 // generate $memwr cells for memory write ports
1367 case AST_MEMWR:
1368 case AST_MEMINIT:
1369 {
1370 std::stringstream sstr;
1371 sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
1372
1373 RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit");
1374 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1375
1376 int mem_width, mem_size, addr_bits;
1377 id2ast->meminfo(mem_width, mem_size, addr_bits);
1378
1379 int num_words = 1;
1380 if (type == AST_MEMINIT) {
1381 if (children[2]->type != AST_CONSTANT)
1382 log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
1383 num_words = int(children[2]->asInt(false));
1384 cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
1385 }
1386
1387 SigSpec addr_sig = children[0]->genRTLIL();
1388
1389 cell->setPort("\\ADDR", addr_sig);
1390 cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
1391
1392 cell->parameters["\\MEMID"] = RTLIL::Const(str);
1393 cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig));
1394 cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);
1395
1396 if (type == AST_MEMWR) {
1397 cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1));
1398 cell->setPort("\\EN", children[2]->genRTLIL());
1399 cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0);
1400 cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
1401 }
1402
1403 cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1);
1404 }
1405 break;
1406
1407 // generate $assert cells
1408 case AST_ASSERT:
1409 case AST_ASSUME:
1410 case AST_LIVE:
1411 case AST_FAIR:
1412 case AST_COVER:
1413 {
1414 const char *celltype = nullptr;
1415 if (type == AST_ASSERT) celltype = "$assert";
1416 if (type == AST_ASSUME) celltype = "$assume";
1417 if (type == AST_LIVE) celltype = "$live";
1418 if (type == AST_FAIR) celltype = "$fair";
1419 if (type == AST_COVER) celltype = "$cover";
1420
1421 log_assert(children.size() == 2);
1422
1423 RTLIL::SigSpec check = children[0]->genRTLIL();
1424 if (GetSize(check) != 1)
1425 check = current_module->ReduceBool(NEW_ID, check);
1426
1427 RTLIL::SigSpec en = children[1]->genRTLIL();
1428 if (GetSize(en) != 1)
1429 en = current_module->ReduceBool(NEW_ID, en);
1430
1431 std::stringstream sstr;
1432 sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
1433
1434 RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
1435 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1436
1437 for (auto &attr : attributes) {
1438 if (attr.second->type != AST_CONSTANT)
1439 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
1440 attr.first.c_str());
1441 cell->attributes[attr.first] = attr.second->asAttrConst();
1442 }
1443
1444 cell->setPort("\\A", check);
1445 cell->setPort("\\EN", en);
1446 }
1447 break;
1448
1449 // add entries to current_module->connections for assignments (outside of always blocks)
1450 case AST_ASSIGN:
1451 {
1452 RTLIL::SigSpec left = children[0]->genRTLIL();
1453 RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size());
1454 if (left.has_const()) {
1455 RTLIL::SigSpec new_left, new_right;
1456 for (int i = 0; i < GetSize(left); i++)
1457 if (left[i].wire) {
1458 new_left.append(left[i]);
1459 new_right.append(right[i]);
1460 }
1461 log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
1462 " old assignment: %s = %s\n new assignment: %s = %s.\n",
1463 log_signal(left), log_signal(right),
1464 log_signal(new_left), log_signal(new_right));
1465 left = new_left;
1466 right = new_right;
1467 }
1468 current_module->connect(RTLIL::SigSig(left, right));
1469 }
1470 break;
1471
1472 // create an RTLIL::Cell for an AST_CELL
1473 case AST_CELL:
1474 {
1475 int port_counter = 0, para_counter = 0;
1476
1477 if (current_module->count_id(str) != 0)
1478 log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
1479
1480 RTLIL::Cell *cell = current_module->addCell(str, "");
1481 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1482 // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
1483 cell->set_bool_attribute("\\module_not_derived");
1484
1485 for (auto it = children.begin(); it != children.end(); it++) {
1486 AstNode *child = *it;
1487 if (child->type == AST_CELLTYPE) {
1488 cell->type = child->str;
1489 if (flag_icells && cell->type.substr(0, 2) == "\\$")
1490 cell->type = cell->type.substr(1);
1491 continue;
1492 }
1493 if (child->type == AST_PARASET) {
1494 IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
1495 if (child->children[0]->type == AST_REALVALUE) {
1496 log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
1497 log_id(cell), log_id(paraname), child->children[0]->realvalue);
1498 auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
1499 strnode->cloneInto(child->children[0]);
1500 delete strnode;
1501 }
1502 if (child->children[0]->type != AST_CONSTANT)
1503 log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
1504 log_id(cell), log_id(paraname));
1505 cell->parameters[paraname] = child->children[0]->asParaConst();
1506 continue;
1507 }
1508 if (child->type == AST_ARGUMENT) {
1509 RTLIL::SigSpec sig;
1510 if (child->children.size() > 0)
1511 sig = child->children[0]->genRTLIL();
1512 if (child->str.size() == 0) {
1513 char buf[100];
1514 snprintf(buf, 100, "$%d", ++port_counter);
1515 cell->setPort(buf, sig);
1516 } else {
1517 cell->setPort(child->str, sig);
1518 }
1519 continue;
1520 }
1521 log_abort();
1522 }
1523 for (auto &attr : attributes) {
1524 if (attr.second->type != AST_CONSTANT)
1525 log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
1526 attr.first.c_str());
1527 cell->attributes[attr.first] = attr.second->asAttrConst();
1528 }
1529 }
1530 break;
1531
1532 // use ProcessGenerator for always blocks
1533 case AST_ALWAYS: {
1534 AstNode *always = this->clone();
1535 ProcessGenerator generator(always);
1536 ignoreThisSignalsInInitial.append(generator.outputSignals);
1537 delete always;
1538 } break;
1539
1540 case AST_INITIAL: {
1541 AstNode *always = this->clone();
1542 ProcessGenerator generator(always, ignoreThisSignalsInInitial);
1543 delete always;
1544 } break;
1545
1546 case AST_FCALL: {
1547 if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq")
1548 {
1549 string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
1550 int width = width_hint;
1551
1552 if (GetSize(children) > 1)
1553 log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
1554 RTLIL::unescape_id(str).c_str(), GetSize(children));
1555
1556 if (GetSize(children) == 1) {
1557 if (children[0]->type != AST_CONSTANT)
1558 log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
1559 RTLIL::unescape_id(str).c_str());
1560 width = children[0]->asInt(true);
1561 }
1562
1563 if (width <= 0)
1564 log_file_error(filename, linenum, "Failed to detect width of %s!\n",
1565 RTLIL::unescape_id(str).c_str());
1566
1567 Cell *cell = current_module->addCell(myid, str.substr(1));
1568 cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1569 cell->parameters["\\WIDTH"] = width;
1570
1571 if (attributes.count("\\reg")) {
1572 auto &attr = attributes.at("\\reg");
1573 if (attr->type != AST_CONSTANT)
1574 log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
1575 cell->attributes["\\reg"] = attr->asAttrConst();
1576 }
1577
1578 Wire *wire = current_module->addWire(myid + "_wire", width);
1579 wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
1580 cell->setPort("\\Y", wire);
1581
1582 is_signed = sign_hint;
1583 return SigSpec(wire);
1584 }
1585 } /* fall through */
1586
1587 // everything should have been handled above -> print error if not.
1588 default:
1589 for (auto f : log_files)
1590 current_ast->dumpAst(f, "verilog-ast> ");
1591 type_name = type2str(type);
1592 log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n",
1593 type_name.c_str());
1594 }
1595
1596 return RTLIL::SigSpec();
1597 }
1598
1599 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
1600 // signals must be substituted before being used as input values (used by ProcessGenerator)
1601 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
1602 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
1603 {
1604 const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
1605
1606 if (new_subst_ptr)
1607 genRTLIL_subst_ptr = new_subst_ptr;
1608
1609 bool sign_hint = true;
1610 int width_hint = width;
1611 detectSignWidthWorker(width_hint, sign_hint);
1612 RTLIL::SigSpec sig = genRTLIL(width_hint, sign_hint);
1613
1614 genRTLIL_subst_ptr = backup_subst_ptr;
1615
1616 if (width >= 0)
1617 sig.extend_u0(width, is_signed);
1618
1619 return sig;
1620 }
1621
1622 YOSYS_NAMESPACE_END