2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 * A very simple and straightforward frontend for the RTLIL text
21 * representation (as generated by the 'ilang' backend).
27 #include "frontends/ilang/ilang_frontend.h"
29 namespace ILANG_FRONTEND {
31 RTLIL::Design *current_design;
32 RTLIL::Module *current_module;
33 RTLIL::Wire *current_wire;
34 RTLIL::Memory *current_memory;
35 RTLIL::Cell *current_cell;
36 RTLIL::Process *current_process;
37 std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
38 std::vector<RTLIL::CaseRule*> case_stack;
39 dict<RTLIL::IdString, RTLIL::Const> attrbuf;
40 bool flag_nooverwrite, flag_overwrite, flag_lib;
41 bool delete_current_module;
43 using namespace ILANG_FRONTEND;
48 %name-prefix "rtlil_frontend_ilang_yy"
53 YOSYS_NAMESPACE_PREFIX RTLIL::Const *data;
54 YOSYS_NAMESPACE_PREFIX RTLIL::SigSpec *sigspec;
55 std::vector<YOSYS_NAMESPACE_PREFIX RTLIL::SigSpec> *rsigspec;
58 %token <string> TOK_ID TOK_VALUE TOK_STRING
59 %token <integer> TOK_INT
60 %token TOK_AUTOIDX TOK_MODULE TOK_WIRE TOK_WIDTH TOK_INPUT TOK_OUTPUT TOK_INOUT
61 %token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC
62 %token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_GLOBAL TOK_INIT
63 %token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET
64 %token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE TOK_SIGNED TOK_UPTO
66 %type <rsigspec> sigspec_list_reversed
67 %type <sigspec> sigspec sigspec_list
68 %type <integer> sync_type
80 if (attrbuf.size() != 0)
81 rtlil_frontend_ilang_yyerror("dangling attribute");
88 optional_eol TOK_EOL | /* empty */;
97 TOK_MODULE TOK_ID EOL {
98 delete_current_module = false;
99 if (current_design->has($2)) {
100 RTLIL::Module *existing_mod = current_design->module($2);
101 if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) {
102 log("Ignoring blackbox re-definition of module %s.\n", $2);
103 delete_current_module = true;
104 } else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
105 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
106 } else if (flag_nooverwrite) {
107 log("Ignoring re-definition of module %s.\n", $2);
108 delete_current_module = true;
110 log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2);
111 current_design->remove(existing_mod);
114 current_module = new RTLIL::Module;
115 current_module->name = $2;
116 current_module->attributes = attrbuf;
117 if (!delete_current_module)
118 current_design->add(current_module);
121 } module_body TOK_END {
122 if (attrbuf.size() != 0)
123 rtlil_frontend_ilang_yyerror("dangling attribute");
124 current_module->fixup_ports();
125 if (delete_current_module)
126 delete current_module;
128 current_module->makeblackbox();
129 current_module = nullptr;
133 module_body module_stmt |
137 param_stmt | attr_stmt | wire_stmt | memory_stmt | cell_stmt | proc_stmt | conn_stmt;
140 TOK_PARAMETER TOK_ID EOL {
141 current_module->avail_parameters.insert($2);
146 TOK_ATTRIBUTE TOK_ID constant EOL {
153 TOK_AUTOIDX TOK_INT EOL {
154 autoidx = max(autoidx, $2);
159 current_wire = current_module->addWire("$__ilang_frontend_tmp__");
160 current_wire->attributes = attrbuf;
162 } wire_options TOK_ID EOL {
163 if (current_module->wires_.count($4) != 0)
164 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of wire %s.", $4).c_str());
165 current_module->rename(current_wire, $4);
170 wire_options TOK_WIDTH TOK_INT {
171 current_wire->width = $3;
173 wire_options TOK_UPTO {
174 current_wire->upto = true;
176 wire_options TOK_OFFSET TOK_INT {
177 current_wire->start_offset = $3;
179 wire_options TOK_INPUT TOK_INT {
180 current_wire->port_id = $3;
181 current_wire->port_input = true;
182 current_wire->port_output = false;
184 wire_options TOK_OUTPUT TOK_INT {
185 current_wire->port_id = $3;
186 current_wire->port_input = false;
187 current_wire->port_output = true;
189 wire_options TOK_INOUT TOK_INT {
190 current_wire->port_id = $3;
191 current_wire->port_input = true;
192 current_wire->port_output = true;
198 current_memory = new RTLIL::Memory;
199 current_memory->attributes = attrbuf;
201 } memory_options TOK_ID EOL {
202 if (current_module->memories.count($4) != 0)
203 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of memory %s.", $4).c_str());
204 current_memory->name = $4;
205 current_module->memories[$4] = current_memory;
210 memory_options TOK_WIDTH TOK_INT {
211 current_memory->width = $3;
213 memory_options TOK_SIZE TOK_INT {
214 current_memory->size = $3;
216 memory_options TOK_OFFSET TOK_INT {
217 current_memory->start_offset = $3;
222 TOK_CELL TOK_ID TOK_ID EOL {
223 if (current_module->cells_.count($3) != 0)
224 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell %s.", $3).c_str());
225 current_cell = current_module->addCell($3, $2);
226 current_cell->attributes = attrbuf;
230 } cell_body TOK_END EOL;
233 cell_body TOK_PARAMETER TOK_ID constant EOL {
234 current_cell->parameters[$3] = *$4;
238 cell_body TOK_PARAMETER TOK_SIGNED TOK_ID constant EOL {
239 current_cell->parameters[$4] = *$5;
240 current_cell->parameters[$4].flags |= RTLIL::CONST_FLAG_SIGNED;
244 cell_body TOK_CONNECT TOK_ID sigspec EOL {
245 if (current_cell->hasPort($3))
246 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of cell port %s.", $3).c_str());
247 current_cell->setPort($3, *$4);
254 TOK_PROCESS TOK_ID EOL {
255 if (current_module->processes.count($2) != 0)
256 rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of process %s.", $2).c_str());
257 current_process = new RTLIL::Process;
258 current_process->name = $2;
259 current_process->attributes = attrbuf;
260 current_module->processes[$2] = current_process;
261 switch_stack.clear();
262 switch_stack.push_back(¤t_process->root_case.switches);
264 case_stack.push_back(¤t_process->root_case);
267 } case_body sync_list TOK_END EOL;
270 attr_list TOK_SWITCH sigspec EOL {
271 RTLIL::SwitchRule *rule = new RTLIL::SwitchRule;
273 rule->attributes = attrbuf;
274 switch_stack.back()->push_back(rule);
277 } switch_body TOK_END EOL;
284 switch_body TOK_CASE {
285 RTLIL::CaseRule *rule = new RTLIL::CaseRule;
286 switch_stack.back()->back()->cases.push_back(rule);
287 switch_stack.push_back(&rule->switches);
288 case_stack.push_back(rule);
289 } compare_list EOL case_body {
290 switch_stack.pop_back();
291 case_stack.pop_back();
297 case_stack.back()->compare.push_back(*$1);
300 compare_list ',' sigspec {
301 case_stack.back()->compare.push_back(*$3);
307 case_body switch_stmt |
308 case_body assign_stmt |
312 TOK_ASSIGN sigspec sigspec EOL {
313 case_stack.back()->actions.push_back(RTLIL::SigSig(*$2, *$3));
319 sync_list TOK_SYNC sync_type sigspec EOL {
320 RTLIL::SyncRule *rule = new RTLIL::SyncRule;
321 rule->type = RTLIL::SyncType($3);
323 current_process->syncs.push_back(rule);
326 sync_list TOK_SYNC TOK_ALWAYS EOL {
327 RTLIL::SyncRule *rule = new RTLIL::SyncRule;
328 rule->type = RTLIL::SyncType::STa;
329 rule->signal = RTLIL::SigSpec();
330 current_process->syncs.push_back(rule);
332 sync_list TOK_SYNC TOK_GLOBAL EOL {
333 RTLIL::SyncRule *rule = new RTLIL::SyncRule;
334 rule->type = RTLIL::SyncType::STg;
335 rule->signal = RTLIL::SigSpec();
336 current_process->syncs.push_back(rule);
338 sync_list TOK_SYNC TOK_INIT EOL {
339 RTLIL::SyncRule *rule = new RTLIL::SyncRule;
340 rule->type = RTLIL::SyncType::STi;
341 rule->signal = RTLIL::SigSpec();
342 current_process->syncs.push_back(rule);
347 TOK_LOW { $$ = RTLIL::ST0; } |
348 TOK_HIGH { $$ = RTLIL::ST1; } |
349 TOK_POSEDGE { $$ = RTLIL::STp; } |
350 TOK_NEGEDGE { $$ = RTLIL::STn; } |
351 TOK_EDGE { $$ = RTLIL::STe; };
354 update_list TOK_UPDATE sigspec sigspec EOL {
355 current_process->syncs.back()->actions.push_back(RTLIL::SigSig(*$3, *$4));
364 int width = strtol($1, &ep, 10);
365 std::list<RTLIL::State> bits;
366 while (*(++ep) != 0) {
367 RTLIL::State bit = RTLIL::Sx;
369 case '0': bit = RTLIL::S0; break;
370 case '1': bit = RTLIL::S1; break;
371 case 'x': bit = RTLIL::Sx; break;
372 case 'z': bit = RTLIL::Sz; break;
373 case '-': bit = RTLIL::Sa; break;
374 case 'm': bit = RTLIL::Sm; break;
376 bits.push_front(bit);
378 if (bits.size() == 0)
379 bits.push_back(RTLIL::Sx);
380 while ((int)bits.size() < width) {
381 RTLIL::State bit = bits.back();
382 if (bit == RTLIL::S1)
386 while ((int)bits.size() > width)
388 $$ = new RTLIL::Const;
389 for (auto it = bits.begin(); it != bits.end(); it++)
390 $$->bits.push_back(*it);
394 $$ = new RTLIL::Const($1, 32);
397 $$ = new RTLIL::Const($1);
403 $$ = new RTLIL::SigSpec(*$1);
407 if (current_module->wires_.count($1) == 0)
408 rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
409 $$ = new RTLIL::SigSpec(current_module->wires_[$1]);
412 sigspec '[' TOK_INT ']' {
413 $$ = new RTLIL::SigSpec($1->extract($3));
416 sigspec '[' TOK_INT ':' TOK_INT ']' {
417 $$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1));
420 '{' sigspec_list '}' {
424 sigspec_list_reversed:
425 sigspec_list_reversed sigspec {
430 $$ = new std::vector<RTLIL::SigSpec>;
433 sigspec_list: sigspec_list_reversed {
434 $$ = new RTLIL::SigSpec;
435 for (auto it = $1->rbegin(); it != $1->rend(); it++)
441 TOK_CONNECT sigspec sigspec EOL {
442 if (attrbuf.size() != 0)
443 rtlil_frontend_ilang_yyerror("dangling attribute");
444 current_module->connect(*$2, *$3);