Merge pull request #3297 from jix/sva_nested_clk_else
[yosys.git] / frontends / verific / Makefile.inc
1
2 OBJS += frontends/verific/verific.o
3
4 ifeq ($(ENABLE_VERIFIC),1)
5
6 OBJS += frontends/verific/verificsva.o
7
8 EXTRA_TARGETS += share/verific
9
10 share/verific:
11 $(P) rm -rf share/verific.new
12 $(Q) mkdir -p share/verific.new
13 ifneq ($(DISABLE_VERIFIC_VHDL),1)
14 $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
15 $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
16 $(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
17 endif
18 $(Q) chmod -R a+rX share/verific.new
19 $(Q) mv share/verific.new share/verific
20
21 endif
22