frontends/verific/example.sv

   1 module top (
   2   input clk, rst,
   3   output reg [3:0] cnt
   4 );
   5   initial cnt = 0;
   6
   7   always @(posedge clk) begin
   8     if (rst)
   9       cnt <= 0;
  10     else
  11       cnt <= cnt + 4'd 1;
  12   end
  13
  14   always @(posedge clk) begin
  15     assume (cnt != 10);
  16     assert (cnt != 15);
  17   end
  18 endmodule