2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/log.h"
24 #include "libs/sha1/sha1.h"
34 #include "frontends/verific/verific.h"
38 #ifdef YOSYS_ENABLE_VERIFIC
41 #pragma clang diagnostic push
42 #pragma clang diagnostic ignored "-Woverloaded-virtual"
45 #include "veri_file.h"
46 #include "hier_tree.h"
47 #include "VeriModule.h"
48 #include "VeriWrite.h"
49 #include "VeriLibrary.h"
51 #ifdef VERIFIC_VHDL_SUPPORT
52 #include "vhdl_file.h"
53 #include "VhdlUnits.h"
56 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
57 #include "InitialAssertions.h"
60 #ifndef YOSYSHQ_VERIFIC_API_VERSION
61 # error "Only YosysHQ flavored Verific is supported. Please contact office@yosyshq.com for commercial support for Yosys+Verific."
64 #if YOSYSHQ_VERIFIC_API_VERSION < 20210801
65 # error "Please update your version of YosysHQ flavored Verific."
69 #pragma clang diagnostic pop
72 #ifdef VERIFIC_NAMESPACE
73 using namespace Verific
;
78 #ifdef YOSYS_ENABLE_VERIFIC
82 bool verific_import_pending
;
83 string verific_error_msg
;
84 int verific_sva_fsm_limit
;
86 vector
<string
> verific_incdirs
, verific_libdirs
;
88 void msg_func(msg_type_t msg_type
, const char *message_id
, linefile_type linefile
, const char *msg
, va_list args
)
90 string message_prefix
= stringf("VERIFIC-%s [%s] ",
91 msg_type
== VERIFIC_NONE
? "NONE" :
92 msg_type
== VERIFIC_ERROR
? "ERROR" :
93 msg_type
== VERIFIC_WARNING
? "WARNING" :
94 msg_type
== VERIFIC_IGNORE
? "IGNORE" :
95 msg_type
== VERIFIC_INFO
? "INFO" :
96 msg_type
== VERIFIC_COMMENT
? "COMMENT" :
97 msg_type
== VERIFIC_PROGRAM_ERROR
? "PROGRAM_ERROR" : "UNKNOWN", message_id
);
99 string message
= linefile
? stringf("%s:%d: ", LineFile::GetFileName(linefile
), LineFile::GetLineNo(linefile
)) : "";
100 message
+= vstringf(msg
, args
);
102 if (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_WARNING
|| msg_type
== VERIFIC_PROGRAM_ERROR
)
103 log_warning_noprefix("%s%s\n", message_prefix
.c_str(), message
.c_str());
105 log("%s%s\n", message_prefix
.c_str(), message
.c_str());
107 if (verific_error_msg
.empty() && (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_PROGRAM_ERROR
))
108 verific_error_msg
= message
;
111 string
get_full_netlist_name(Netlist
*nl
)
113 if (nl
->NumOfRefs() == 1) {
114 Instance
*inst
= (Instance
*)nl
->GetReferences()->GetLast();
115 return get_full_netlist_name(inst
->Owner()) + "." + inst
->Name();
118 return nl
->CellBaseName();
121 // ==================================================================
123 VerificImporter::VerificImporter(bool mode_gates
, bool mode_keep
, bool mode_nosva
, bool mode_names
, bool mode_verific
, bool mode_autocover
, bool mode_fullinit
) :
124 mode_gates(mode_gates
), mode_keep(mode_keep
), mode_nosva(mode_nosva
),
125 mode_names(mode_names
), mode_verific(mode_verific
), mode_autocover(mode_autocover
),
126 mode_fullinit(mode_fullinit
)
130 RTLIL::SigBit
VerificImporter::net_map_at(Net
*net
)
132 if (net
->IsExternalTo(netlist
))
133 log_error("Found external reference to '%s.%s' in netlist '%s', please use -flatten or -extnets.\n",
134 get_full_netlist_name(net
->Owner()).c_str(), net
->Name(), get_full_netlist_name(netlist
).c_str());
136 return net_map
.at(net
);
139 bool is_blackbox(Netlist
*nl
)
141 if (nl
->IsBlackBox() || nl
->IsEmptyBox())
144 const char *attr
= nl
->GetAttValue("blackbox");
145 if (attr
!= nullptr && strcmp(attr
, "0"))
151 RTLIL::IdString
VerificImporter::new_verific_id(Verific::DesignObj
*obj
)
153 std::string s
= stringf("$verific$%s", obj
->Name());
155 s
+= stringf("$%s:%d", Verific::LineFile::GetFileName(obj
->Linefile()), Verific::LineFile::GetLineNo(obj
->Linefile()));
156 s
+= stringf("$%d", autoidx
++);
160 void VerificImporter::import_attributes(dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, DesignObj
*obj
, Netlist
*nl
)
166 attributes
[ID::src
] = stringf("%s:%d", LineFile::GetFileName(obj
->Linefile()), LineFile::GetLineNo(obj
->Linefile()));
168 // FIXME: Parse numeric attributes
169 FOREACH_ATTRIBUTE(obj
, mi
, attr
) {
170 if (attr
->Key()[0] == ' ' || attr
->Value() == nullptr)
172 attributes
[RTLIL::escape_id(attr
->Key())] = RTLIL::Const(std::string(attr
->Value()));
176 auto type_range
= nl
->GetTypeRange(obj
->Name());
179 if (!type_range
->IsTypeEnum())
181 #ifdef VERIFIC_VHDL_SUPPORT
182 if (nl
->IsFromVhdl() && strcmp(type_range
->GetTypeName(), "STD_LOGIC") == 0)
185 auto type_name
= type_range
->GetTypeName();
188 attributes
.emplace(ID::wiretype
, RTLIL::escape_id(type_name
));
192 FOREACH_MAP_ITEM(type_range
->GetEnumIdMap(), mi
, &k
, &v
) {
193 if (nl
->IsFromVerilog()) {
194 // Expect <decimal>'b<binary>
195 auto p
= strchr(v
, '\'');
200 for (auto q
= p
+2; *q
!= '\0'; q
++)
201 if (*q
!= '0' && *q
!= '1') {
207 log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v
);
208 attributes
.emplace(stringf("\\enum_value_%s", p
+2), RTLIL::escape_id(k
));
210 #ifdef VERIFIC_VHDL_SUPPORT
211 else if (nl
->IsFromVhdl()) {
212 // Expect "<binary>" or plain <binary>
217 auto q
= (char*)malloc(l
+1);
220 for(char *ptr
= q
; *ptr
; ++ptr
)*ptr
= tolower(*ptr
);
221 attributes
.emplace(stringf("\\enum_value_%s", q
), RTLIL::escape_id(k
));
224 for (; *q
!= '"'; q
++)
225 if (*q
!= '0' && *q
!= '1') {
229 if (p
&& *(q
+1) != '\0')
235 auto q
= (char*)malloc(l
+1-2);
236 strncpy(q
, p
+1, l
-2);
238 attributes
.emplace(stringf("\\enum_value_%s", q
), RTLIL::escape_id(k
));
244 log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v
);
251 RTLIL::SigSpec
VerificImporter::operatorInput(Instance
*inst
)
254 for (int i
= int(inst
->InputSize())-1; i
>= 0; i
--)
255 if (inst
->GetInputBit(i
))
256 sig
.append(net_map_at(inst
->GetInputBit(i
)));
258 sig
.append(RTLIL::State::Sz
);
262 RTLIL::SigSpec
VerificImporter::operatorInput1(Instance
*inst
)
265 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--)
266 if (inst
->GetInput1Bit(i
))
267 sig
.append(net_map_at(inst
->GetInput1Bit(i
)));
269 sig
.append(RTLIL::State::Sz
);
273 RTLIL::SigSpec
VerificImporter::operatorInput2(Instance
*inst
)
276 for (int i
= int(inst
->Input2Size())-1; i
>= 0; i
--)
277 if (inst
->GetInput2Bit(i
))
278 sig
.append(net_map_at(inst
->GetInput2Bit(i
)));
280 sig
.append(RTLIL::State::Sz
);
284 RTLIL::SigSpec
VerificImporter::operatorInport(Instance
*inst
, const char *portname
)
286 PortBus
*portbus
= inst
->View()->GetPortBus(portname
);
289 for (unsigned i
= 0; i
< portbus
->Size(); i
++) {
290 Net
*net
= inst
->GetNet(portbus
->ElementAtIndex(i
));
293 sig
.append(RTLIL::State::S0
);
294 else if (net
->IsPwr())
295 sig
.append(RTLIL::State::S1
);
297 sig
.append(net_map_at(net
));
299 sig
.append(RTLIL::State::Sz
);
303 Port
*port
= inst
->View()->GetPort(portname
);
304 log_assert(port
!= NULL
);
305 Net
*net
= inst
->GetNet(port
);
306 return net_map_at(net
);
310 RTLIL::SigSpec
VerificImporter::operatorOutput(Instance
*inst
, const pool
<Net
*, hash_ptr_ops
> *any_all_nets
)
313 RTLIL::Wire
*dummy_wire
= NULL
;
314 for (int i
= int(inst
->OutputSize())-1; i
>= 0; i
--)
315 if (inst
->GetOutputBit(i
) && (!any_all_nets
|| !any_all_nets
->count(inst
->GetOutputBit(i
)))) {
316 sig
.append(net_map_at(inst
->GetOutputBit(i
)));
319 if (dummy_wire
== NULL
)
320 dummy_wire
= module
->addWire(new_verific_id(inst
));
323 sig
.append(RTLIL::SigSpec(dummy_wire
, dummy_wire
->width
- 1));
328 bool VerificImporter::import_netlist_instance_gates(Instance
*inst
, RTLIL::IdString inst_name
)
330 if (inst
->Type() == PRIM_AND
) {
331 module
->addAndGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
335 if (inst
->Type() == PRIM_NAND
) {
336 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
337 module
->addAndGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
338 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
342 if (inst
->Type() == PRIM_OR
) {
343 module
->addOrGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
347 if (inst
->Type() == PRIM_NOR
) {
348 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
349 module
->addOrGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
350 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
354 if (inst
->Type() == PRIM_XOR
) {
355 module
->addXorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
359 if (inst
->Type() == PRIM_XNOR
) {
360 module
->addXnorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
364 if (inst
->Type() == PRIM_BUF
) {
365 auto outnet
= inst
->GetOutput();
366 if (!any_all_nets
.count(outnet
))
367 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
371 if (inst
->Type() == PRIM_INV
) {
372 module
->addNotGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
376 if (inst
->Type() == PRIM_MUX
) {
377 module
->addMuxGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
381 if ((inst
->Type() == PRIM_TRI
) || (inst
->Type() == PRIM_BUFIF1
)) {
382 module
->addMuxGate(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
386 if (inst
->Type() == PRIM_FADD
)
388 RTLIL::SigSpec a
= net_map_at(inst
->GetInput1()), b
= net_map_at(inst
->GetInput2()), c
= net_map_at(inst
->GetCin());
389 RTLIL::SigSpec x
= inst
->GetCout() ? net_map_at(inst
->GetCout()) : module
->addWire(new_verific_id(inst
));
390 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
391 RTLIL::SigSpec tmp1
= module
->addWire(new_verific_id(inst
));
392 RTLIL::SigSpec tmp2
= module
->addWire(new_verific_id(inst
));
393 RTLIL::SigSpec tmp3
= module
->addWire(new_verific_id(inst
));
394 module
->addXorGate(new_verific_id(inst
), a
, b
, tmp1
);
395 module
->addXorGate(inst_name
, tmp1
, c
, y
);
396 module
->addAndGate(new_verific_id(inst
), tmp1
, c
, tmp2
);
397 module
->addAndGate(new_verific_id(inst
), a
, b
, tmp3
);
398 module
->addOrGate(new_verific_id(inst
), tmp2
, tmp3
, x
);
402 if (inst
->Type() == PRIM_DFFRS
)
404 VerificClocking
clocking(this, inst
->GetClock());
405 log_assert(clocking
.disable_sig
== State::S0
);
406 log_assert(clocking
.body_net
== nullptr);
408 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
409 clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
410 else if (inst
->GetSet()->IsGnd())
411 clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S0
);
412 else if (inst
->GetReset()->IsGnd())
413 clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S1
);
415 clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
416 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
420 if (inst
->Type() == PRIM_DLATCHRS
)
422 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
423 module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
425 module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
426 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
430 if (inst
->Type() == PRIM_DFF
)
432 VerificClocking
clocking(this, inst
->GetClock());
433 log_assert(clocking
.disable_sig
== State::S0
);
434 log_assert(clocking
.body_net
== nullptr);
436 if (inst
->GetAsyncCond()->IsGnd())
437 clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
439 clocking
.addAldff(inst_name
, net_map_at(inst
->GetAsyncCond()), net_map_at(inst
->GetAsyncVal()),
440 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
444 if (inst
->Type() == PRIM_DLATCH
)
446 if (inst
->GetAsyncCond()->IsGnd()) {
447 module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
449 RTLIL::SigSpec sig_set
= module
->And(NEW_ID
, net_map_at(inst
->GetAsyncCond()), net_map_at(inst
->GetAsyncVal()));
450 RTLIL::SigSpec sig_clr
= module
->And(NEW_ID
, net_map_at(inst
->GetAsyncCond()), module
->Not(NEW_ID
, net_map_at(inst
->GetAsyncVal())));
451 module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), sig_set
, sig_clr
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
459 bool VerificImporter::import_netlist_instance_cells(Instance
*inst
, RTLIL::IdString inst_name
)
461 RTLIL::Cell
*cell
= nullptr;
463 if (inst
->Type() == PRIM_AND
) {
464 cell
= module
->addAnd(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
465 import_attributes(cell
->attributes
, inst
);
469 if (inst
->Type() == PRIM_NAND
) {
470 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
471 cell
= module
->addAnd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
472 import_attributes(cell
->attributes
, inst
);
473 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
474 import_attributes(cell
->attributes
, inst
);
478 if (inst
->Type() == PRIM_OR
) {
479 cell
= module
->addOr(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
480 import_attributes(cell
->attributes
, inst
);
484 if (inst
->Type() == PRIM_NOR
) {
485 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
486 cell
= module
->addOr(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
487 import_attributes(cell
->attributes
, inst
);
488 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
489 import_attributes(cell
->attributes
, inst
);
493 if (inst
->Type() == PRIM_XOR
) {
494 cell
= module
->addXor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
495 import_attributes(cell
->attributes
, inst
);
499 if (inst
->Type() == PRIM_XNOR
) {
500 cell
= module
->addXnor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
501 import_attributes(cell
->attributes
, inst
);
505 if (inst
->Type() == PRIM_INV
) {
506 cell
= module
->addNot(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
507 import_attributes(cell
->attributes
, inst
);
511 if (inst
->Type() == PRIM_MUX
) {
512 cell
= module
->addMux(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
513 import_attributes(cell
->attributes
, inst
);
517 if ((inst
->Type() == PRIM_TRI
) || (inst
->Type() == PRIM_BUFIF1
)) {
518 cell
= module
->addMux(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
519 import_attributes(cell
->attributes
, inst
);
523 if (inst
->Type() == PRIM_FADD
)
525 RTLIL::SigSpec a_plus_b
= module
->addWire(new_verific_id(inst
), 2);
526 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
528 y
.append(net_map_at(inst
->GetCout()));
529 cell
= module
->addAdd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), a_plus_b
);
530 import_attributes(cell
->attributes
, inst
);
531 cell
= module
->addAdd(inst_name
, a_plus_b
, net_map_at(inst
->GetCin()), y
);
532 import_attributes(cell
->attributes
, inst
);
536 if (inst
->Type() == PRIM_DFFRS
)
538 VerificClocking
clocking(this, inst
->GetClock());
539 log_assert(clocking
.disable_sig
== State::S0
);
540 log_assert(clocking
.body_net
== nullptr);
542 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
543 cell
= clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
544 else if (inst
->GetSet()->IsGnd())
545 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
546 else if (inst
->GetReset()->IsGnd())
547 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
549 cell
= clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
550 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
551 import_attributes(cell
->attributes
, inst
);
555 if (inst
->Type() == PRIM_DLATCHRS
)
557 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
558 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
560 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
561 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
562 import_attributes(cell
->attributes
, inst
);
566 if (inst
->Type() == PRIM_DFF
)
568 VerificClocking
clocking(this, inst
->GetClock());
569 log_assert(clocking
.disable_sig
== State::S0
);
570 log_assert(clocking
.body_net
== nullptr);
572 if (inst
->GetAsyncCond()->IsGnd())
573 cell
= clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
575 cell
= clocking
.addAldff(inst_name
, net_map_at(inst
->GetAsyncCond()), net_map_at(inst
->GetAsyncVal()),
576 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
577 import_attributes(cell
->attributes
, inst
);
581 if (inst
->Type() == PRIM_DLATCH
)
583 if (inst
->GetAsyncCond()->IsGnd()) {
584 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
586 RTLIL::SigSpec sig_set
= module
->And(NEW_ID
, net_map_at(inst
->GetAsyncCond()), net_map_at(inst
->GetAsyncVal()));
587 RTLIL::SigSpec sig_clr
= module
->And(NEW_ID
, net_map_at(inst
->GetAsyncCond()), module
->Not(NEW_ID
, net_map_at(inst
->GetAsyncVal())));
588 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), sig_set
, sig_clr
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
590 import_attributes(cell
->attributes
, inst
);
594 #define IN operatorInput(inst)
595 #define IN1 operatorInput1(inst)
596 #define IN2 operatorInput2(inst)
597 #define OUT operatorOutput(inst)
598 #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
599 #define SIGNED inst->View()->IsSigned()
601 if (inst
->Type() == OPER_ADDER
) {
602 RTLIL::SigSpec out
= OUT
;
603 if (inst
->GetCout() != NULL
)
604 out
.append(net_map_at(inst
->GetCout()));
605 if (inst
->GetCin()->IsGnd()) {
606 cell
= module
->addAdd(inst_name
, IN1
, IN2
, out
, SIGNED
);
607 import_attributes(cell
->attributes
, inst
);
609 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
), GetSize(out
));
610 cell
= module
->addAdd(new_verific_id(inst
), IN1
, IN2
, tmp
, SIGNED
);
611 import_attributes(cell
->attributes
, inst
);
612 cell
= module
->addAdd(inst_name
, tmp
, net_map_at(inst
->GetCin()), out
, false);
613 import_attributes(cell
->attributes
, inst
);
618 if (inst
->Type() == OPER_MULTIPLIER
) {
619 cell
= module
->addMul(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
620 import_attributes(cell
->attributes
, inst
);
624 if (inst
->Type() == OPER_DIVIDER
) {
625 cell
= module
->addDiv(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
626 import_attributes(cell
->attributes
, inst
);
630 if (inst
->Type() == OPER_MODULO
) {
631 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
632 import_attributes(cell
->attributes
, inst
);
636 if (inst
->Type() == OPER_REMAINDER
) {
637 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
638 import_attributes(cell
->attributes
, inst
);
642 if (inst
->Type() == OPER_SHIFT_LEFT
) {
643 cell
= module
->addShl(inst_name
, IN1
, IN2
, OUT
, false);
644 import_attributes(cell
->attributes
, inst
);
648 if (inst
->Type() == OPER_ENABLED_DECODER
) {
650 vec
.append(net_map_at(inst
->GetControl()));
651 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
652 vec
.append(RTLIL::State::S0
);
654 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
655 import_attributes(cell
->attributes
, inst
);
659 if (inst
->Type() == OPER_DECODER
) {
661 vec
.append(RTLIL::State::S1
);
662 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
663 vec
.append(RTLIL::State::S0
);
665 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
666 import_attributes(cell
->attributes
, inst
);
670 if (inst
->Type() == OPER_SHIFT_RIGHT
) {
671 Net
*net_cin
= inst
->GetCin();
672 Net
*net_a_msb
= inst
->GetInput1Bit(0);
673 if (net_cin
->IsGnd())
674 cell
= module
->addShr(inst_name
, IN1
, IN2
, OUT
, false);
675 else if (net_cin
== net_a_msb
)
676 cell
= module
->addSshr(inst_name
, IN1
, IN2
, OUT
, true);
678 log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst
->Name());
679 import_attributes(cell
->attributes
, inst
);
683 if (inst
->Type() == OPER_REDUCE_AND
) {
684 cell
= module
->addReduceAnd(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
685 import_attributes(cell
->attributes
, inst
);
689 if (inst
->Type() == OPER_REDUCE_NAND
) {
690 Wire
*tmp
= module
->addWire(NEW_ID
);
691 cell
= module
->addReduceAnd(inst_name
, IN
, tmp
, SIGNED
);
692 module
->addNot(NEW_ID
, tmp
, net_map_at(inst
->GetOutput()));
693 import_attributes(cell
->attributes
, inst
);
697 if (inst
->Type() == OPER_REDUCE_OR
) {
698 cell
= module
->addReduceOr(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
699 import_attributes(cell
->attributes
, inst
);
703 if (inst
->Type() == OPER_REDUCE_XOR
) {
704 cell
= module
->addReduceXor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
705 import_attributes(cell
->attributes
, inst
);
709 if (inst
->Type() == OPER_REDUCE_XNOR
) {
710 cell
= module
->addReduceXnor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
711 import_attributes(cell
->attributes
, inst
);
715 if (inst
->Type() == OPER_REDUCE_NOR
) {
716 SigSpec t
= module
->ReduceOr(new_verific_id(inst
), IN
, SIGNED
);
717 cell
= module
->addNot(inst_name
, t
, net_map_at(inst
->GetOutput()));
718 import_attributes(cell
->attributes
, inst
);
722 if (inst
->Type() == OPER_LESSTHAN
) {
723 Net
*net_cin
= inst
->GetCin();
724 if (net_cin
->IsGnd())
725 cell
= module
->addLt(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
726 else if (net_cin
->IsPwr())
727 cell
= module
->addLe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
729 log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst
->Name());
730 import_attributes(cell
->attributes
, inst
);
734 if (inst
->Type() == OPER_WIDE_AND
) {
735 cell
= module
->addAnd(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
736 import_attributes(cell
->attributes
, inst
);
740 if (inst
->Type() == OPER_WIDE_OR
) {
741 cell
= module
->addOr(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
742 import_attributes(cell
->attributes
, inst
);
746 if (inst
->Type() == OPER_WIDE_XOR
) {
747 cell
= module
->addXor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
748 import_attributes(cell
->attributes
, inst
);
752 if (inst
->Type() == OPER_WIDE_XNOR
) {
753 cell
= module
->addXnor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
754 import_attributes(cell
->attributes
, inst
);
758 if (inst
->Type() == OPER_WIDE_BUF
) {
759 cell
= module
->addPos(inst_name
, IN
, FILTERED_OUT
, SIGNED
);
760 import_attributes(cell
->attributes
, inst
);
764 if (inst
->Type() == OPER_WIDE_INV
) {
765 cell
= module
->addNot(inst_name
, IN
, OUT
, SIGNED
);
766 import_attributes(cell
->attributes
, inst
);
770 if (inst
->Type() == OPER_MINUS
) {
771 cell
= module
->addSub(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
772 import_attributes(cell
->attributes
, inst
);
776 if (inst
->Type() == OPER_UMINUS
) {
777 cell
= module
->addNeg(inst_name
, IN
, OUT
, SIGNED
);
778 import_attributes(cell
->attributes
, inst
);
782 if (inst
->Type() == OPER_EQUAL
) {
783 cell
= module
->addEq(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
784 import_attributes(cell
->attributes
, inst
);
788 if (inst
->Type() == OPER_NEQUAL
) {
789 cell
= module
->addNe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
790 import_attributes(cell
->attributes
, inst
);
794 if (inst
->Type() == OPER_WIDE_MUX
) {
795 cell
= module
->addMux(inst_name
, IN1
, IN2
, net_map_at(inst
->GetControl()), OUT
);
796 import_attributes(cell
->attributes
, inst
);
800 if (inst
->Type() == OPER_NTO1MUX
) {
801 cell
= module
->addShr(inst_name
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
802 import_attributes(cell
->attributes
, inst
);
806 if (inst
->Type() == OPER_WIDE_NTO1MUX
)
808 SigSpec data
= IN2
, out
= OUT
;
810 int wordsize_bits
= ceil_log2(GetSize(out
));
811 int wordsize
= 1 << wordsize_bits
;
813 SigSpec sel
= {IN1
, SigSpec(State::S0
, wordsize_bits
)};
816 for (int i
= 0; i
< GetSize(data
); i
+= GetSize(out
)) {
817 SigSpec d
= data
.extract(i
, GetSize(out
));
818 d
.extend_u0(wordsize
);
819 padded_data
.append(d
);
822 cell
= module
->addShr(inst_name
, padded_data
, sel
, out
);
823 import_attributes(cell
->attributes
, inst
);
827 if (inst
->Type() == OPER_SELECTOR
)
829 cell
= module
->addPmux(inst_name
, State::S0
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
830 import_attributes(cell
->attributes
, inst
);
834 if (inst
->Type() == OPER_WIDE_SELECTOR
)
837 cell
= module
->addPmux(inst_name
, SigSpec(State::S0
, GetSize(out
)), IN2
, IN1
, out
);
838 import_attributes(cell
->attributes
, inst
);
842 if (inst
->Type() == OPER_WIDE_TRI
) {
843 cell
= module
->addMux(inst_name
, RTLIL::SigSpec(RTLIL::State::Sz
, inst
->OutputSize()), IN
, net_map_at(inst
->GetControl()), OUT
);
844 import_attributes(cell
->attributes
, inst
);
848 if (inst
->Type() == OPER_WIDE_DFFRS
)
850 VerificClocking
clocking(this, inst
->GetClock());
851 log_assert(clocking
.disable_sig
== State::S0
);
852 log_assert(clocking
.body_net
== nullptr);
854 RTLIL::SigSpec sig_set
= operatorInport(inst
, "set");
855 RTLIL::SigSpec sig_reset
= operatorInport(inst
, "reset");
857 if (sig_set
.is_fully_const() && !sig_set
.as_bool() && sig_reset
.is_fully_const() && !sig_reset
.as_bool())
858 cell
= clocking
.addDff(inst_name
, IN
, OUT
);
860 cell
= clocking
.addDffsr(inst_name
, sig_set
, sig_reset
, IN
, OUT
);
861 import_attributes(cell
->attributes
, inst
);
866 if (inst
->Type() == OPER_WIDE_DLATCHRS
)
868 RTLIL::SigSpec sig_set
= operatorInport(inst
, "set");
869 RTLIL::SigSpec sig_reset
= operatorInport(inst
, "reset");
871 if (sig_set
.is_fully_const() && !sig_set
.as_bool() && sig_reset
.is_fully_const() && !sig_reset
.as_bool())
872 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), IN
, OUT
);
874 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), sig_set
, sig_reset
, IN
, OUT
);
875 import_attributes(cell
->attributes
, inst
);
880 if (inst
->Type() == OPER_WIDE_DFF
)
882 VerificClocking
clocking(this, inst
->GetClock());
883 log_assert(clocking
.disable_sig
== State::S0
);
884 log_assert(clocking
.body_net
== nullptr);
886 RTLIL::SigSpec sig_d
= IN
;
887 RTLIL::SigSpec sig_q
= OUT
;
888 RTLIL::SigSpec sig_adata
= IN1
;
889 RTLIL::SigSpec sig_acond
= IN2
;
891 if (sig_acond
.is_fully_const() && !sig_acond
.as_bool()) {
892 cell
= clocking
.addDff(inst_name
, sig_d
, sig_q
);
893 import_attributes(cell
->attributes
, inst
);
895 int offset
= 0, width
= 0;
896 for (offset
= 0; offset
< GetSize(sig_acond
); offset
+= width
) {
897 for (width
= 1; offset
+width
< GetSize(sig_acond
); width
++)
898 if (sig_acond
[offset
] != sig_acond
[offset
+width
]) break;
899 cell
= clocking
.addAldff(inst_name
, sig_acond
[offset
], sig_adata
.extract(offset
, width
),
900 sig_d
.extract(offset
, width
), sig_q
.extract(offset
, width
));
901 import_attributes(cell
->attributes
, inst
);
908 if (inst
->Type() == OPER_WIDE_DLATCH
)
910 RTLIL::SigSpec sig_d
= IN
;
911 RTLIL::SigSpec sig_q
= OUT
;
912 RTLIL::SigSpec sig_adata
= IN1
;
913 RTLIL::SigSpec sig_acond
= IN2
;
915 if (sig_acond
.is_fully_const() && !sig_acond
.as_bool()) {
916 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), sig_d
, sig_q
);
917 import_attributes(cell
->attributes
, inst
);
919 int offset
= 0, width
= 0;
920 for (offset
= 0; offset
< GetSize(sig_acond
); offset
+= width
) {
921 for (width
= 1; offset
+width
< GetSize(sig_acond
); width
++)
922 if (sig_acond
[offset
] != sig_acond
[offset
+width
]) break;
923 RTLIL::SigSpec sig_set
= module
->Mux(NEW_ID
, RTLIL::SigSpec(0, width
), sig_adata
.extract(offset
, width
), sig_acond
[offset
]);
924 RTLIL::SigSpec sig_clr
= module
->Mux(NEW_ID
, RTLIL::SigSpec(0, width
), module
->Not(NEW_ID
, sig_adata
.extract(offset
, width
)), sig_acond
[offset
]);
925 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), sig_set
, sig_clr
,
926 sig_d
.extract(offset
, width
), sig_q
.extract(offset
, width
));
927 import_attributes(cell
->attributes
, inst
);
943 void VerificImporter::merge_past_ffs_clock(pool
<RTLIL::Cell
*> &candidates
, SigBit clock
, bool clock_pol
)
945 bool keep_running
= true;
950 keep_running
= false;
952 dict
<SigBit
, pool
<RTLIL::Cell
*>> dbits_db
;
955 for (auto cell
: candidates
) {
956 SigBit bit
= sigmap(cell
->getPort(ID::D
));
957 dbits_db
[bit
].insert(cell
);
961 dbits
.sort_and_unify();
963 for (auto chunk
: dbits
.chunks())
965 SigSpec sig_d
= chunk
;
967 if (chunk
.wire
== nullptr || GetSize(sig_d
) == 1)
970 SigSpec sig_q
= module
->addWire(NEW_ID
, GetSize(sig_d
));
971 RTLIL::Cell
*new_ff
= module
->addDff(NEW_ID
, clock
, sig_d
, sig_q
, clock_pol
);
974 log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d
), log_id(new_ff
));
976 for (int i
= 0; i
< GetSize(sig_d
); i
++)
977 for (auto old_ff
: dbits_db
[sig_d
[i
]])
980 log(" replacing old ff %s on bit %d.\n", log_id(old_ff
), i
);
982 SigBit old_q
= old_ff
->getPort(ID::Q
);
983 SigBit new_q
= sig_q
[i
];
985 sigmap
.add(old_q
, new_q
);
986 module
->connect(old_q
, new_q
);
987 candidates
.erase(old_ff
);
988 module
->remove(old_ff
);
995 void VerificImporter::merge_past_ffs(pool
<RTLIL::Cell
*> &candidates
)
997 dict
<pair
<SigBit
, int>, pool
<RTLIL::Cell
*>> database
;
999 for (auto cell
: candidates
)
1001 SigBit clock
= cell
->getPort(ID::CLK
);
1002 bool clock_pol
= cell
->getParam(ID::CLK_POLARITY
).as_bool();
1003 database
[make_pair(clock
, int(clock_pol
))].insert(cell
);
1006 for (auto it
: database
)
1007 merge_past_ffs_clock(it
.second
, it
.first
.first
, it
.first
.second
);
1010 static std::string
sha1_if_contain_spaces(std::string str
)
1012 if(str
.find_first_of(' ') != std::string::npos
) {
1013 std::size_t open
= str
.find_first_of('(');
1014 std::size_t closed
= str
.find_last_of(')');
1015 if (open
!= std::string::npos
&& closed
!= std::string::npos
) {
1016 std::string content
= str
.substr(open
+ 1, closed
- open
- 1);
1017 return str
.substr(0, open
+ 1) + sha1(content
) + str
.substr(closed
);
1025 void VerificImporter::import_netlist(RTLIL::Design
*design
, Netlist
*nl
, std::set
<Netlist
*> &nl_todo
, bool norename
)
1027 std::string netlist_name
= nl
->GetAtt(" \\top") ? nl
->CellBaseName() : nl
->Owner()->Name();
1028 std::string module_name
= netlist_name
;
1030 if (nl
->IsOperator() || nl
->IsPrimitive()) {
1031 module_name
= "$verific$" + module_name
;
1033 if (!norename
&& *nl
->Name()) {
1035 module_name
+= nl
->Name();
1038 module_name
= "\\" + sha1_if_contain_spaces(module_name
);
1043 if (design
->has(module_name
)) {
1044 if (!nl
->IsOperator() && !is_blackbox(nl
))
1045 log_cmd_error("Re-definition of module `%s'.\n", netlist_name
.c_str());
1049 module
= new RTLIL::Module
;
1050 module
->name
= module_name
;
1051 design
->add(module
);
1053 if (is_blackbox(nl
)) {
1054 log("Importing blackbox module %s.\n", RTLIL::id2cstr(module
->name
));
1055 module
->set_bool_attribute(ID::blackbox
);
1057 log("Importing module %s.\n", RTLIL::id2cstr(module
->name
));
1059 import_attributes(module
->attributes
, nl
, nl
);
1070 FOREACH_PORT_OF_NETLIST(nl
, mi
, port
)
1075 if (verific_verbose
)
1076 log(" importing port %s.\n", port
->Name());
1078 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(port
->Name()));
1079 import_attributes(wire
->attributes
, port
, nl
);
1081 wire
->port_id
= nl
->IndexOf(port
) + 1;
1083 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_IN
)
1084 wire
->port_input
= true;
1085 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_OUT
)
1086 wire
->port_output
= true;
1088 if (port
->GetNet()) {
1089 net
= port
->GetNet();
1090 if (net_map
.count(net
) == 0)
1091 net_map
[net
] = wire
;
1092 else if (wire
->port_input
)
1093 module
->connect(net_map_at(net
), wire
);
1095 module
->connect(wire
, net_map_at(net
));
1099 FOREACH_PORTBUS_OF_NETLIST(nl
, mi
, portbus
)
1101 if (verific_verbose
)
1102 log(" importing portbus %s.\n", portbus
->Name());
1104 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(portbus
->Name()), portbus
->Size());
1105 wire
->start_offset
= min(portbus
->LeftIndex(), portbus
->RightIndex());
1106 import_attributes(wire
->attributes
, portbus
, nl
);
1108 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_IN
)
1109 wire
->port_input
= true;
1110 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_OUT
)
1111 wire
->port_output
= true;
1113 for (int i
= portbus
->LeftIndex();; i
+= portbus
->IsUp() ? +1 : -1) {
1114 if (portbus
->ElementAtIndex(i
) && portbus
->ElementAtIndex(i
)->GetNet()) {
1115 net
= portbus
->ElementAtIndex(i
)->GetNet();
1116 RTLIL::SigBit
bit(wire
, i
- wire
->start_offset
);
1117 if (net_map
.count(net
) == 0)
1119 else if (wire
->port_input
)
1120 module
->connect(net_map_at(net
), bit
);
1122 module
->connect(bit
, net_map_at(net
));
1124 if (i
== portbus
->RightIndex())
1129 module
->fixup_ports();
1131 dict
<Net
*, char, hash_ptr_ops
> init_nets
;
1132 pool
<Net
*, hash_ptr_ops
> anyconst_nets
, anyseq_nets
;
1133 pool
<Net
*, hash_ptr_ops
> allconst_nets
, allseq_nets
;
1134 any_all_nets
.clear();
1136 FOREACH_NET_OF_NETLIST(nl
, mi
, net
)
1138 if (net
->IsRamNet())
1140 RTLIL::Memory
*memory
= new RTLIL::Memory
;
1141 memory
->name
= RTLIL::escape_id(net
->Name());
1142 log_assert(module
->count_id(memory
->name
) == 0);
1143 module
->memories
[memory
->name
] = memory
;
1145 int number_of_bits
= net
->Size();
1146 number_of_bits
= 1 << ceil_log2(number_of_bits
);
1147 int bits_in_word
= number_of_bits
;
1148 FOREACH_PORTREF_OF_NET(net
, si
, pr
) {
1149 if (pr
->GetInst()->Type() == OPER_READ_PORT
) {
1150 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->OutputSize());
1153 if (pr
->GetInst()->Type() == OPER_WRITE_PORT
|| pr
->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT
) {
1154 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->Input2Size());
1157 log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
1158 net
->Name(), pr
->GetInst()->View()->Owner()->Name(), pr
->GetInst()->Name());
1161 memory
->width
= bits_in_word
;
1162 memory
->size
= number_of_bits
/ bits_in_word
;
1164 const char *ascii_initdata
= net
->GetWideInitialValue();
1165 if (ascii_initdata
) {
1166 while (*ascii_initdata
!= 0 && *ascii_initdata
!= '\'')
1168 if (*ascii_initdata
== '\'')
1170 if (*ascii_initdata
!= 0) {
1171 log_assert(*ascii_initdata
== 'b');
1174 for (int word_idx
= 0; word_idx
< memory
->size
; word_idx
++) {
1175 Const initval
= Const(State::Sx
, memory
->width
);
1176 bool initval_valid
= false;
1177 for (int bit_idx
= memory
->width
-1; bit_idx
>= 0; bit_idx
--) {
1178 if (*ascii_initdata
== 0)
1180 if (*ascii_initdata
== '0' || *ascii_initdata
== '1') {
1181 initval
[bit_idx
] = (*ascii_initdata
== '0') ? State::S0
: State::S1
;
1182 initval_valid
= true;
1186 if (initval_valid
) {
1187 RTLIL::Cell
*cell
= module
->addCell(new_verific_id(net
), ID($meminit
));
1188 cell
->parameters
[ID::WORDS
] = 1;
1189 if (net
->GetOrigTypeRange()->LeftRangeBound() < net
->GetOrigTypeRange()->RightRangeBound())
1190 cell
->setPort(ID::ADDR
, word_idx
);
1192 cell
->setPort(ID::ADDR
, memory
->size
- word_idx
- 1);
1193 cell
->setPort(ID::DATA
, initval
);
1194 cell
->parameters
[ID::MEMID
] = RTLIL::Const(memory
->name
.str());
1195 cell
->parameters
[ID::ABITS
] = 32;
1196 cell
->parameters
[ID::WIDTH
] = memory
->width
;
1197 cell
->parameters
[ID::PRIORITY
] = RTLIL::Const(autoidx
-1);
1204 if (net
->GetInitialValue())
1205 init_nets
[net
] = net
->GetInitialValue();
1207 const char *rand_const_attr
= net
->GetAttValue(" rand_const");
1208 const char *rand_attr
= net
->GetAttValue(" rand");
1210 const char *anyconst_attr
= net
->GetAttValue("anyconst");
1211 const char *anyseq_attr
= net
->GetAttValue("anyseq");
1213 const char *allconst_attr
= net
->GetAttValue("allconst");
1214 const char *allseq_attr
= net
->GetAttValue("allseq");
1216 if (rand_const_attr
!= nullptr && (!strcmp(rand_const_attr
, "1") || !strcmp(rand_const_attr
, "'1'"))) {
1217 anyconst_nets
.insert(net
);
1218 any_all_nets
.insert(net
);
1220 else if (rand_attr
!= nullptr && (!strcmp(rand_attr
, "1") || !strcmp(rand_attr
, "'1'"))) {
1221 anyseq_nets
.insert(net
);
1222 any_all_nets
.insert(net
);
1224 else if (anyconst_attr
!= nullptr && (!strcmp(anyconst_attr
, "1") || !strcmp(anyconst_attr
, "'1'"))) {
1225 anyconst_nets
.insert(net
);
1226 any_all_nets
.insert(net
);
1228 else if (anyseq_attr
!= nullptr && (!strcmp(anyseq_attr
, "1") || !strcmp(anyseq_attr
, "'1'"))) {
1229 anyseq_nets
.insert(net
);
1230 any_all_nets
.insert(net
);
1232 else if (allconst_attr
!= nullptr && (!strcmp(allconst_attr
, "1") || !strcmp(allconst_attr
, "'1'"))) {
1233 allconst_nets
.insert(net
);
1234 any_all_nets
.insert(net
);
1236 else if (allseq_attr
!= nullptr && (!strcmp(allseq_attr
, "1") || !strcmp(allseq_attr
, "'1'"))) {
1237 allseq_nets
.insert(net
);
1238 any_all_nets
.insert(net
);
1241 if (net_map
.count(net
)) {
1242 if (verific_verbose
)
1243 log(" skipping net %s.\n", net
->Name());
1250 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| net
->IsUserDeclared() ? RTLIL::escape_id(net
->Name()) : new_verific_id(net
));
1252 if (verific_verbose
)
1253 log(" importing net %s as %s.\n", net
->Name(), log_id(wire_name
));
1255 RTLIL::Wire
*wire
= module
->addWire(wire_name
);
1256 import_attributes(wire
->attributes
, net
, nl
);
1258 net_map
[net
] = wire
;
1261 FOREACH_NETBUS_OF_NETLIST(nl
, mi
, netbus
)
1263 bool found_new_net
= false;
1264 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1) {
1265 net
= netbus
->ElementAtIndex(i
);
1266 if (net_map
.count(net
) == 0)
1267 found_new_net
= true;
1268 if (i
== netbus
->RightIndex())
1274 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| netbus
->IsUserDeclared() ? RTLIL::escape_id(netbus
->Name()) : new_verific_id(netbus
));
1276 if (verific_verbose
)
1277 log(" importing netbus %s as %s.\n", netbus
->Name(), log_id(wire_name
));
1279 RTLIL::Wire
*wire
= module
->addWire(wire_name
, netbus
->Size());
1280 wire
->start_offset
= min(netbus
->LeftIndex(), netbus
->RightIndex());
1282 FOREACH_NET_OF_NETBUS(netbus
, mibus
, net
) {
1284 import_attributes(wire
->attributes
, net
, nl
);
1288 RTLIL::Const initval
= Const(State::Sx
, GetSize(wire
));
1289 bool initval_valid
= false;
1291 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1)
1293 if (netbus
->ElementAtIndex(i
))
1295 int bitidx
= i
- wire
->start_offset
;
1296 net
= netbus
->ElementAtIndex(i
);
1297 RTLIL::SigBit
bit(wire
, bitidx
);
1299 if (init_nets
.count(net
)) {
1300 if (init_nets
.at(net
) == '0')
1301 initval
.bits
.at(bitidx
) = State::S0
;
1302 if (init_nets
.at(net
) == '1')
1303 initval
.bits
.at(bitidx
) = State::S1
;
1304 initval_valid
= true;
1305 init_nets
.erase(net
);
1308 if (net_map
.count(net
) == 0)
1311 module
->connect(bit
, net_map_at(net
));
1314 if (i
== netbus
->RightIndex())
1319 wire
->attributes
[ID::init
] = initval
;
1323 if (verific_verbose
)
1324 log(" skipping netbus %s.\n", netbus
->Name());
1327 SigSpec anyconst_sig
;
1329 SigSpec allconst_sig
;
1332 for (int i
= netbus
->RightIndex();; i
+= netbus
->IsUp() ? -1 : +1) {
1333 net
= netbus
->ElementAtIndex(i
);
1334 if (net
!= nullptr && anyconst_nets
.count(net
)) {
1335 anyconst_sig
.append(net_map_at(net
));
1336 anyconst_nets
.erase(net
);
1338 if (net
!= nullptr && anyseq_nets
.count(net
)) {
1339 anyseq_sig
.append(net_map_at(net
));
1340 anyseq_nets
.erase(net
);
1342 if (net
!= nullptr && allconst_nets
.count(net
)) {
1343 allconst_sig
.append(net_map_at(net
));
1344 allconst_nets
.erase(net
);
1346 if (net
!= nullptr && allseq_nets
.count(net
)) {
1347 allseq_sig
.append(net_map_at(net
));
1348 allseq_nets
.erase(net
);
1350 if (i
== netbus
->LeftIndex())
1354 if (GetSize(anyconst_sig
))
1355 module
->connect(anyconst_sig
, module
->Anyconst(new_verific_id(netbus
), GetSize(anyconst_sig
)));
1357 if (GetSize(anyseq_sig
))
1358 module
->connect(anyseq_sig
, module
->Anyseq(new_verific_id(netbus
), GetSize(anyseq_sig
)));
1360 if (GetSize(allconst_sig
))
1361 module
->connect(allconst_sig
, module
->Allconst(new_verific_id(netbus
), GetSize(allconst_sig
)));
1363 if (GetSize(allseq_sig
))
1364 module
->connect(allseq_sig
, module
->Allseq(new_verific_id(netbus
), GetSize(allseq_sig
)));
1367 for (auto it
: init_nets
)
1370 SigBit bit
= net_map_at(it
.first
);
1371 log_assert(bit
.wire
);
1373 if (bit
.wire
->attributes
.count(ID::init
))
1374 initval
= bit
.wire
->attributes
.at(ID::init
);
1376 while (GetSize(initval
) < GetSize(bit
.wire
))
1377 initval
.bits
.push_back(State::Sx
);
1379 if (it
.second
== '0')
1380 initval
.bits
.at(bit
.offset
) = State::S0
;
1381 if (it
.second
== '1')
1382 initval
.bits
.at(bit
.offset
) = State::S1
;
1384 bit
.wire
->attributes
[ID::init
] = initval
;
1387 for (auto net
: anyconst_nets
)
1388 module
->connect(net_map_at(net
), module
->Anyconst(new_verific_id(net
)));
1390 for (auto net
: anyseq_nets
)
1391 module
->connect(net_map_at(net
), module
->Anyseq(new_verific_id(net
)));
1393 pool
<Instance
*, hash_ptr_ops
> sva_asserts
;
1394 pool
<Instance
*, hash_ptr_ops
> sva_assumes
;
1395 pool
<Instance
*, hash_ptr_ops
> sva_covers
;
1396 pool
<Instance
*, hash_ptr_ops
> sva_triggers
;
1398 pool
<RTLIL::Cell
*> past_ffs
;
1400 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1402 RTLIL::IdString inst_name
= module
->uniquify(mode_names
|| inst
->IsUserDeclared() ? RTLIL::escape_id(inst
->Name()) : new_verific_id(inst
));
1404 if (verific_verbose
)
1405 log(" importing cell %s (%s) as %s.\n", inst
->Name(), inst
->View()->Owner()->Name(), log_id(inst_name
));
1408 goto import_verific_cells
;
1410 if (inst
->Type() == PRIM_PWR
) {
1411 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
1415 if (inst
->Type() == PRIM_GND
) {
1416 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
1420 if (inst
->Type() == PRIM_BUF
) {
1421 auto outnet
= inst
->GetOutput();
1422 if (!any_all_nets
.count(outnet
))
1423 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
1427 if (inst
->Type() == PRIM_X
) {
1428 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sx
);
1432 if (inst
->Type() == PRIM_Z
) {
1433 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sz
);
1437 if (inst
->Type() == OPER_READ_PORT
)
1439 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetInput()->Name()), nullptr);
1441 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst
->GetInput()->Name());
1443 int numchunks
= int(inst
->OutputSize()) / memory
->width
;
1444 int chunksbits
= ceil_log2(numchunks
);
1446 for (int i
= 0; i
< numchunks
; i
++)
1448 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1449 RTLIL::SigSpec data
= operatorOutput(inst
).extract(i
* memory
->width
, memory
->width
);
1451 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1452 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), ID($memrd
));
1453 cell
->parameters
[ID::MEMID
] = memory
->name
.str();
1454 cell
->parameters
[ID::CLK_ENABLE
] = false;
1455 cell
->parameters
[ID::CLK_POLARITY
] = true;
1456 cell
->parameters
[ID::TRANSPARENT
] = false;
1457 cell
->parameters
[ID::ABITS
] = GetSize(addr
);
1458 cell
->parameters
[ID::WIDTH
] = GetSize(data
);
1459 cell
->setPort(ID::CLK
, RTLIL::State::Sx
);
1460 cell
->setPort(ID::EN
, RTLIL::State::Sx
);
1461 cell
->setPort(ID::ADDR
, addr
);
1462 cell
->setPort(ID::DATA
, data
);
1467 if (inst
->Type() == OPER_WRITE_PORT
|| inst
->Type() == OPER_CLOCKED_WRITE_PORT
)
1469 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetOutput()->Name()), nullptr);
1471 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst
->GetInput()->Name());
1472 int numchunks
= int(inst
->Input2Size()) / memory
->width
;
1473 int chunksbits
= ceil_log2(numchunks
);
1475 for (int i
= 0; i
< numchunks
; i
++)
1477 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1478 RTLIL::SigSpec data
= operatorInput2(inst
).extract(i
* memory
->width
, memory
->width
);
1480 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1481 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), ID($memwr
));
1482 cell
->parameters
[ID::MEMID
] = memory
->name
.str();
1483 cell
->parameters
[ID::CLK_ENABLE
] = false;
1484 cell
->parameters
[ID::CLK_POLARITY
] = true;
1485 cell
->parameters
[ID::PRIORITY
] = 0;
1486 cell
->parameters
[ID::ABITS
] = GetSize(addr
);
1487 cell
->parameters
[ID::WIDTH
] = GetSize(data
);
1488 cell
->setPort(ID::EN
, RTLIL::SigSpec(net_map_at(inst
->GetControl())).repeat(GetSize(data
)));
1489 cell
->setPort(ID::CLK
, RTLIL::State::S0
);
1490 cell
->setPort(ID::ADDR
, addr
);
1491 cell
->setPort(ID::DATA
, data
);
1493 if (inst
->Type() == OPER_CLOCKED_WRITE_PORT
) {
1494 cell
->parameters
[ID::CLK_ENABLE
] = true;
1495 cell
->setPort(ID::CLK
, net_map_at(inst
->GetClock()));
1502 if (import_netlist_instance_cells(inst
, inst_name
))
1504 if (inst
->IsOperator() && !verific_sva_prims
.count(inst
->Type()))
1505 log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst
->View()->Owner()->Name());
1507 if (import_netlist_instance_gates(inst
, inst_name
))
1511 if (inst
->Type() == PRIM_SVA_ASSERT
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSERT
)
1512 sva_asserts
.insert(inst
);
1514 if (inst
->Type() == PRIM_SVA_ASSUME
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSUME
|| inst
->Type() == PRIM_SVA_RESTRICT
)
1515 sva_assumes
.insert(inst
);
1517 if (inst
->Type() == PRIM_SVA_COVER
|| inst
->Type() == PRIM_SVA_IMMEDIATE_COVER
)
1518 sva_covers
.insert(inst
);
1520 if (inst
->Type() == PRIM_SVA_TRIGGERED
)
1521 sva_triggers
.insert(inst
);
1523 if (inst
->Type() == OPER_SVA_STABLE
)
1525 VerificClocking
clocking(this, inst
->GetInput2Bit(0));
1526 log_assert(clocking
.disable_sig
== State::S0
);
1527 log_assert(clocking
.body_net
== nullptr);
1529 log_assert(inst
->Input1Size() == inst
->OutputSize());
1531 SigSpec sig_d
, sig_q
, sig_o
;
1532 sig_q
= module
->addWire(new_verific_id(inst
), inst
->Input1Size());
1534 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--){
1535 sig_d
.append(net_map_at(inst
->GetInput1Bit(i
)));
1536 sig_o
.append(net_map_at(inst
->GetOutputBit(i
)));
1539 if (verific_verbose
) {
1540 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1541 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1542 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1543 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1546 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1547 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1553 if (inst
->Type() == PRIM_SVA_STABLE
)
1555 VerificClocking
clocking(this, inst
->GetInput2());
1556 log_assert(clocking
.disable_sig
== State::S0
);
1557 log_assert(clocking
.body_net
== nullptr);
1559 SigSpec sig_d
= net_map_at(inst
->GetInput1());
1560 SigSpec sig_o
= net_map_at(inst
->GetOutput());
1561 SigSpec sig_q
= module
->addWire(new_verific_id(inst
));
1563 if (verific_verbose
) {
1564 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1565 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1566 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1567 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1570 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1571 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1577 if (inst
->Type() == PRIM_SVA_PAST
)
1579 VerificClocking
clocking(this, inst
->GetInput2());
1580 log_assert(clocking
.disable_sig
== State::S0
);
1581 log_assert(clocking
.body_net
== nullptr);
1583 SigBit sig_d
= net_map_at(inst
->GetInput1());
1584 SigBit sig_q
= net_map_at(inst
->GetOutput());
1586 if (verific_verbose
)
1587 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1588 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1590 past_ffs
.insert(clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
));
1596 if ((inst
->Type() == PRIM_SVA_ROSE
|| inst
->Type() == PRIM_SVA_FELL
))
1598 VerificClocking
clocking(this, inst
->GetInput2());
1599 log_assert(clocking
.disable_sig
== State::S0
);
1600 log_assert(clocking
.body_net
== nullptr);
1602 SigBit sig_d
= net_map_at(inst
->GetInput1());
1603 SigBit sig_o
= net_map_at(inst
->GetOutput());
1604 SigBit sig_q
= module
->addWire(new_verific_id(inst
));
1606 if (verific_verbose
)
1607 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1608 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1610 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1611 module
->addEq(new_verific_id(inst
), {sig_q
, sig_d
}, Const(inst
->Type() == PRIM_SVA_ROSE
? 1 : 2, 2), sig_o
);
1617 if (inst
->Type() == PRIM_YOSYSHQ_INITSTATE
)
1619 if (verific_verbose
)
1620 log(" adding YosysHQ init state\n");
1621 SigBit initstate
= module
->Initstate(new_verific_id(inst
));
1622 SigBit sig_o
= net_map_at(inst
->GetOutput());
1623 module
->connect(sig_o
, initstate
);
1629 if (!mode_keep
&& verific_sva_prims
.count(inst
->Type())) {
1630 if (verific_verbose
)
1631 log(" skipping SVA cell in non k-mode\n");
1635 if (inst
->Type() == PRIM_HDL_ASSERTION
)
1637 SigBit cond
= net_map_at(inst
->GetInput());
1639 if (verific_verbose
)
1640 log(" assert condition %s.\n", log_signal(cond
));
1642 const char *assume_attr
= nullptr; // inst->GetAttValue("assume");
1644 Cell
*cell
= nullptr;
1645 if (assume_attr
!= nullptr && !strcmp(assume_attr
, "1"))
1646 cell
= module
->addAssume(new_verific_id(inst
), cond
, State::S1
);
1648 cell
= module
->addAssert(new_verific_id(inst
), cond
, State::S1
);
1650 import_attributes(cell
->attributes
, inst
);
1654 if (inst
->IsPrimitive())
1657 log_error("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1659 if (!verific_sva_prims
.count(inst
->Type()))
1660 log_warning("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1663 import_verific_cells
:
1664 nl_todo
.insert(inst
->View());
1666 std::string inst_type
= inst
->View()->Owner()->Name();
1668 if (inst
->View()->IsOperator() || inst
->View()->IsPrimitive()) {
1669 inst_type
= "$verific$" + inst_type
;
1671 if (*inst
->View()->Name()) {
1673 inst_type
+= inst
->View()->Name();
1676 inst_type
= "\\" + sha1_if_contain_spaces(inst_type
);
1679 RTLIL::Cell
*cell
= module
->addCell(inst_name
, inst_type
);
1681 if (inst
->IsPrimitive() && mode_keep
)
1682 cell
->attributes
[ID::keep
] = 1;
1684 dict
<IdString
, vector
<SigBit
>> cell_port_conns
;
1686 if (verific_verbose
)
1687 log(" ports in verific db:\n");
1689 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
) {
1690 if (verific_verbose
)
1691 log(" .%s(%s)\n", pr
->GetPort()->Name(), pr
->GetNet()->Name());
1692 const char *port_name
= pr
->GetPort()->Name();
1693 int port_offset
= 0;
1694 if (pr
->GetPort()->Bus()) {
1695 port_name
= pr
->GetPort()->Bus()->Name();
1696 port_offset
= pr
->GetPort()->Bus()->IndexOf(pr
->GetPort()) -
1697 min(pr
->GetPort()->Bus()->LeftIndex(), pr
->GetPort()->Bus()->RightIndex());
1699 IdString port_name_id
= RTLIL::escape_id(port_name
);
1700 auto &sigvec
= cell_port_conns
[port_name_id
];
1701 if (GetSize(sigvec
) <= port_offset
) {
1702 SigSpec zwires
= module
->addWire(new_verific_id(inst
), port_offset
+1-GetSize(sigvec
));
1703 for (auto bit
: zwires
)
1704 sigvec
.push_back(bit
);
1706 sigvec
[port_offset
] = net_map_at(pr
->GetNet());
1709 if (verific_verbose
)
1710 log(" ports in yosys db:\n");
1712 for (auto &it
: cell_port_conns
) {
1713 if (verific_verbose
)
1714 log(" .%s(%s)\n", log_id(it
.first
), log_signal(it
.second
));
1715 cell
->setPort(it
.first
, it
.second
);
1721 for (auto inst
: sva_asserts
) {
1723 verific_import_sva_cover(this, inst
);
1724 verific_import_sva_assert(this, inst
);
1727 for (auto inst
: sva_assumes
)
1728 verific_import_sva_assume(this, inst
);
1730 for (auto inst
: sva_covers
)
1731 verific_import_sva_cover(this, inst
);
1733 for (auto inst
: sva_triggers
)
1734 verific_import_sva_trigger(this, inst
);
1736 merge_past_ffs(past_ffs
);
1741 pool
<SigBit
> non_ff_bits
;
1744 ff_types
.setup_internals_ff();
1745 ff_types
.setup_stdcells_mem();
1747 for (auto cell
: module
->cells())
1749 if (ff_types
.cell_known(cell
->type
))
1752 for (auto conn
: cell
->connections())
1754 if (!cell
->output(conn
.first
))
1757 for (auto bit
: conn
.second
)
1758 if (bit
.wire
!= nullptr)
1759 non_ff_bits
.insert(bit
);
1763 for (auto wire
: module
->wires())
1765 if (!wire
->attributes
.count(ID::init
))
1768 Const
&initval
= wire
->attributes
.at(ID::init
);
1769 for (int i
= 0; i
< GetSize(initval
); i
++)
1771 if (initval
[i
] != State::S0
&& initval
[i
] != State::S1
)
1774 if (non_ff_bits
.count(SigBit(wire
, i
)))
1775 initval
[i
] = State::Sx
;
1778 if (initval
.is_fully_undef())
1779 wire
->attributes
.erase(ID::init
);
1784 // ==================================================================
1786 VerificClocking::VerificClocking(VerificImporter
*importer
, Net
*net
, bool sva_at_only
)
1788 module
= importer
->module
;
1790 log_assert(importer
!= nullptr);
1791 log_assert(net
!= nullptr);
1793 Instance
*inst
= net
->Driver();
1795 if (inst
!= nullptr && inst
->Type() == PRIM_SVA_AT
)
1797 net
= inst
->GetInput1();
1798 body_net
= inst
->GetInput2();
1800 inst
= net
->Driver();
1802 Instance
*body_inst
= body_net
->Driver();
1803 if (body_inst
!= nullptr && body_inst
->Type() == PRIM_SVA_DISABLE_IFF
) {
1804 disable_net
= body_inst
->GetInput1();
1805 disable_sig
= importer
->net_map_at(disable_net
);
1806 body_net
= body_inst
->GetInput2();
1815 // Use while() instead of if() to work around VIPER #13453
1816 while (inst
!= nullptr && inst
->Type() == PRIM_SVA_POSEDGE
)
1818 net
= inst
->GetInput();
1819 inst
= net
->Driver();;
1822 if (inst
!= nullptr && inst
->Type() == PRIM_INV
)
1824 net
= inst
->GetInput();
1825 inst
= net
->Driver();;
1829 // Detect clock-enable circuit
1831 if (inst
== nullptr || inst
->Type() != PRIM_AND
)
1834 Net
*net_dlatch
= inst
->GetInput1();
1835 Instance
*inst_dlatch
= net_dlatch
->Driver();
1837 if (inst_dlatch
== nullptr || inst_dlatch
->Type() != PRIM_DLATCHRS
)
1840 if (!inst_dlatch
->GetSet()->IsGnd() || !inst_dlatch
->GetReset()->IsGnd())
1843 Net
*net_enable
= inst_dlatch
->GetInput();
1844 Net
*net_not_clock
= inst_dlatch
->GetControl();
1846 if (net_enable
== nullptr || net_not_clock
== nullptr)
1849 Instance
*inst_not_clock
= net_not_clock
->Driver();
1851 if (inst_not_clock
== nullptr || inst_not_clock
->Type() != PRIM_INV
)
1854 Net
*net_clock1
= inst_not_clock
->GetInput();
1855 Net
*net_clock2
= inst
->GetInput2();
1857 if (net_clock1
== nullptr || net_clock1
!= net_clock2
)
1860 enable_net
= net_enable
;
1861 enable_sig
= importer
->net_map_at(enable_net
);
1864 inst
= net
->Driver();;
1867 // Detect condition expression
1869 if (body_net
== nullptr)
1872 Instance
*inst_mux
= body_net
->Driver();
1874 if (inst_mux
== nullptr || inst_mux
->Type() != PRIM_MUX
)
1877 if (!inst_mux
->GetInput1()->IsPwr())
1880 Net
*sva_net
= inst_mux
->GetInput2();
1881 if (!verific_is_sva_net(importer
, sva_net
))
1885 cond_net
= inst_mux
->GetControl();
1889 clock_sig
= importer
->net_map_at(clock_net
);
1891 const char *gclk_attr
= clock_net
->GetAttValue("gclk");
1892 if (gclk_attr
!= nullptr && (!strcmp(gclk_attr
, "1") || !strcmp(gclk_attr
, "'1'")))
1896 Cell
*VerificClocking::addDff(IdString name
, SigSpec sig_d
, SigSpec sig_q
, Const init_value
)
1898 log_assert(GetSize(sig_d
) == GetSize(sig_q
));
1900 if (GetSize(init_value
) != 0) {
1901 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1902 if (sig_q
.is_wire()) {
1903 sig_q
.as_wire()->attributes
[ID::init
] = init_value
;
1905 Wire
*w
= module
->addWire(NEW_ID
, GetSize(sig_q
));
1906 w
->attributes
[ID::init
] = init_value
;
1907 module
->connect(sig_q
, w
);
1912 if (enable_sig
!= State::S1
)
1913 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1915 if (disable_sig
!= State::S0
) {
1916 log_assert(gclk
== false);
1917 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1918 return module
->addAdff(name
, clock_sig
, disable_sig
, sig_d
, sig_q
, init_value
, posedge
);
1922 return module
->addFf(name
, sig_d
, sig_q
);
1924 return module
->addDff(name
, clock_sig
, sig_d
, sig_q
, posedge
);
1927 Cell
*VerificClocking::addAdff(IdString name
, RTLIL::SigSpec sig_arst
, SigSpec sig_d
, SigSpec sig_q
, Const arst_value
)
1929 log_assert(gclk
== false);
1930 log_assert(disable_sig
== State::S0
);
1933 if (enable_sig
!= State::S1
)
1934 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1936 return module
->addAdff(name
, clock_sig
, sig_arst
, sig_d
, sig_q
, arst_value
, posedge
);
1939 Cell
*VerificClocking::addDffsr(IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, SigSpec sig_d
, SigSpec sig_q
)
1941 log_assert(gclk
== false);
1942 log_assert(disable_sig
== State::S0
);
1945 if (enable_sig
!= State::S1
)
1946 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1948 return module
->addDffsr(name
, clock_sig
, sig_set
, sig_clr
, sig_d
, sig_q
, posedge
);
1951 Cell
*VerificClocking::addAldff(IdString name
, RTLIL::SigSpec sig_aload
, RTLIL::SigSpec sig_adata
, SigSpec sig_d
, SigSpec sig_q
)
1953 log_assert(gclk
== false);
1954 log_assert(disable_sig
== State::S0
);
1957 if (enable_sig
!= State::S1
)
1958 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1960 return module
->addAldff(name
, clock_sig
, sig_aload
, sig_d
, sig_q
, sig_adata
, posedge
);
1963 // ==================================================================
1965 struct VerificExtNets
1967 int portname_cnt
= 0;
1969 // a map from Net to the same Net one level up in the design hierarchy
1970 std::map
<Net
*, Net
*> net_level_up_drive_up
;
1971 std::map
<Net
*, Net
*> net_level_up_drive_down
;
1973 Net
*route_up(Net
*net
, bool drive_up
, Net
*final_net
= nullptr)
1975 auto &net_level_up
= drive_up
? net_level_up_drive_up
: net_level_up_drive_down
;
1977 if (net_level_up
.count(net
) == 0)
1979 Netlist
*nl
= net
->Owner();
1981 // Simply return if Netlist is not unique
1982 log_assert(nl
->NumOfRefs() == 1);
1984 Instance
*up_inst
= (Instance
*)nl
->GetReferences()->GetLast();
1985 Netlist
*up_nl
= up_inst
->Owner();
1988 string name
= stringf("___extnets_%d", portname_cnt
++);
1989 Port
*new_port
= new Port(name
.c_str(), drive_up
? DIR_OUT
: DIR_IN
);
1991 net
->Connect(new_port
);
1993 // create new Net in up Netlist
1994 Net
*new_net
= final_net
;
1995 if (new_net
== nullptr || new_net
->Owner() != up_nl
) {
1996 new_net
= new Net(name
.c_str());
1997 up_nl
->Add(new_net
);
1999 up_inst
->Connect(new_port
, new_net
);
2001 net_level_up
[net
] = new_net
;
2004 return net_level_up
.at(net
);
2007 Net
*route_up(Net
*net
, bool drive_up
, Netlist
*dest
, Net
*final_net
= nullptr)
2009 while (net
->Owner() != dest
)
2010 net
= route_up(net
, drive_up
, final_net
);
2011 if (final_net
!= nullptr)
2012 log_assert(net
== final_net
);
2016 Netlist
*find_common_ancestor(Netlist
*A
, Netlist
*B
)
2018 std::set
<Netlist
*> ancestors_of_A
;
2020 Netlist
*cursor
= A
;
2022 ancestors_of_A
.insert(cursor
);
2023 if (cursor
->NumOfRefs() != 1)
2025 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
2030 if (ancestors_of_A
.count(cursor
))
2032 if (cursor
->NumOfRefs() != 1)
2034 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
2037 log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A
).c_str(), get_full_netlist_name(B
).c_str());
2040 void run(Netlist
*nl
)
2046 vector
<tuple
<Instance
*, Port
*, Net
*>> todo_connect
;
2048 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
2051 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
2052 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
)
2054 Port
*port
= pr
->GetPort();
2055 Net
*net
= pr
->GetNet();
2057 if (!net
->IsExternalTo(nl
))
2060 if (verific_verbose
)
2061 log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl
).c_str(), inst
->Name(), port
->Name());
2063 Netlist
*ext_nl
= net
->Owner();
2065 if (verific_verbose
)
2066 log(" external net owner: %s\n", get_full_netlist_name(ext_nl
).c_str());
2068 Netlist
*ca_nl
= find_common_ancestor(nl
, ext_nl
);
2070 if (verific_verbose
)
2071 log(" common ancestor: %s\n", get_full_netlist_name(ca_nl
).c_str());
2073 Net
*ca_net
= route_up(net
, !port
->IsOutput(), ca_nl
);
2074 Net
*new_net
= ca_net
;
2078 if (verific_verbose
)
2079 log(" net in common ancestor: %s\n", ca_net
->Name());
2081 string name
= stringf("___extnets_%d", portname_cnt
++);
2082 new_net
= new Net(name
.c_str());
2085 Net
*n
= route_up(new_net
, port
->IsOutput(), ca_nl
, ca_net
);
2086 log_assert(n
== ca_net
);
2089 if (verific_verbose
)
2090 log(" new local net: %s\n", new_net
->Name());
2092 log_assert(!new_net
->IsExternalTo(nl
));
2093 todo_connect
.push_back(tuple
<Instance
*, Port
*, Net
*>(inst
, port
, new_net
));
2096 for (auto it
: todo_connect
) {
2097 get
<0>(it
)->Disconnect(get
<1>(it
));
2098 get
<0>(it
)->Connect(get
<1>(it
), get
<2>(it
));
2103 void verific_import(Design
*design
, const std::map
<std::string
,std::string
> ¶meters
, std::string top
)
2105 verific_sva_fsm_limit
= 16;
2107 std::set
<Netlist
*> nl_todo
, nl_done
;
2109 VeriLibrary
*veri_lib
= veri_file::GetLibrary("work", 1);
2110 Array
*netlists
= NULL
;
2111 Array veri_libs
, vhdl_libs
;
2112 #ifdef VERIFIC_VHDL_SUPPORT
2113 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary("work", 1);
2114 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
2116 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
2118 Map
verific_params(STRING_HASH
);
2119 for (const auto &i
: parameters
)
2120 verific_params
.Insert(i
.first
.c_str(), i
.second
.c_str());
2122 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
2123 InitialAssertions::Rewrite("work", &verific_params
);
2127 netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, &verific_params
);
2130 Array veri_modules
, vhdl_units
;
2133 VeriModule
*veri_module
= veri_lib
->GetModule(top
.c_str(), 1);
2135 veri_modules
.InsertLast(veri_module
);
2138 // Also elaborate all root modules since they may contain bind statements
2140 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
2141 if (!veri_module
->IsRootModule()) continue;
2142 veri_modules
.InsertLast(veri_module
);
2146 #ifdef VERIFIC_VHDL_SUPPORT
2148 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(top
.c_str());
2150 vhdl_units
.InsertLast(vhdl_unit
);
2153 netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, &verific_params
);
2159 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
2160 if (top
.empty() && nl
->CellBaseName() != top
)
2162 nl
->AddAtt(new Att(" \\top", NULL
));
2168 if (!verific_error_msg
.empty())
2169 log_error("%s\n", verific_error_msg
.c_str());
2171 for (auto nl
: nl_todo
)
2172 nl
->ChangePortBusStructures(1 /* hierarchical */);
2174 VerificExtNets worker
;
2175 for (auto nl
: nl_todo
)
2178 while (!nl_todo
.empty()) {
2179 Netlist
*nl
= *nl_todo
.begin();
2180 if (nl_done
.count(nl
) == 0) {
2181 VerificImporter
importer(false, false, false, false, false, false, false);
2182 importer
.import_netlist(design
, nl
, nl_todo
, nl
->Owner()->Name() == top
);
2189 #ifdef VERIFIC_VHDL_SUPPORT
2193 verific_incdirs
.clear();
2194 verific_libdirs
.clear();
2195 verific_import_pending
= false;
2197 if (!verific_error_msg
.empty())
2198 log_error("%s\n", verific_error_msg
.c_str());
2202 #endif /* YOSYS_ENABLE_VERIFIC */
2204 PRIVATE_NAMESPACE_BEGIN
2206 #ifdef YOSYS_ENABLE_VERIFIC
2207 bool check_noverific_env()
2209 const char *e
= getenv("YOSYS_NOVERIFIC");
2218 struct VerificPass
: public Pass
{
2219 VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
2220 void help() override
2222 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2224 log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
2226 log("Load the specified Verilog/SystemVerilog files into Verific.\n");
2228 log("All files specified in one call to this command are one compilation unit.\n");
2229 log("Files passed to different calls to this command are treated as belonging to\n");
2230 log("different compilation units.\n");
2232 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2233 log("the language version (and before file names) to set additional verilog defines.\n");
2234 log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
2237 log(" verific -formal <verilog-file>..\n");
2239 log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
2242 #ifdef VERIFIC_VHDL_SUPPORT
2243 log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2245 log("Load the specified VHDL files into Verific.\n");
2249 log(" verific {-f|-F} <command-file>\n");
2251 log("Load and execute the specified command file.\n");
2253 log("Command file parser supports following commands:\n");
2254 log(" +define - defines macro\n");
2255 log(" -u - upper case all identifier (makes Verilog parser case insensitive)\n");
2256 log(" -v - register library name (file)\n");
2257 log(" -y - register library name (directory)\n");
2258 log(" +incdir - specify include dir\n");
2259 log(" +libext - specify library extension\n");
2260 log(" +liborder - add library in ordered list\n");
2261 log(" +librescan - unresolved modules will be always searched starting with the first\n");
2262 log(" library specified by -y/-v options.\n");
2263 log(" -f/-file - nested -f option\n");
2264 log(" -F - nested -F option\n");
2266 log(" parse mode:\n");
2268 log(" +systemverilogext\n");
2270 log(" +verilog1995ext\n");
2271 log(" +verilog2001ext\n");
2272 log(" -sverilog\n");
2275 log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2277 log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
2278 log("(default library when -work is not present: \"work\")\n");
2281 log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2283 log("Look up external definitions in the specified library.\n");
2284 log("(-L may be used more than once)\n");
2287 log(" verific -vlog-incdir <directory>..\n");
2289 log("Add Verilog include directories.\n");
2292 log(" verific -vlog-libdir <directory>..\n");
2294 log("Add Verilog library directories. Verific will search in this directories to\n");
2295 log("find undefined modules.\n");
2298 log(" verific -vlog-define <macro>[=<value>]..\n");
2300 log("Add Verilog defines.\n");
2303 log(" verific -vlog-undef <macro>..\n");
2305 log("Remove Verilog defines previously set with -vlog-define.\n");
2308 log(" verific -set-error <msg_id>..\n");
2309 log(" verific -set-warning <msg_id>..\n");
2310 log(" verific -set-info <msg_id>..\n");
2311 log(" verific -set-ignore <msg_id>..\n");
2313 log("Set message severity. <msg_id> is the string in square brackets when a message\n");
2314 log("is printed, such as VERI-1209.\n");
2317 log(" verific -import [options] <top-module>..\n");
2319 log("Elaborate the design for the specified top modules, import to Yosys and\n");
2320 log("reset the internal state of Verific.\n");
2322 log("Import options:\n");
2325 log(" Elaborate all modules, not just the hierarchy below the given top\n");
2326 log(" modules. With this option the list of modules to import is optional.\n");
2329 log(" Create a gate-level netlist.\n");
2332 log(" Flatten the design in Verific before importing.\n");
2335 log(" Resolve references to external nets by adding module ports as needed.\n");
2337 log(" -autocover\n");
2338 log(" Generate automatic cover statements for all asserts\n");
2340 log(" -fullinit\n");
2341 log(" Keep all register initializations, even those for non-FF registers.\n");
2343 log(" -chparam name value \n");
2344 log(" Elaborate the specified top modules (all modules when -all given) using\n");
2345 log(" this parameter value. Modules on which this parameter does not exist will\n");
2346 log(" cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
2347 log(" can be specified multiple times to override multiple parameters.\n");
2348 log(" String values must be passed in double quotes (\").\n");
2351 log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
2353 log("The following additional import options are useful for debugging the Verific\n");
2354 log("bindings (for Yosys and/or Verific developers):\n");
2357 log(" Keep going after an unsupported verific primitive is found. The\n");
2358 log(" unsupported primitive is added as blockbox module to the design.\n");
2359 log(" This will also add all SVA related cells to the design parallel to\n");
2360 log(" the checker logic inferred by it.\n");
2363 log(" Import Verific netlist as-is without translating to Yosys cell types. \n");
2366 log(" Ignore SVA properties, do not infer checker logic.\n");
2369 log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
2372 log(" Keep all Verific names on instances and nets. By default only\n");
2373 log(" user-declared names are preserved.\n");
2375 log(" -d <dump_file>\n");
2376 log(" Dump the Verific netlist as a verilog file.\n");
2379 log(" verific [-work <libname>] -pp [options] <filename> [<module>]..\n");
2381 log("Pretty print design (or just module) to the specified file from the\n");
2382 log("specified library. (default library when -work is not present: \"work\")\n");
2384 log("Pretty print options:\n");
2387 log(" Save output for Verilog/SystemVerilog design modules (default).\n");
2390 log(" Save output for VHDL design units.\n");
2393 log(" verific -app <application>..\n");
2395 log("Execute YosysHQ formal application on loaded Verilog files.\n");
2397 log("Application options:\n");
2399 log(" -module <module>\n");
2400 log(" Run formal application only on specified module.\n");
2402 log(" -blacklist <filename[:lineno]>\n");
2403 log(" Do not run application on modules from files that match the filename\n");
2404 log(" or filename and line number if provided in such format.\n");
2405 log(" Parameter can also contain comma separated list of file locations.\n");
2407 log(" -blfile <file>\n");
2408 log(" Do not run application on locations specified in file, they can represent filename\n");
2409 log(" or filename and location in file.\n");
2411 log("Applications:\n");
2413 #if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_FORMALAPPS)
2414 VerificFormalApplications vfa
;
2415 log("%s\n",vfa
.GetHelp().c_str());
2417 log(" WARNING: Applications only available in commercial build.\n");
2422 log(" verific -template <name> <top_module>..\n");
2424 log("Generate template for specified top module of loaded design.\n");
2426 log("Template options:\n");
2429 log(" Specifies output file for generated template, by default output is stdout\n");
2431 log(" -chparam name value \n");
2432 log(" Generate template using this parameter value. Otherwise default parameter\n");
2433 log(" values will be used for templat generate functionality. This option\n");
2434 log(" can be specified multiple times to override multiple parameters.\n");
2435 log(" String values must be passed in double quotes (\").\n");
2437 log("Templates:\n");
2439 #if defined(YOSYS_ENABLE_VERIFIC) && defined(YOSYSHQ_VERIFIC_TEMPLATES)
2440 VerificTemplateGenerator vfg
;
2441 log("%s\n",vfg
.GetHelp().c_str());
2443 log(" WARNING: Templates only available in commercial build.\n");
2446 log("Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n");
2447 log("https://www.yosyshq.com/\n");
2449 log("Contact office@yosyshq.com for free evaluation\n");
2450 log("binaries of YosysHQ Tabby CAD Suite.\n");
2453 #ifdef YOSYS_ENABLE_VERIFIC
2454 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
2456 static bool set_verific_global_flags
= true;
2458 if (check_noverific_env())
2459 log_cmd_error("This version of Yosys is built without Verific support.\n"
2461 "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
2462 "https://www.yosyshq.com/\n"
2464 "Contact office@yosyshq.com for free evaluation\n"
2465 "binaries of YosysHQ Tabby CAD Suite.\n");
2467 log_header(design
, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
2469 if (set_verific_global_flags
)
2471 Message::SetConsoleOutput(0);
2472 Message::RegisterCallBackMsg(msg_func
);
2474 RuntimeFlags::SetVar("db_preserve_user_nets", 1);
2475 RuntimeFlags::SetVar("db_allow_external_nets", 1);
2476 RuntimeFlags::SetVar("db_infer_wide_operators", 1);
2477 RuntimeFlags::SetVar("db_infer_set_reset_registers", 0);
2479 RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
2480 RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
2482 #ifdef VERIFIC_VHDL_SUPPORT
2483 RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
2484 RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
2486 RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
2487 RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
2489 RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
2490 //RuntimeFlags::SetVar("vhdl_preserve_comments",1);
2492 RuntimeFlags::SetVar("veri_preserve_assignments", 1);
2493 RuntimeFlags::SetVar("veri_preserve_comments",1);
2495 // Workaround for VIPER #13851
2496 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
2498 // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
2499 Message::SetMessageType("VERI-1063", VERIFIC_ERROR
);
2501 // https://github.com/YosysHQ/yosys/issues/1055
2502 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
2504 #ifndef DB_PRESERVE_INITIAL_VALUE
2505 # warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
2508 set_verific_global_flags
= false;
2511 verific_verbose
= 0;
2512 verific_sva_fsm_limit
= 16;
2514 const char *release_str
= Message::ReleaseString();
2515 time_t release_time
= Message::ReleaseDate();
2516 char *release_tmstr
= ctime(&release_time
);
2518 if (release_str
== nullptr)
2519 release_str
= "(no release string)";
2521 for (char *p
= release_tmstr
; *p
; p
++)
2522 if (*p
== '\n') *p
= 0;
2524 log("Built with Verific %s, released at %s.\n", release_str
, release_tmstr
);
2527 std::string work
= "work";
2529 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-set-error" || args
[argidx
] == "-set-warning" ||
2530 args
[argidx
] == "-set-info" || args
[argidx
] == "-set-ignore"))
2532 msg_type_t new_type
;
2534 if (args
[argidx
] == "-set-error")
2535 new_type
= VERIFIC_ERROR
;
2536 else if (args
[argidx
] == "-set-warning")
2537 new_type
= VERIFIC_WARNING
;
2538 else if (args
[argidx
] == "-set-info")
2539 new_type
= VERIFIC_INFO
;
2540 else if (args
[argidx
] == "-set-ignore")
2541 new_type
= VERIFIC_IGNORE
;
2545 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2546 Message::SetMessageType(args
[argidx
].c_str(), new_type
);
2551 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-incdir") {
2552 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2553 verific_incdirs
.push_back(args
[argidx
]);
2557 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-libdir") {
2558 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2559 verific_libdirs
.push_back(args
[argidx
]);
2563 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-define") {
2564 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2565 string name
= args
[argidx
];
2566 size_t equal
= name
.find('=');
2567 if (equal
!= std::string::npos
) {
2568 string value
= name
.substr(equal
+1);
2569 name
= name
.substr(0, equal
);
2570 veri_file::DefineCmdLineMacro(name
.c_str(), value
.c_str());
2572 veri_file::DefineCmdLineMacro(name
.c_str());
2578 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-undef") {
2579 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2580 string name
= args
[argidx
];
2581 veri_file::UndefineMacro(name
.c_str());
2586 veri_file::RemoveAllLOptions();
2587 for (; argidx
< GetSize(args
); argidx
++)
2589 if (args
[argidx
] == "-work" && argidx
+1 < GetSize(args
)) {
2590 work
= args
[++argidx
];
2593 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2594 veri_file::AddLOption(args
[++argidx
].c_str());
2600 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-f" || args
[argidx
] == "-F"))
2602 unsigned verilog_mode
= veri_file::VERILOG_95
; // default recommended by Verific
2604 Verific::veri_file::f_file_flags flags
= (args
[argidx
] == "-f") ? veri_file::F_FILE_NONE
: veri_file::F_FILE_CAPITAL
;
2605 Array
*file_names
= veri_file::ProcessFFile(args
[++argidx
].c_str(), flags
, verilog_mode
);
2607 veri_file::DefineMacro("VERIFIC");
2609 if (!veri_file::AnalyzeMultipleFiles(file_names
, verilog_mode
, work
.c_str(), veri_file::MFCU
)) {
2610 verific_error_msg
.clear();
2611 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2615 verific_import_pending
= true;
2619 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vlog95" || args
[argidx
] == "-vlog2k" || args
[argidx
] == "-sv2005" ||
2620 args
[argidx
] == "-sv2009" || args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal"))
2623 unsigned verilog_mode
;
2625 if (args
[argidx
] == "-vlog95")
2626 verilog_mode
= veri_file::VERILOG_95
;
2627 else if (args
[argidx
] == "-vlog2k")
2628 verilog_mode
= veri_file::VERILOG_2K
;
2629 else if (args
[argidx
] == "-sv2005")
2630 verilog_mode
= veri_file::SYSTEM_VERILOG_2005
;
2631 else if (args
[argidx
] == "-sv2009")
2632 verilog_mode
= veri_file::SYSTEM_VERILOG_2009
;
2633 else if (args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal")
2634 verilog_mode
= veri_file::SYSTEM_VERILOG
;
2638 veri_file::DefineMacro("VERIFIC");
2639 veri_file::DefineMacro(args
[argidx
] == "-formal" ? "FORMAL" : "SYNTHESIS");
2641 for (argidx
++; argidx
< GetSize(args
) && GetSize(args
[argidx
]) >= 2 && args
[argidx
].compare(0, 2, "-D") == 0; argidx
++) {
2642 std::string name
= args
[argidx
].substr(2);
2643 if (args
[argidx
] == "-D") {
2644 if (++argidx
>= GetSize(args
))
2646 name
= args
[argidx
];
2648 size_t equal
= name
.find('=');
2649 if (equal
!= std::string::npos
) {
2650 string value
= name
.substr(equal
+1);
2651 name
= name
.substr(0, equal
);
2652 veri_file::DefineMacro(name
.c_str(), value
.c_str());
2654 veri_file::DefineMacro(name
.c_str());
2658 for (auto &dir
: verific_incdirs
)
2659 veri_file::AddIncludeDir(dir
.c_str());
2660 for (auto &dir
: verific_libdirs
)
2661 veri_file::AddYDir(dir
.c_str());
2663 while (argidx
< GetSize(args
))
2664 file_names
.Insert(args
[argidx
++].c_str());
2666 if (!veri_file::AnalyzeMultipleFiles(&file_names
, verilog_mode
, work
.c_str(), veri_file::MFCU
)) {
2667 verific_error_msg
.clear();
2668 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2671 verific_import_pending
= true;
2675 #ifdef VERIFIC_VHDL_SUPPORT
2676 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl87") {
2677 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
2678 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2679 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_87
))
2680 log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args
[argidx
].c_str());
2681 verific_import_pending
= true;
2685 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl93") {
2686 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2687 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2688 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_93
))
2689 log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args
[argidx
].c_str());
2690 verific_import_pending
= true;
2694 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl2k") {
2695 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2696 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2697 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2K
))
2698 log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args
[argidx
].c_str());
2699 verific_import_pending
= true;
2703 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vhdl2008" || args
[argidx
] == "-vhdl")) {
2704 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
2705 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2706 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2008
))
2707 log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args
[argidx
].c_str());
2708 verific_import_pending
= true;
2713 #ifdef YOSYSHQ_VERIFIC_FORMALAPPS
2714 if (argidx
< GetSize(args
) && args
[argidx
] == "-app")
2716 if (!(argidx
+1 < GetSize(args
)))
2717 cmd_error(args
, argidx
, "No formal application specified.\n");
2719 VerificFormalApplications vfa
;
2720 auto apps
= vfa
.GetApps();
2721 std::string app
= args
[++argidx
];
2722 std::vector
<std::string
> blacklists
;
2723 if (apps
.find(app
) == apps
.end())
2724 log_cmd_error("Application '%s' does not exist.\n", app
.c_str());
2726 FormalApplication
*application
= apps
[app
];
2727 application
->setLogger([](std::string msg
) { log("%s",msg
.c_str()); } );
2728 VeriModule
*selected_module
= nullptr;
2730 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2732 if (application
->checkParams(args
, argidx
, error
)) {
2734 cmd_error(args
, argidx
, error
);
2738 if (args
[argidx
] == "-module" && argidx
< GetSize(args
)) {
2739 if (!(argidx
+1 < GetSize(args
)))
2740 cmd_error(args
, argidx
+1, "No module name specified.\n");
2741 std::string module
= args
[++argidx
];
2742 VeriLibrary
* veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2743 selected_module
= veri_lib
? veri_lib
->GetModule(module
.c_str(), 1) : nullptr;
2744 if (!selected_module
) {
2745 log_error("Can't find module '%s'.\n", module
.c_str());
2749 if (args
[argidx
] == "-blacklist" && argidx
< GetSize(args
)) {
2750 if (!(argidx
+1 < GetSize(args
)))
2751 cmd_error(args
, argidx
+1, "No blacklist specified.\n");
2753 std::string line
= args
[++argidx
];
2755 while (!(p
= next_token(line
, ",\t\r\n ")).empty())
2756 blacklists
.push_back(p
);
2759 if (args
[argidx
] == "-blfile" && argidx
< GetSize(args
)) {
2760 if (!(argidx
+1 < GetSize(args
)))
2761 cmd_error(args
, argidx
+1, "No blacklist file specified.\n");
2762 std::string fn
= args
[++argidx
];
2763 std::ifstream
f(fn
);
2765 log_cmd_error("Can't open blacklist file '%s'!\n", fn
.c_str());
2768 while (std::getline(f
, line
)) {
2769 while (!(p
= next_token(line
, ",\t\r\n ")).empty())
2770 blacklists
.push_back(p
);
2776 if (argidx
< GetSize(args
))
2777 cmd_error(args
, argidx
, "unknown option/parameter");
2779 application
->setBlacklists(&blacklists
);
2780 application
->setSingleModuleMode(selected_module
!=nullptr);
2782 const char *err
= application
->validate();
2784 cmd_error(args
, argidx
, err
);
2787 VeriLibrary
*veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2788 log("Running formal application '%s'.\n", app
.c_str());
2790 if (selected_module
) {
2792 if (!application
->execute(selected_module
, out
))
2793 log_error("%s", out
.c_str());
2796 VeriModule
*module
;
2797 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, module
) {
2799 if (!application
->execute(module
, out
)) {
2800 log_error("%s", out
.c_str());
2808 if (argidx
< GetSize(args
) && args
[argidx
] == "-pp")
2810 const char* filename
= nullptr;
2811 const char* module
= nullptr;
2812 bool mode_vhdl
= false;
2813 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2814 #ifdef VERIFIC_VHDL_SUPPORT
2815 if (args
[argidx
] == "-vhdl") {
2820 if (args
[argidx
] == "-verilog") {
2825 if (args
[argidx
].compare(0, 1, "-") == 0) {
2826 cmd_error(args
, argidx
, "unknown option");
2831 filename
= args
[argidx
].c_str();
2835 log_cmd_error("Only one module can be specified.\n");
2836 module
= args
[argidx
].c_str();
2839 if (argidx
< GetSize(args
))
2840 cmd_error(args
, argidx
, "unknown option/parameter");
2843 log_cmd_error("Filname must be specified.\n");
2846 #ifdef VERIFIC_VHDL_SUPPORT
2847 vhdl_file::PrettyPrint(filename
, module
, work
.c_str());
2852 veri_file::PrettyPrint(filename
, module
, work
.c_str());
2856 #ifdef YOSYSHQ_VERIFIC_TEMPLATES
2857 if (argidx
< GetSize(args
) && args
[argidx
] == "-template")
2859 if (!(argidx
+1 < GetSize(args
)))
2860 cmd_error(args
, argidx
+1, "No template type specified.\n");
2862 VerificTemplateGenerator vfg
;
2863 auto gens
= vfg
.GetGenerators();
2864 std::string app
= args
[++argidx
];
2865 if (gens
.find(app
) == gens
.end())
2866 log_cmd_error("Template generator '%s' does not exist.\n", app
.c_str());
2867 TemplateGenerator
*generator
= gens
[app
];
2868 if (!(argidx
+1 < GetSize(args
)))
2869 cmd_error(args
, argidx
+1, "No top module specified.\n");
2870 generator
->setLogger([](std::string msg
) { log("%s",msg
.c_str()); } );
2872 std::string module
= args
[++argidx
];
2873 VeriLibrary
* veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2874 VeriModule
*veri_module
= veri_lib
? veri_lib
->GetModule(module
.c_str(), 1) : nullptr;
2876 log_error("Can't find module/unit '%s'.\n", module
.c_str());
2879 log("Template '%s' is running for module '%s'.\n", app
.c_str(),module
.c_str());
2881 Map
parameters(STRING_HASH
);
2882 const char *out_filename
= nullptr;
2884 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2886 if (generator
->checkParams(args
, argidx
, error
)) {
2888 cmd_error(args
, argidx
, error
);
2892 if (args
[argidx
] == "-chparam" && argidx
< GetSize(args
)) {
2893 if (!(argidx
+1 < GetSize(args
)))
2894 cmd_error(args
, argidx
+1, "No param name specified.\n");
2895 if (!(argidx
+2 < GetSize(args
)))
2896 cmd_error(args
, argidx
+2, "No param value specified.\n");
2898 const std::string
&key
= args
[++argidx
];
2899 const std::string
&value
= args
[++argidx
];
2900 unsigned new_insertion
= parameters
.Insert(key
.c_str(), value
.c_str(),
2901 1 /* force_overwrite */);
2903 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key
.c_str());
2907 if (args
[argidx
] == "-out" && argidx
< GetSize(args
)) {
2908 if (!(argidx
+1 < GetSize(args
)))
2909 cmd_error(args
, argidx
+1, "No output file specified.\n");
2910 out_filename
= args
[++argidx
].c_str();
2916 if (argidx
< GetSize(args
))
2917 cmd_error(args
, argidx
, "unknown option/parameter");
2919 const char *err
= generator
->validate();
2921 cmd_error(args
, argidx
, err
);
2924 if (!generator
->generate(veri_module
, val
, ¶meters
))
2925 log_error("%s", val
.c_str());
2929 of
= fopen(out_filename
, "w");
2931 log_error("Can't open '%s' for writing: %s\n", out_filename
, strerror(errno
));
2932 log("Writing output to '%s'\n",out_filename
);
2934 fprintf(of
, "%s\n",val
.c_str());
2941 if (GetSize(args
) > argidx
&& args
[argidx
] == "-import")
2943 std::set
<Netlist
*> nl_todo
, nl_done
;
2944 bool mode_all
= false, mode_gates
= false, mode_keep
= false;
2945 bool mode_nosva
= false, mode_names
= false, mode_verific
= false;
2946 bool mode_autocover
= false, mode_fullinit
= false;
2947 bool flatten
= false, extnets
= false;
2949 Map
parameters(STRING_HASH
);
2951 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2952 if (args
[argidx
] == "-all") {
2956 if (args
[argidx
] == "-gates") {
2960 if (args
[argidx
] == "-flatten") {
2964 if (args
[argidx
] == "-extnets") {
2968 if (args
[argidx
] == "-k") {
2972 if (args
[argidx
] == "-nosva") {
2976 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2977 verific_sva_fsm_limit
= atoi(args
[++argidx
].c_str());
2980 if (args
[argidx
] == "-n") {
2984 if (args
[argidx
] == "-autocover") {
2985 mode_autocover
= true;
2988 if (args
[argidx
] == "-fullinit") {
2989 mode_fullinit
= true;
2992 if (args
[argidx
] == "-chparam" && argidx
+2 < GetSize(args
)) {
2993 const std::string
&key
= args
[++argidx
];
2994 const std::string
&value
= args
[++argidx
];
2995 unsigned new_insertion
= parameters
.Insert(key
.c_str(), value
.c_str(),
2996 1 /* force_overwrite */);
2998 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key
.c_str());
3001 if (args
[argidx
] == "-V") {
3002 mode_verific
= true;
3005 if (args
[argidx
] == "-v") {
3006 verific_verbose
= 1;
3009 if (args
[argidx
] == "-vv") {
3010 verific_verbose
= 2;
3013 if (args
[argidx
] == "-d" && argidx
+1 < GetSize(args
)) {
3014 dumpfile
= args
[++argidx
];
3020 if (argidx
> GetSize(args
) && args
[argidx
].compare(0, 1, "-") == 0)
3021 cmd_error(args
, argidx
, "unknown option");
3023 std::set
<std::string
> top_mod_names
;
3025 #ifdef YOSYSHQ_VERIFIC_EXTENSIONS
3026 InitialAssertions::Rewrite(work
, ¶meters
);
3030 log("Running hier_tree::ElaborateAll().\n");
3032 VeriLibrary
*veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
3034 Array veri_libs
, vhdl_libs
;
3035 #ifdef VERIFIC_VHDL_SUPPORT
3036 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
3037 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
3039 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
3041 Array
*netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, ¶meters
);
3045 FOREACH_ARRAY_ITEM(netlists
, i
, nl
)
3051 if (argidx
== GetSize(args
))
3052 cmd_error(args
, argidx
, "No top module specified.\n");
3054 VeriLibrary
* veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
3055 #ifdef VERIFIC_VHDL_SUPPORT
3056 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
3059 Array veri_modules
, vhdl_units
;
3060 for (; argidx
< GetSize(args
); argidx
++)
3062 const char *name
= args
[argidx
].c_str();
3063 top_mod_names
.insert(name
);
3065 VeriModule
*veri_module
= veri_lib
? veri_lib
->GetModule(name
, 1) : nullptr;
3067 log("Adding Verilog module '%s' to elaboration queue.\n", name
);
3068 veri_modules
.InsertLast(veri_module
);
3071 #ifdef VERIFIC_VHDL_SUPPORT
3072 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
? vhdl_lib
->GetPrimUnit(name
) : nullptr;
3074 log("Adding VHDL unit '%s' to elaboration queue.\n", name
);
3075 vhdl_units
.InsertLast(vhdl_unit
);
3079 log_error("Can't find module/unit '%s'.\n", name
);
3083 // Also elaborate all root modules since they may contain bind statements
3085 VeriModule
*veri_module
;
3086 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
3087 if (!veri_module
->IsRootModule()) continue;
3088 veri_modules
.InsertLast(veri_module
);
3092 log("Running hier_tree::Elaborate().\n");
3093 Array
*netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, ¶meters
);
3097 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
3098 nl
->AddAtt(new Att(" \\top", NULL
));
3104 if (!verific_error_msg
.empty())
3108 for (auto nl
: nl_todo
)
3113 VerificExtNets worker
;
3114 for (auto nl
: nl_todo
)
3118 for (auto nl
: nl_todo
)
3119 nl
->ChangePortBusStructures(1 /* hierarchical */);
3121 if (!dumpfile
.empty()) {
3122 VeriWrite veri_writer
;
3123 veri_writer
.WriteFile(dumpfile
.c_str(), Netlist::PresentDesign());
3126 while (!nl_todo
.empty()) {
3127 Netlist
*nl
= *nl_todo
.begin();
3128 if (nl_done
.count(nl
) == 0) {
3129 VerificImporter
importer(mode_gates
, mode_keep
, mode_nosva
,
3130 mode_names
, mode_verific
, mode_autocover
, mode_fullinit
);
3131 importer
.import_netlist(design
, nl
, nl_todo
, top_mod_names
.count(nl
->Owner()->Name()));
3138 #ifdef VERIFIC_VHDL_SUPPORT
3142 verific_incdirs
.clear();
3143 verific_libdirs
.clear();
3144 verific_import_pending
= false;
3148 cmd_error(args
, argidx
, "Missing or unsupported mode parameter.\n");
3151 if (!verific_error_msg
.empty())
3152 log_error("%s\n", verific_error_msg
.c_str());
3155 #else /* YOSYS_ENABLE_VERIFIC */
3156 void execute(std::vector
<std::string
>, RTLIL::Design
*) override
{
3157 log_cmd_error("This version of Yosys is built without Verific support.\n"
3159 "Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.\n"
3160 "https://www.yosyshq.com/\n"
3162 "Contact office@yosyshq.com for free evaluation\n"
3163 "binaries of YosysHQ Tabby CAD Suite.\n");
3168 struct ReadPass
: public Pass
{
3169 ReadPass() : Pass("read", "load HDL designs") { }
3170 void help() override
3172 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
3174 log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
3176 log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
3177 log("is only available via Verific.)\n");
3179 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
3180 log("the language version (and before file names) to set additional verilog defines.\n");
3183 #ifdef VERIFIC_VHDL_SUPPORT
3184 log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
3186 log("Load the specified VHDL files. (Requires Verific.)\n");
3190 log(" read {-f|-F} <command-file>\n");
3192 log("Load and execute the specified command file. (Requires Verific.)\n");
3193 log("Check verific command for more information about supported commands in file.\n");
3196 log(" read -define <macro>[=<value>]..\n");
3198 log("Set global Verilog/SystemVerilog defines.\n");
3201 log(" read -undef <macro>..\n");
3203 log("Unset global Verilog/SystemVerilog defines.\n");
3206 log(" read -incdir <directory>\n");
3208 log("Add directory to global Verilog/SystemVerilog include directories.\n");
3211 log(" read -verific\n");
3212 log(" read -noverific\n");
3214 log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
3215 log("with -verific will result in an error on Yosys binaries that are built without\n");
3216 log("Verific support. The default is to use Verific if it is available.\n");
3219 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
3221 #ifdef YOSYS_ENABLE_VERIFIC
3222 static bool verific_available
= !check_noverific_env();
3224 static bool verific_available
= false;
3226 static bool use_verific
= verific_available
;
3228 if (args
.size() < 2 || args
[1][0] != '-')
3229 cmd_error(args
, 1, "Missing mode parameter.\n");
3231 if (args
[1] == "-verific" || args
[1] == "-noverific") {
3232 if (args
.size() != 2)
3233 cmd_error(args
, 1, "Additional arguments to -verific/-noverific.\n");
3234 if (args
[1] == "-verific") {
3235 if (!verific_available
)
3236 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
3239 use_verific
= false;
3244 if (args
.size() < 3)
3245 cmd_error(args
, 3, "Missing file name parameter.\n");
3247 if (args
[1] == "-vlog95" || args
[1] == "-vlog2k") {
3249 args
[0] = "verific";
3251 args
[0] = "read_verilog";
3254 Pass::call(design
, args
);
3258 if (args
[1] == "-sv2005" || args
[1] == "-sv2009" || args
[1] == "-sv2012" || args
[1] == "-sv" || args
[1] == "-formal") {
3260 args
[0] = "verific";
3262 args
[0] = "read_verilog";
3263 if (args
[1] == "-formal")
3264 args
.insert(args
.begin()+1, std::string());
3266 args
.insert(args
.begin()+1, "-defer");
3268 Pass::call(design
, args
);
3272 #ifdef VERIFIC_VHDL_SUPPORT
3273 if (args
[1] == "-vhdl87" || args
[1] == "-vhdl93" || args
[1] == "-vhdl2k" || args
[1] == "-vhdl2008" || args
[1] == "-vhdl") {
3275 args
[0] = "verific";
3276 Pass::call(design
, args
);
3278 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
3283 if (args
[1] == "-f" || args
[1] == "-F") {
3285 args
[0] = "verific";
3286 Pass::call(design
, args
);
3288 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
3293 if (args
[1] == "-define") {
3295 args
[0] = "verific";
3296 args
[1] = "-vlog-define";
3297 Pass::call(design
, args
);
3299 args
[0] = "verilog_defines";
3300 args
.erase(args
.begin()+1, args
.begin()+2);
3301 for (int i
= 1; i
< GetSize(args
); i
++)
3302 args
[i
] = "-D" + args
[i
];
3303 Pass::call(design
, args
);
3307 if (args
[1] == "-undef") {
3309 args
[0] = "verific";
3310 args
[1] = "-vlog-undef";
3311 Pass::call(design
, args
);
3313 args
[0] = "verilog_defines";
3314 args
.erase(args
.begin()+1, args
.begin()+2);
3315 for (int i
= 1; i
< GetSize(args
); i
++)
3316 args
[i
] = "-U" + args
[i
];
3317 Pass::call(design
, args
);
3321 if (args
[1] == "-incdir") {
3323 args
[0] = "verific";
3324 args
[1] = "-vlog-incdir";
3325 Pass::call(design
, args
);
3327 args
[0] = "verilog_defaults";
3329 for (int i
= 2; i
< GetSize(args
); i
++)
3330 args
[i
] = "-I" + args
[i
];
3331 Pass::call(design
, args
);
3335 cmd_error(args
, 1, "Missing or unsupported mode parameter.\n");
3339 PRIVATE_NAMESPACE_END