2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/log.h"
32 #include "frontends/verific/verific.h"
36 #ifdef YOSYS_ENABLE_VERIFIC
39 #pragma clang diagnostic push
40 #pragma clang diagnostic ignored "-Woverloaded-virtual"
43 #include "veri_file.h"
44 #include "vhdl_file.h"
45 #include "hier_tree.h"
46 #include "VeriModule.h"
47 #include "VeriWrite.h"
48 #include "VhdlUnits.h"
52 #pragma clang diagnostic pop
55 #ifdef VERIFIC_NAMESPACE
56 using namespace Verific
;
61 #ifdef YOSYS_ENABLE_VERIFIC
65 bool verific_import_pending
;
66 string verific_error_msg
;
67 int verific_sva_fsm_limit
;
69 vector
<string
> verific_incdirs
, verific_libdirs
;
71 void msg_func(msg_type_t msg_type
, const char *message_id
, linefile_type linefile
, const char *msg
, va_list args
)
73 string message_prefix
= stringf("VERIFIC-%s [%s] ",
74 msg_type
== VERIFIC_NONE
? "NONE" :
75 msg_type
== VERIFIC_ERROR
? "ERROR" :
76 msg_type
== VERIFIC_WARNING
? "WARNING" :
77 msg_type
== VERIFIC_IGNORE
? "IGNORE" :
78 msg_type
== VERIFIC_INFO
? "INFO" :
79 msg_type
== VERIFIC_COMMENT
? "COMMENT" :
80 msg_type
== VERIFIC_PROGRAM_ERROR
? "PROGRAM_ERROR" : "UNKNOWN", message_id
);
82 string message
= linefile
? stringf("%s:%d: ", LineFile::GetFileName(linefile
), LineFile::GetLineNo(linefile
)) : "";
83 message
+= vstringf(msg
, args
);
85 if (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_WARNING
|| msg_type
== VERIFIC_PROGRAM_ERROR
)
86 log_warning_noprefix("%s%s\n", message_prefix
.c_str(), message
.c_str());
88 log("%s%s\n", message_prefix
.c_str(), message
.c_str());
90 if (verific_error_msg
.empty() && (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_PROGRAM_ERROR
))
91 verific_error_msg
= message
;
94 string
get_full_netlist_name(Netlist
*nl
)
96 if (nl
->NumOfRefs() == 1) {
97 Instance
*inst
= (Instance
*)nl
->GetReferences()->GetLast();
98 return get_full_netlist_name(inst
->Owner()) + "." + inst
->Name();
101 return nl
->CellBaseName();
104 // ==================================================================
106 VerificImporter::VerificImporter(bool mode_gates
, bool mode_keep
, bool mode_nosva
, bool mode_names
, bool mode_verific
, bool mode_autocover
) :
107 mode_gates(mode_gates
), mode_keep(mode_keep
), mode_nosva(mode_nosva
),
108 mode_names(mode_names
), mode_verific(mode_verific
), mode_autocover(mode_autocover
)
112 RTLIL::SigBit
VerificImporter::net_map_at(Net
*net
)
114 if (net
->IsExternalTo(netlist
))
115 log_error("Found external reference to '%s.%s' in netlist '%s', please use -flatten or -extnets.\n",
116 get_full_netlist_name(net
->Owner()).c_str(), net
->Name(), get_full_netlist_name(netlist
).c_str());
118 return net_map
.at(net
);
121 bool is_blackbox(Netlist
*nl
)
123 if (nl
->IsBlackBox())
126 const char *attr
= nl
->GetAttValue("blackbox");
127 if (attr
!= nullptr && strcmp(attr
, "0"))
133 RTLIL::IdString
VerificImporter::new_verific_id(Verific::DesignObj
*obj
)
135 std::string s
= stringf("$verific$%s", obj
->Name());
137 s
+= stringf("$%s:%d", Verific::LineFile::GetFileName(obj
->Linefile()), Verific::LineFile::GetLineNo(obj
->Linefile()));
138 s
+= stringf("$%d", autoidx
++);
142 void VerificImporter::import_attributes(dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, DesignObj
*obj
)
148 attributes
["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj
->Linefile()), LineFile::GetLineNo(obj
->Linefile()));
150 // FIXME: Parse numeric attributes
151 FOREACH_ATTRIBUTE(obj
, mi
, attr
) {
152 if (attr
->Key()[0] == ' ' || attr
->Value() == nullptr)
154 attributes
[RTLIL::escape_id(attr
->Key())] = RTLIL::Const(std::string(attr
->Value()));
158 RTLIL::SigSpec
VerificImporter::operatorInput(Instance
*inst
)
161 for (int i
= int(inst
->InputSize())-1; i
>= 0; i
--)
162 if (inst
->GetInputBit(i
))
163 sig
.append(net_map_at(inst
->GetInputBit(i
)));
165 sig
.append(RTLIL::State::Sz
);
169 RTLIL::SigSpec
VerificImporter::operatorInput1(Instance
*inst
)
172 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--)
173 if (inst
->GetInput1Bit(i
))
174 sig
.append(net_map_at(inst
->GetInput1Bit(i
)));
176 sig
.append(RTLIL::State::Sz
);
180 RTLIL::SigSpec
VerificImporter::operatorInput2(Instance
*inst
)
183 for (int i
= int(inst
->Input2Size())-1; i
>= 0; i
--)
184 if (inst
->GetInput2Bit(i
))
185 sig
.append(net_map_at(inst
->GetInput2Bit(i
)));
187 sig
.append(RTLIL::State::Sz
);
191 RTLIL::SigSpec
VerificImporter::operatorInport(Instance
*inst
, const char *portname
)
193 PortBus
*portbus
= inst
->View()->GetPortBus(portname
);
196 for (unsigned i
= 0; i
< portbus
->Size(); i
++) {
197 Net
*net
= inst
->GetNet(portbus
->ElementAtIndex(i
));
200 sig
.append(RTLIL::State::S0
);
201 else if (net
->IsPwr())
202 sig
.append(RTLIL::State::S1
);
204 sig
.append(net_map_at(net
));
206 sig
.append(RTLIL::State::Sz
);
210 Port
*port
= inst
->View()->GetPort(portname
);
211 log_assert(port
!= NULL
);
212 Net
*net
= inst
->GetNet(port
);
213 return net_map_at(net
);
217 RTLIL::SigSpec
VerificImporter::operatorOutput(Instance
*inst
, const pool
<Net
*, hash_ptr_ops
> *any_all_nets
)
220 RTLIL::Wire
*dummy_wire
= NULL
;
221 for (int i
= int(inst
->OutputSize())-1; i
>= 0; i
--)
222 if (inst
->GetOutputBit(i
) && (!any_all_nets
|| !any_all_nets
->count(inst
->GetOutputBit(i
)))) {
223 sig
.append(net_map_at(inst
->GetOutputBit(i
)));
226 if (dummy_wire
== NULL
)
227 dummy_wire
= module
->addWire(new_verific_id(inst
));
230 sig
.append(RTLIL::SigSpec(dummy_wire
, dummy_wire
->width
- 1));
235 bool VerificImporter::import_netlist_instance_gates(Instance
*inst
, RTLIL::IdString inst_name
)
237 if (inst
->Type() == PRIM_AND
) {
238 module
->addAndGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
242 if (inst
->Type() == PRIM_NAND
) {
243 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
244 module
->addAndGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
245 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
249 if (inst
->Type() == PRIM_OR
) {
250 module
->addOrGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
254 if (inst
->Type() == PRIM_NOR
) {
255 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
256 module
->addOrGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
257 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
261 if (inst
->Type() == PRIM_XOR
) {
262 module
->addXorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
266 if (inst
->Type() == PRIM_XNOR
) {
267 module
->addXnorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
271 if (inst
->Type() == PRIM_BUF
) {
272 auto outnet
= inst
->GetOutput();
273 if (!any_all_nets
.count(outnet
))
274 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
278 if (inst
->Type() == PRIM_INV
) {
279 module
->addNotGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
283 if (inst
->Type() == PRIM_MUX
) {
284 module
->addMuxGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
288 if (inst
->Type() == PRIM_TRI
) {
289 module
->addMuxGate(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
293 if (inst
->Type() == PRIM_FADD
)
295 RTLIL::SigSpec a
= net_map_at(inst
->GetInput1()), b
= net_map_at(inst
->GetInput2()), c
= net_map_at(inst
->GetCin());
296 RTLIL::SigSpec x
= inst
->GetCout() ? net_map_at(inst
->GetCout()) : module
->addWire(new_verific_id(inst
));
297 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
298 RTLIL::SigSpec tmp1
= module
->addWire(new_verific_id(inst
));
299 RTLIL::SigSpec tmp2
= module
->addWire(new_verific_id(inst
));
300 RTLIL::SigSpec tmp3
= module
->addWire(new_verific_id(inst
));
301 module
->addXorGate(new_verific_id(inst
), a
, b
, tmp1
);
302 module
->addXorGate(inst_name
, tmp1
, c
, y
);
303 module
->addAndGate(new_verific_id(inst
), tmp1
, c
, tmp2
);
304 module
->addAndGate(new_verific_id(inst
), a
, b
, tmp3
);
305 module
->addOrGate(new_verific_id(inst
), tmp2
, tmp3
, x
);
309 if (inst
->Type() == PRIM_DFFRS
)
311 VerificClocking
clocking(this, inst
->GetClock());
312 log_assert(clocking
.disable_sig
== State::S0
);
313 log_assert(clocking
.body_net
== nullptr);
315 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
316 clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
317 else if (inst
->GetSet()->IsGnd())
318 clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S0
);
319 else if (inst
->GetReset()->IsGnd())
320 clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S1
);
322 clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
323 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
330 bool VerificImporter::import_netlist_instance_cells(Instance
*inst
, RTLIL::IdString inst_name
)
332 RTLIL::Cell
*cell
= nullptr;
334 if (inst
->Type() == PRIM_AND
) {
335 cell
= module
->addAnd(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
336 import_attributes(cell
->attributes
, inst
);
340 if (inst
->Type() == PRIM_NAND
) {
341 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
342 cell
= module
->addAnd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
343 import_attributes(cell
->attributes
, inst
);
344 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
345 import_attributes(cell
->attributes
, inst
);
349 if (inst
->Type() == PRIM_OR
) {
350 cell
= module
->addOr(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
351 import_attributes(cell
->attributes
, inst
);
355 if (inst
->Type() == PRIM_NOR
) {
356 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
357 cell
= module
->addOr(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
358 import_attributes(cell
->attributes
, inst
);
359 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
360 import_attributes(cell
->attributes
, inst
);
364 if (inst
->Type() == PRIM_XOR
) {
365 cell
= module
->addXor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
366 import_attributes(cell
->attributes
, inst
);
370 if (inst
->Type() == PRIM_XNOR
) {
371 cell
= module
->addXnor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
372 import_attributes(cell
->attributes
, inst
);
376 if (inst
->Type() == PRIM_INV
) {
377 cell
= module
->addNot(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
378 import_attributes(cell
->attributes
, inst
);
382 if (inst
->Type() == PRIM_MUX
) {
383 cell
= module
->addMux(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
384 import_attributes(cell
->attributes
, inst
);
388 if (inst
->Type() == PRIM_TRI
) {
389 cell
= module
->addMux(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
390 import_attributes(cell
->attributes
, inst
);
394 if (inst
->Type() == PRIM_FADD
)
396 RTLIL::SigSpec a_plus_b
= module
->addWire(new_verific_id(inst
), 2);
397 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
399 y
.append(net_map_at(inst
->GetCout()));
400 cell
= module
->addAdd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), a_plus_b
);
401 import_attributes(cell
->attributes
, inst
);
402 cell
= module
->addAdd(inst_name
, a_plus_b
, net_map_at(inst
->GetCin()), y
);
403 import_attributes(cell
->attributes
, inst
);
407 if (inst
->Type() == PRIM_DFFRS
)
409 VerificClocking
clocking(this, inst
->GetClock());
410 log_assert(clocking
.disable_sig
== State::S0
);
411 log_assert(clocking
.body_net
== nullptr);
413 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
414 cell
= clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
415 else if (inst
->GetSet()->IsGnd())
416 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
417 else if (inst
->GetReset()->IsGnd())
418 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
420 cell
= clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
421 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
422 import_attributes(cell
->attributes
, inst
);
426 if (inst
->Type() == PRIM_DLATCHRS
)
428 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
429 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
431 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
432 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
433 import_attributes(cell
->attributes
, inst
);
437 #define IN operatorInput(inst)
438 #define IN1 operatorInput1(inst)
439 #define IN2 operatorInput2(inst)
440 #define OUT operatorOutput(inst)
441 #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
442 #define SIGNED inst->View()->IsSigned()
444 if (inst
->Type() == OPER_ADDER
) {
445 RTLIL::SigSpec out
= OUT
;
446 if (inst
->GetCout() != NULL
)
447 out
.append(net_map_at(inst
->GetCout()));
448 if (inst
->GetCin()->IsGnd()) {
449 cell
= module
->addAdd(inst_name
, IN1
, IN2
, out
, SIGNED
);
450 import_attributes(cell
->attributes
, inst
);
452 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
), GetSize(out
));
453 cell
= module
->addAdd(new_verific_id(inst
), IN1
, IN2
, tmp
, SIGNED
);
454 import_attributes(cell
->attributes
, inst
);
455 cell
= module
->addAdd(inst_name
, tmp
, net_map_at(inst
->GetCin()), out
, false);
456 import_attributes(cell
->attributes
, inst
);
461 if (inst
->Type() == OPER_MULTIPLIER
) {
462 cell
= module
->addMul(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
463 import_attributes(cell
->attributes
, inst
);
467 if (inst
->Type() == OPER_DIVIDER
) {
468 cell
= module
->addDiv(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
469 import_attributes(cell
->attributes
, inst
);
473 if (inst
->Type() == OPER_MODULO
) {
474 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
475 import_attributes(cell
->attributes
, inst
);
479 if (inst
->Type() == OPER_REMAINDER
) {
480 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
481 import_attributes(cell
->attributes
, inst
);
485 if (inst
->Type() == OPER_SHIFT_LEFT
) {
486 cell
= module
->addShl(inst_name
, IN1
, IN2
, OUT
, false);
487 import_attributes(cell
->attributes
, inst
);
491 if (inst
->Type() == OPER_ENABLED_DECODER
) {
493 vec
.append(net_map_at(inst
->GetControl()));
494 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
495 vec
.append(RTLIL::State::S0
);
497 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
498 import_attributes(cell
->attributes
, inst
);
502 if (inst
->Type() == OPER_DECODER
) {
504 vec
.append(RTLIL::State::S1
);
505 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
506 vec
.append(RTLIL::State::S0
);
508 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
509 import_attributes(cell
->attributes
, inst
);
513 if (inst
->Type() == OPER_SHIFT_RIGHT
) {
514 Net
*net_cin
= inst
->GetCin();
515 Net
*net_a_msb
= inst
->GetInput1Bit(0);
516 if (net_cin
->IsGnd())
517 cell
= module
->addShr(inst_name
, IN1
, IN2
, OUT
, false);
518 else if (net_cin
== net_a_msb
)
519 cell
= module
->addSshr(inst_name
, IN1
, IN2
, OUT
, true);
521 log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst
->Name());
522 import_attributes(cell
->attributes
, inst
);
526 if (inst
->Type() == OPER_REDUCE_AND
) {
527 cell
= module
->addReduceAnd(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
528 import_attributes(cell
->attributes
, inst
);
532 if (inst
->Type() == OPER_REDUCE_OR
) {
533 cell
= module
->addReduceOr(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
534 import_attributes(cell
->attributes
, inst
);
538 if (inst
->Type() == OPER_REDUCE_XOR
) {
539 cell
= module
->addReduceXor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
540 import_attributes(cell
->attributes
, inst
);
544 if (inst
->Type() == OPER_REDUCE_XNOR
) {
545 cell
= module
->addReduceXnor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
546 import_attributes(cell
->attributes
, inst
);
550 if (inst
->Type() == OPER_REDUCE_NOR
) {
551 SigSpec t
= module
->ReduceOr(new_verific_id(inst
), IN
, SIGNED
);
552 cell
= module
->addNot(inst_name
, t
, net_map_at(inst
->GetOutput()));
553 import_attributes(cell
->attributes
, inst
);
557 if (inst
->Type() == OPER_LESSTHAN
) {
558 Net
*net_cin
= inst
->GetCin();
559 if (net_cin
->IsGnd())
560 cell
= module
->addLt(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
561 else if (net_cin
->IsPwr())
562 cell
= module
->addLe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
564 log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst
->Name());
565 import_attributes(cell
->attributes
, inst
);
569 if (inst
->Type() == OPER_WIDE_AND
) {
570 cell
= module
->addAnd(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
571 import_attributes(cell
->attributes
, inst
);
575 if (inst
->Type() == OPER_WIDE_OR
) {
576 cell
= module
->addOr(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
577 import_attributes(cell
->attributes
, inst
);
581 if (inst
->Type() == OPER_WIDE_XOR
) {
582 cell
= module
->addXor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
583 import_attributes(cell
->attributes
, inst
);
587 if (inst
->Type() == OPER_WIDE_XNOR
) {
588 cell
= module
->addXnor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
589 import_attributes(cell
->attributes
, inst
);
593 if (inst
->Type() == OPER_WIDE_BUF
) {
594 cell
= module
->addPos(inst_name
, IN
, FILTERED_OUT
, SIGNED
);
595 import_attributes(cell
->attributes
, inst
);
599 if (inst
->Type() == OPER_WIDE_INV
) {
600 cell
= module
->addNot(inst_name
, IN
, OUT
, SIGNED
);
601 import_attributes(cell
->attributes
, inst
);
605 if (inst
->Type() == OPER_MINUS
) {
606 cell
= module
->addSub(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
607 import_attributes(cell
->attributes
, inst
);
611 if (inst
->Type() == OPER_UMINUS
) {
612 cell
= module
->addNeg(inst_name
, IN
, OUT
, SIGNED
);
613 import_attributes(cell
->attributes
, inst
);
617 if (inst
->Type() == OPER_EQUAL
) {
618 cell
= module
->addEq(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
619 import_attributes(cell
->attributes
, inst
);
623 if (inst
->Type() == OPER_NEQUAL
) {
624 cell
= module
->addNe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
625 import_attributes(cell
->attributes
, inst
);
629 if (inst
->Type() == OPER_WIDE_MUX
) {
630 cell
= module
->addMux(inst_name
, IN1
, IN2
, net_map_at(inst
->GetControl()), OUT
);
631 import_attributes(cell
->attributes
, inst
);
635 if (inst
->Type() == OPER_NTO1MUX
) {
636 cell
= module
->addShr(inst_name
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
637 import_attributes(cell
->attributes
, inst
);
641 if (inst
->Type() == OPER_WIDE_NTO1MUX
)
643 SigSpec data
= IN2
, out
= OUT
;
645 int wordsize_bits
= ceil_log2(GetSize(out
));
646 int wordsize
= 1 << wordsize_bits
;
648 SigSpec sel
= {IN1
, SigSpec(State::S0
, wordsize_bits
)};
651 for (int i
= 0; i
< GetSize(data
); i
+= GetSize(out
)) {
652 SigSpec d
= data
.extract(i
, GetSize(out
));
653 d
.extend_u0(wordsize
);
654 padded_data
.append(d
);
657 cell
= module
->addShr(inst_name
, padded_data
, sel
, out
);
658 import_attributes(cell
->attributes
, inst
);
662 if (inst
->Type() == OPER_SELECTOR
)
664 cell
= module
->addPmux(inst_name
, State::S0
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
665 import_attributes(cell
->attributes
, inst
);
669 if (inst
->Type() == OPER_WIDE_SELECTOR
)
672 cell
= module
->addPmux(inst_name
, SigSpec(State::S0
, GetSize(out
)), IN2
, IN1
, out
);
673 import_attributes(cell
->attributes
, inst
);
677 if (inst
->Type() == OPER_WIDE_TRI
) {
678 cell
= module
->addMux(inst_name
, RTLIL::SigSpec(RTLIL::State::Sz
, inst
->OutputSize()), IN
, net_map_at(inst
->GetControl()), OUT
);
679 import_attributes(cell
->attributes
, inst
);
683 if (inst
->Type() == OPER_WIDE_DFFRS
)
685 VerificClocking
clocking(this, inst
->GetClock());
686 log_assert(clocking
.disable_sig
== State::S0
);
687 log_assert(clocking
.body_net
== nullptr);
689 RTLIL::SigSpec sig_set
= operatorInport(inst
, "set");
690 RTLIL::SigSpec sig_reset
= operatorInport(inst
, "reset");
692 if (sig_set
.is_fully_const() && !sig_set
.as_bool() && sig_reset
.is_fully_const() && !sig_reset
.as_bool())
693 cell
= clocking
.addDff(inst_name
, IN
, OUT
);
695 cell
= clocking
.addDffsr(inst_name
, sig_set
, sig_reset
, IN
, OUT
);
696 import_attributes(cell
->attributes
, inst
);
710 void VerificImporter::merge_past_ffs_clock(pool
<RTLIL::Cell
*> &candidates
, SigBit clock
, bool clock_pol
)
712 bool keep_running
= true;
717 keep_running
= false;
719 dict
<SigBit
, pool
<RTLIL::Cell
*>> dbits_db
;
722 for (auto cell
: candidates
) {
723 SigBit bit
= sigmap(cell
->getPort("\\D"));
724 dbits_db
[bit
].insert(cell
);
728 dbits
.sort_and_unify();
730 for (auto chunk
: dbits
.chunks())
732 SigSpec sig_d
= chunk
;
734 if (chunk
.wire
== nullptr || GetSize(sig_d
) == 1)
737 SigSpec sig_q
= module
->addWire(NEW_ID
, GetSize(sig_d
));
738 RTLIL::Cell
*new_ff
= module
->addDff(NEW_ID
, clock
, sig_d
, sig_q
, clock_pol
);
741 log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d
), log_id(new_ff
));
743 for (int i
= 0; i
< GetSize(sig_d
); i
++)
744 for (auto old_ff
: dbits_db
[sig_d
[i
]])
747 log(" replacing old ff %s on bit %d.\n", log_id(old_ff
), i
);
749 SigBit old_q
= old_ff
->getPort("\\Q");
750 SigBit new_q
= sig_q
[i
];
752 sigmap
.add(old_q
, new_q
);
753 module
->connect(old_q
, new_q
);
754 candidates
.erase(old_ff
);
755 module
->remove(old_ff
);
762 void VerificImporter::merge_past_ffs(pool
<RTLIL::Cell
*> &candidates
)
764 dict
<pair
<SigBit
, int>, pool
<RTLIL::Cell
*>> database
;
766 for (auto cell
: candidates
)
768 SigBit clock
= cell
->getPort("\\CLK");
769 bool clock_pol
= cell
->getParam("\\CLK_POLARITY").as_bool();
770 database
[make_pair(clock
, int(clock_pol
))].insert(cell
);
773 for (auto it
: database
)
774 merge_past_ffs_clock(it
.second
, it
.first
.first
, it
.first
.second
);
777 void VerificImporter::import_netlist(RTLIL::Design
*design
, Netlist
*nl
, std::set
<Netlist
*> &nl_todo
)
779 std::string module_name
= nl
->IsOperator() ? std::string("$verific$") + nl
->Owner()->Name() : RTLIL::escape_id(nl
->Owner()->Name());
783 if (design
->has(module_name
)) {
784 if (!nl
->IsOperator() && !is_blackbox(nl
))
785 log_cmd_error("Re-definition of module `%s'.\n", nl
->Owner()->Name());
789 module
= new RTLIL::Module
;
790 module
->name
= module_name
;
793 if (is_blackbox(nl
)) {
794 log("Importing blackbox module %s.\n", RTLIL::id2cstr(module
->name
));
795 module
->set_bool_attribute("\\blackbox");
797 log("Importing module %s.\n", RTLIL::id2cstr(module
->name
));
809 FOREACH_PORT_OF_NETLIST(nl
, mi
, port
)
815 log(" importing port %s.\n", port
->Name());
817 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(port
->Name()));
818 import_attributes(wire
->attributes
, port
);
820 wire
->port_id
= nl
->IndexOf(port
) + 1;
822 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_IN
)
823 wire
->port_input
= true;
824 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_OUT
)
825 wire
->port_output
= true;
827 if (port
->GetNet()) {
828 net
= port
->GetNet();
829 if (net_map
.count(net
) == 0)
831 else if (wire
->port_input
)
832 module
->connect(net_map_at(net
), wire
);
834 module
->connect(wire
, net_map_at(net
));
838 FOREACH_PORTBUS_OF_NETLIST(nl
, mi
, portbus
)
841 log(" importing portbus %s.\n", portbus
->Name());
843 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(portbus
->Name()), portbus
->Size());
844 wire
->start_offset
= min(portbus
->LeftIndex(), portbus
->RightIndex());
845 import_attributes(wire
->attributes
, portbus
);
847 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_IN
)
848 wire
->port_input
= true;
849 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_OUT
)
850 wire
->port_output
= true;
852 for (int i
= portbus
->LeftIndex();; i
+= portbus
->IsUp() ? +1 : -1) {
853 if (portbus
->ElementAtIndex(i
) && portbus
->ElementAtIndex(i
)->GetNet()) {
854 net
= portbus
->ElementAtIndex(i
)->GetNet();
855 RTLIL::SigBit
bit(wire
, i
- wire
->start_offset
);
856 if (net_map
.count(net
) == 0)
858 else if (wire
->port_input
)
859 module
->connect(net_map_at(net
), bit
);
861 module
->connect(bit
, net_map_at(net
));
863 if (i
== portbus
->RightIndex())
868 module
->fixup_ports();
870 dict
<Net
*, char, hash_ptr_ops
> init_nets
;
871 pool
<Net
*, hash_ptr_ops
> anyconst_nets
, anyseq_nets
;
872 pool
<Net
*, hash_ptr_ops
> allconst_nets
, allseq_nets
;
873 any_all_nets
.clear();
875 FOREACH_NET_OF_NETLIST(nl
, mi
, net
)
879 RTLIL::Memory
*memory
= new RTLIL::Memory
;
880 memory
->name
= RTLIL::escape_id(net
->Name());
881 log_assert(module
->count_id(memory
->name
) == 0);
882 module
->memories
[memory
->name
] = memory
;
884 int number_of_bits
= net
->Size();
885 int bits_in_word
= number_of_bits
;
886 FOREACH_PORTREF_OF_NET(net
, si
, pr
) {
887 if (pr
->GetInst()->Type() == OPER_READ_PORT
) {
888 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->OutputSize());
891 if (pr
->GetInst()->Type() == OPER_WRITE_PORT
|| pr
->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT
) {
892 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->Input2Size());
895 log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
896 net
->Name(), pr
->GetInst()->View()->Owner()->Name(), pr
->GetInst()->Name());
899 memory
->width
= bits_in_word
;
900 memory
->size
= number_of_bits
/ bits_in_word
;
902 const char *ascii_initdata
= net
->GetWideInitialValue();
903 if (ascii_initdata
) {
904 while (*ascii_initdata
!= 0 && *ascii_initdata
!= '\'')
906 if (*ascii_initdata
== '\'')
908 if (*ascii_initdata
!= 0) {
909 log_assert(*ascii_initdata
== 'b');
912 for (int word_idx
= 0; word_idx
< memory
->size
; word_idx
++) {
913 Const initval
= Const(State::Sx
, memory
->width
);
914 bool initval_valid
= false;
915 for (int bit_idx
= memory
->width
-1; bit_idx
>= 0; bit_idx
--) {
916 if (*ascii_initdata
== 0)
918 if (*ascii_initdata
== '0' || *ascii_initdata
== '1') {
919 initval
[bit_idx
] = (*ascii_initdata
== '0') ? State::S0
: State::S1
;
920 initval_valid
= true;
925 RTLIL::Cell
*cell
= module
->addCell(new_verific_id(net
), "$meminit");
926 cell
->parameters
["\\WORDS"] = 1;
927 if (net
->GetOrigTypeRange()->LeftRangeBound() < net
->GetOrigTypeRange()->RightRangeBound())
928 cell
->setPort("\\ADDR", word_idx
);
930 cell
->setPort("\\ADDR", memory
->size
- word_idx
- 1);
931 cell
->setPort("\\DATA", initval
);
932 cell
->parameters
["\\MEMID"] = RTLIL::Const(memory
->name
.str());
933 cell
->parameters
["\\ABITS"] = 32;
934 cell
->parameters
["\\WIDTH"] = memory
->width
;
935 cell
->parameters
["\\PRIORITY"] = RTLIL::Const(autoidx
-1);
942 if (net
->GetInitialValue())
943 init_nets
[net
] = net
->GetInitialValue();
945 const char *rand_const_attr
= net
->GetAttValue(" rand_const");
946 const char *rand_attr
= net
->GetAttValue(" rand");
948 const char *anyconst_attr
= net
->GetAttValue("anyconst");
949 const char *anyseq_attr
= net
->GetAttValue("anyseq");
951 const char *allconst_attr
= net
->GetAttValue("allconst");
952 const char *allseq_attr
= net
->GetAttValue("allseq");
954 if (rand_const_attr
!= nullptr && (!strcmp(rand_const_attr
, "1") || !strcmp(rand_const_attr
, "'1'"))) {
955 anyconst_nets
.insert(net
);
956 any_all_nets
.insert(net
);
958 else if (rand_attr
!= nullptr && (!strcmp(rand_attr
, "1") || !strcmp(rand_attr
, "'1'"))) {
959 anyseq_nets
.insert(net
);
960 any_all_nets
.insert(net
);
962 else if (anyconst_attr
!= nullptr && (!strcmp(anyconst_attr
, "1") || !strcmp(anyconst_attr
, "'1'"))) {
963 anyconst_nets
.insert(net
);
964 any_all_nets
.insert(net
);
966 else if (anyseq_attr
!= nullptr && (!strcmp(anyseq_attr
, "1") || !strcmp(anyseq_attr
, "'1'"))) {
967 anyseq_nets
.insert(net
);
968 any_all_nets
.insert(net
);
970 else if (allconst_attr
!= nullptr && (!strcmp(allconst_attr
, "1") || !strcmp(allconst_attr
, "'1'"))) {
971 allconst_nets
.insert(net
);
972 any_all_nets
.insert(net
);
974 else if (allseq_attr
!= nullptr && (!strcmp(allseq_attr
, "1") || !strcmp(allseq_attr
, "'1'"))) {
975 allseq_nets
.insert(net
);
976 any_all_nets
.insert(net
);
979 if (net_map
.count(net
)) {
981 log(" skipping net %s.\n", net
->Name());
988 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| net
->IsUserDeclared() ? RTLIL::escape_id(net
->Name()) : new_verific_id(net
));
991 log(" importing net %s as %s.\n", net
->Name(), log_id(wire_name
));
993 RTLIL::Wire
*wire
= module
->addWire(wire_name
);
994 import_attributes(wire
->attributes
, net
);
999 FOREACH_NETBUS_OF_NETLIST(nl
, mi
, netbus
)
1001 bool found_new_net
= false;
1002 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1) {
1003 net
= netbus
->ElementAtIndex(i
);
1004 if (net_map
.count(net
) == 0)
1005 found_new_net
= true;
1006 if (i
== netbus
->RightIndex())
1012 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| netbus
->IsUserDeclared() ? RTLIL::escape_id(netbus
->Name()) : new_verific_id(netbus
));
1014 if (verific_verbose
)
1015 log(" importing netbus %s as %s.\n", netbus
->Name(), log_id(wire_name
));
1017 RTLIL::Wire
*wire
= module
->addWire(wire_name
, netbus
->Size());
1018 wire
->start_offset
= min(netbus
->LeftIndex(), netbus
->RightIndex());
1019 import_attributes(wire
->attributes
, netbus
);
1021 RTLIL::Const initval
= Const(State::Sx
, GetSize(wire
));
1022 bool initval_valid
= false;
1024 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1)
1026 if (netbus
->ElementAtIndex(i
))
1028 int bitidx
= i
- wire
->start_offset
;
1029 net
= netbus
->ElementAtIndex(i
);
1030 RTLIL::SigBit
bit(wire
, bitidx
);
1032 if (init_nets
.count(net
)) {
1033 if (init_nets
.at(net
) == '0')
1034 initval
.bits
.at(bitidx
) = State::S0
;
1035 if (init_nets
.at(net
) == '1')
1036 initval
.bits
.at(bitidx
) = State::S1
;
1037 initval_valid
= true;
1038 init_nets
.erase(net
);
1041 if (net_map
.count(net
) == 0)
1044 module
->connect(bit
, net_map_at(net
));
1047 if (i
== netbus
->RightIndex())
1052 wire
->attributes
["\\init"] = initval
;
1056 if (verific_verbose
)
1057 log(" skipping netbus %s.\n", netbus
->Name());
1060 SigSpec anyconst_sig
;
1062 SigSpec allconst_sig
;
1065 for (int i
= netbus
->RightIndex();; i
+= netbus
->IsUp() ? -1 : +1) {
1066 net
= netbus
->ElementAtIndex(i
);
1067 if (net
!= nullptr && anyconst_nets
.count(net
)) {
1068 anyconst_sig
.append(net_map_at(net
));
1069 anyconst_nets
.erase(net
);
1071 if (net
!= nullptr && anyseq_nets
.count(net
)) {
1072 anyseq_sig
.append(net_map_at(net
));
1073 anyseq_nets
.erase(net
);
1075 if (net
!= nullptr && allconst_nets
.count(net
)) {
1076 allconst_sig
.append(net_map_at(net
));
1077 allconst_nets
.erase(net
);
1079 if (net
!= nullptr && allseq_nets
.count(net
)) {
1080 allseq_sig
.append(net_map_at(net
));
1081 allseq_nets
.erase(net
);
1083 if (i
== netbus
->LeftIndex())
1087 if (GetSize(anyconst_sig
))
1088 module
->connect(anyconst_sig
, module
->Anyconst(new_verific_id(netbus
), GetSize(anyconst_sig
)));
1090 if (GetSize(anyseq_sig
))
1091 module
->connect(anyseq_sig
, module
->Anyseq(new_verific_id(netbus
), GetSize(anyseq_sig
)));
1093 if (GetSize(allconst_sig
))
1094 module
->connect(allconst_sig
, module
->Allconst(new_verific_id(netbus
), GetSize(allconst_sig
)));
1096 if (GetSize(allseq_sig
))
1097 module
->connect(allseq_sig
, module
->Allseq(new_verific_id(netbus
), GetSize(allseq_sig
)));
1100 for (auto it
: init_nets
)
1103 SigBit bit
= net_map_at(it
.first
);
1104 log_assert(bit
.wire
);
1106 if (bit
.wire
->attributes
.count("\\init"))
1107 initval
= bit
.wire
->attributes
.at("\\init");
1109 while (GetSize(initval
) < GetSize(bit
.wire
))
1110 initval
.bits
.push_back(State::Sx
);
1112 if (it
.second
== '0')
1113 initval
.bits
.at(bit
.offset
) = State::S0
;
1114 if (it
.second
== '1')
1115 initval
.bits
.at(bit
.offset
) = State::S1
;
1117 bit
.wire
->attributes
["\\init"] = initval
;
1120 for (auto net
: anyconst_nets
)
1121 module
->connect(net_map_at(net
), module
->Anyconst(new_verific_id(net
)));
1123 for (auto net
: anyseq_nets
)
1124 module
->connect(net_map_at(net
), module
->Anyseq(new_verific_id(net
)));
1126 pool
<Instance
*, hash_ptr_ops
> sva_asserts
;
1127 pool
<Instance
*, hash_ptr_ops
> sva_assumes
;
1128 pool
<Instance
*, hash_ptr_ops
> sva_covers
;
1129 pool
<Instance
*, hash_ptr_ops
> sva_triggers
;
1131 pool
<RTLIL::Cell
*> past_ffs
;
1133 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1135 RTLIL::IdString inst_name
= module
->uniquify(mode_names
|| inst
->IsUserDeclared() ? RTLIL::escape_id(inst
->Name()) : new_verific_id(inst
));
1137 if (verific_verbose
)
1138 log(" importing cell %s (%s) as %s.\n", inst
->Name(), inst
->View()->Owner()->Name(), log_id(inst_name
));
1141 goto import_verific_cells
;
1143 if (inst
->Type() == PRIM_PWR
) {
1144 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
1148 if (inst
->Type() == PRIM_GND
) {
1149 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
1153 if (inst
->Type() == PRIM_BUF
) {
1154 auto outnet
= inst
->GetOutput();
1155 if (!any_all_nets
.count(outnet
))
1156 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
1160 if (inst
->Type() == PRIM_X
) {
1161 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sx
);
1165 if (inst
->Type() == PRIM_Z
) {
1166 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sz
);
1170 if (inst
->Type() == OPER_READ_PORT
)
1172 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetInput()->Name()));
1173 int numchunks
= int(inst
->OutputSize()) / memory
->width
;
1174 int chunksbits
= ceil_log2(numchunks
);
1176 if ((numchunks
* memory
->width
) != int(inst
->OutputSize()) || (numchunks
& (numchunks
- 1)) != 0)
1177 log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst
->Name(), inst
->GetInput()->Name());
1179 for (int i
= 0; i
< numchunks
; i
++)
1181 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1182 RTLIL::SigSpec data
= operatorOutput(inst
).extract(i
* memory
->width
, memory
->width
);
1184 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1185 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), "$memrd");
1186 cell
->parameters
["\\MEMID"] = memory
->name
.str();
1187 cell
->parameters
["\\CLK_ENABLE"] = false;
1188 cell
->parameters
["\\CLK_POLARITY"] = true;
1189 cell
->parameters
["\\TRANSPARENT"] = false;
1190 cell
->parameters
["\\ABITS"] = GetSize(addr
);
1191 cell
->parameters
["\\WIDTH"] = GetSize(data
);
1192 cell
->setPort("\\CLK", RTLIL::State::Sx
);
1193 cell
->setPort("\\EN", RTLIL::State::Sx
);
1194 cell
->setPort("\\ADDR", addr
);
1195 cell
->setPort("\\DATA", data
);
1200 if (inst
->Type() == OPER_WRITE_PORT
|| inst
->Type() == OPER_CLOCKED_WRITE_PORT
)
1202 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetOutput()->Name()));
1203 int numchunks
= int(inst
->Input2Size()) / memory
->width
;
1204 int chunksbits
= ceil_log2(numchunks
);
1206 if ((numchunks
* memory
->width
) != int(inst
->Input2Size()) || (numchunks
& (numchunks
- 1)) != 0)
1207 log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst
->Name(), inst
->GetOutput()->Name());
1209 for (int i
= 0; i
< numchunks
; i
++)
1211 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1212 RTLIL::SigSpec data
= operatorInput2(inst
).extract(i
* memory
->width
, memory
->width
);
1214 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1215 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), "$memwr");
1216 cell
->parameters
["\\MEMID"] = memory
->name
.str();
1217 cell
->parameters
["\\CLK_ENABLE"] = false;
1218 cell
->parameters
["\\CLK_POLARITY"] = true;
1219 cell
->parameters
["\\PRIORITY"] = 0;
1220 cell
->parameters
["\\ABITS"] = GetSize(addr
);
1221 cell
->parameters
["\\WIDTH"] = GetSize(data
);
1222 cell
->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst
->GetControl())).repeat(GetSize(data
)));
1223 cell
->setPort("\\CLK", RTLIL::State::S0
);
1224 cell
->setPort("\\ADDR", addr
);
1225 cell
->setPort("\\DATA", data
);
1227 if (inst
->Type() == OPER_CLOCKED_WRITE_PORT
) {
1228 cell
->parameters
["\\CLK_ENABLE"] = true;
1229 cell
->setPort("\\CLK", net_map_at(inst
->GetClock()));
1236 if (import_netlist_instance_cells(inst
, inst_name
))
1238 if (inst
->IsOperator() && !verific_sva_prims
.count(inst
->Type()))
1239 log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst
->View()->Owner()->Name());
1241 if (import_netlist_instance_gates(inst
, inst_name
))
1245 if (inst
->Type() == PRIM_SVA_ASSERT
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSERT
)
1246 sva_asserts
.insert(inst
);
1248 if (inst
->Type() == PRIM_SVA_ASSUME
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSUME
)
1249 sva_assumes
.insert(inst
);
1251 if (inst
->Type() == PRIM_SVA_COVER
|| inst
->Type() == PRIM_SVA_IMMEDIATE_COVER
)
1252 sva_covers
.insert(inst
);
1254 if (inst
->Type() == PRIM_SVA_TRIGGERED
)
1255 sva_triggers
.insert(inst
);
1257 if (inst
->Type() == OPER_SVA_STABLE
)
1259 VerificClocking
clocking(this, inst
->GetInput2Bit(0));
1260 log_assert(clocking
.disable_sig
== State::S0
);
1261 log_assert(clocking
.body_net
== nullptr);
1263 log_assert(inst
->Input1Size() == inst
->OutputSize());
1265 SigSpec sig_d
, sig_q
, sig_o
;
1266 sig_q
= module
->addWire(new_verific_id(inst
), inst
->Input1Size());
1268 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--){
1269 sig_d
.append(net_map_at(inst
->GetInput1Bit(i
)));
1270 sig_o
.append(net_map_at(inst
->GetOutputBit(i
)));
1273 if (verific_verbose
) {
1274 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1275 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1276 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1277 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1280 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1281 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1287 if (inst
->Type() == PRIM_SVA_STABLE
)
1289 VerificClocking
clocking(this, inst
->GetInput2());
1290 log_assert(clocking
.disable_sig
== State::S0
);
1291 log_assert(clocking
.body_net
== nullptr);
1293 SigSpec sig_d
= net_map_at(inst
->GetInput1());
1294 SigSpec sig_o
= net_map_at(inst
->GetOutput());
1295 SigSpec sig_q
= module
->addWire(new_verific_id(inst
));
1297 if (verific_verbose
) {
1298 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1299 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1300 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1301 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1304 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1305 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1311 if (inst
->Type() == PRIM_SVA_PAST
)
1313 VerificClocking
clocking(this, inst
->GetInput2());
1314 log_assert(clocking
.disable_sig
== State::S0
);
1315 log_assert(clocking
.body_net
== nullptr);
1317 SigBit sig_d
= net_map_at(inst
->GetInput1());
1318 SigBit sig_q
= net_map_at(inst
->GetOutput());
1320 if (verific_verbose
)
1321 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1322 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1324 past_ffs
.insert(clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
));
1330 if ((inst
->Type() == PRIM_SVA_ROSE
|| inst
->Type() == PRIM_SVA_FELL
))
1332 VerificClocking
clocking(this, inst
->GetInput2());
1333 log_assert(clocking
.disable_sig
== State::S0
);
1334 log_assert(clocking
.body_net
== nullptr);
1336 SigBit sig_d
= net_map_at(inst
->GetInput1());
1337 SigBit sig_o
= net_map_at(inst
->GetOutput());
1338 SigBit sig_q
= module
->addWire(new_verific_id(inst
));
1340 if (verific_verbose
)
1341 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1342 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1344 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1345 module
->addEq(new_verific_id(inst
), {sig_q
, sig_d
}, Const(inst
->Type() == PRIM_SVA_ROSE
? 1 : 2, 2), sig_o
);
1351 if (!mode_keep
&& verific_sva_prims
.count(inst
->Type())) {
1352 if (verific_verbose
)
1353 log(" skipping SVA cell in non k-mode\n");
1357 if (inst
->Type() == PRIM_HDL_ASSERTION
)
1359 SigBit cond
= net_map_at(inst
->GetInput());
1361 if (verific_verbose
)
1362 log(" assert condition %s.\n", log_signal(cond
));
1364 const char *assume_attr
= nullptr; // inst->GetAttValue("assume");
1366 Cell
*cell
= nullptr;
1367 if (assume_attr
!= nullptr && !strcmp(assume_attr
, "1"))
1368 cell
= module
->addAssume(new_verific_id(inst
), cond
, State::S1
);
1370 cell
= module
->addAssert(new_verific_id(inst
), cond
, State::S1
);
1372 import_attributes(cell
->attributes
, inst
);
1376 if (inst
->IsPrimitive())
1379 log_error("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1381 if (!verific_sva_prims
.count(inst
->Type()))
1382 log_warning("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1385 import_verific_cells
:
1386 nl_todo
.insert(inst
->View());
1388 RTLIL::Cell
*cell
= module
->addCell(inst_name
, inst
->IsOperator() ?
1389 std::string("$verific$") + inst
->View()->Owner()->Name() : RTLIL::escape_id(inst
->View()->Owner()->Name()));
1391 if (inst
->IsPrimitive() && mode_keep
)
1392 cell
->attributes
["\\keep"] = 1;
1394 dict
<IdString
, vector
<SigBit
>> cell_port_conns
;
1396 if (verific_verbose
)
1397 log(" ports in verific db:\n");
1399 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
) {
1400 if (verific_verbose
)
1401 log(" .%s(%s)\n", pr
->GetPort()->Name(), pr
->GetNet()->Name());
1402 const char *port_name
= pr
->GetPort()->Name();
1403 int port_offset
= 0;
1404 if (pr
->GetPort()->Bus()) {
1405 port_name
= pr
->GetPort()->Bus()->Name();
1406 port_offset
= pr
->GetPort()->Bus()->IndexOf(pr
->GetPort()) -
1407 min(pr
->GetPort()->Bus()->LeftIndex(), pr
->GetPort()->Bus()->RightIndex());
1409 IdString port_name_id
= RTLIL::escape_id(port_name
);
1410 auto &sigvec
= cell_port_conns
[port_name_id
];
1411 if (GetSize(sigvec
) <= port_offset
) {
1412 SigSpec zwires
= module
->addWire(new_verific_id(inst
), port_offset
+1-GetSize(sigvec
));
1413 for (auto bit
: zwires
)
1414 sigvec
.push_back(bit
);
1416 sigvec
[port_offset
] = net_map_at(pr
->GetNet());
1419 if (verific_verbose
)
1420 log(" ports in yosys db:\n");
1422 for (auto &it
: cell_port_conns
) {
1423 if (verific_verbose
)
1424 log(" .%s(%s)\n", log_id(it
.first
), log_signal(it
.second
));
1425 cell
->setPort(it
.first
, it
.second
);
1431 for (auto inst
: sva_asserts
) {
1433 verific_import_sva_cover(this, inst
);
1434 verific_import_sva_assert(this, inst
);
1437 for (auto inst
: sva_assumes
)
1438 verific_import_sva_assume(this, inst
);
1440 for (auto inst
: sva_covers
)
1441 verific_import_sva_cover(this, inst
);
1443 for (auto inst
: sva_triggers
)
1444 verific_import_sva_trigger(this, inst
);
1446 merge_past_ffs(past_ffs
);
1450 // ==================================================================
1452 VerificClocking::VerificClocking(VerificImporter
*importer
, Net
*net
, bool sva_at_only
)
1454 module
= importer
->module
;
1456 log_assert(importer
!= nullptr);
1457 log_assert(net
!= nullptr);
1459 Instance
*inst
= net
->Driver();
1461 if (inst
!= nullptr && inst
->Type() == PRIM_SVA_AT
)
1463 net
= inst
->GetInput1();
1464 body_net
= inst
->GetInput2();
1466 inst
= net
->Driver();
1468 Instance
*body_inst
= body_net
->Driver();
1469 if (body_inst
!= nullptr && body_inst
->Type() == PRIM_SVA_DISABLE_IFF
) {
1470 disable_net
= body_inst
->GetInput1();
1471 disable_sig
= importer
->net_map_at(disable_net
);
1472 body_net
= body_inst
->GetInput2();
1481 // Use while() instead of if() to work around VIPER #13453
1482 while (inst
!= nullptr && inst
->Type() == PRIM_SVA_POSEDGE
)
1484 net
= inst
->GetInput();
1485 inst
= net
->Driver();;
1488 if (inst
!= nullptr && inst
->Type() == PRIM_INV
)
1490 net
= inst
->GetInput();
1491 inst
= net
->Driver();;
1495 // Detect clock-enable circuit
1497 if (inst
== nullptr || inst
->Type() != PRIM_AND
)
1500 Net
*net_dlatch
= inst
->GetInput1();
1501 Instance
*inst_dlatch
= net_dlatch
->Driver();
1503 if (inst_dlatch
== nullptr || inst_dlatch
->Type() != PRIM_DLATCHRS
)
1506 if (!inst_dlatch
->GetSet()->IsGnd() || !inst_dlatch
->GetReset()->IsGnd())
1509 Net
*net_enable
= inst_dlatch
->GetInput();
1510 Net
*net_not_clock
= inst_dlatch
->GetControl();
1512 if (net_enable
== nullptr || net_not_clock
== nullptr)
1515 Instance
*inst_not_clock
= net_not_clock
->Driver();
1517 if (inst_not_clock
== nullptr || inst_not_clock
->Type() != PRIM_INV
)
1520 Net
*net_clock1
= inst_not_clock
->GetInput();
1521 Net
*net_clock2
= inst
->GetInput2();
1523 if (net_clock1
== nullptr || net_clock1
!= net_clock2
)
1526 enable_net
= net_enable
;
1527 enable_sig
= importer
->net_map_at(enable_net
);
1530 inst
= net
->Driver();;
1533 // Detect condition expression
1535 if (body_net
== nullptr)
1538 Instance
*inst_mux
= body_net
->Driver();
1540 if (inst_mux
== nullptr || inst_mux
->Type() != PRIM_MUX
)
1543 if (!inst_mux
->GetInput1()->IsPwr())
1546 Net
*sva_net
= inst_mux
->GetInput2();
1547 if (!verific_is_sva_net(importer
, sva_net
))
1551 cond_net
= inst_mux
->GetControl();
1555 clock_sig
= importer
->net_map_at(clock_net
);
1557 const char *gclk_attr
= clock_net
->GetAttValue("gclk");
1558 if (gclk_attr
!= nullptr && (!strcmp(gclk_attr
, "1") || !strcmp(gclk_attr
, "'1'")))
1562 Cell
*VerificClocking::addDff(IdString name
, SigSpec sig_d
, SigSpec sig_q
, Const init_value
)
1564 log_assert(GetSize(sig_d
) == GetSize(sig_q
));
1566 if (GetSize(init_value
) != 0) {
1567 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1568 if (sig_q
.is_wire()) {
1569 sig_q
.as_wire()->attributes
["\\init"] = init_value
;
1571 Wire
*w
= module
->addWire(NEW_ID
, GetSize(sig_q
));
1572 w
->attributes
["\\init"] = init_value
;
1573 module
->connect(sig_q
, w
);
1578 if (enable_sig
!= State::S1
)
1579 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1581 if (disable_sig
!= State::S0
) {
1582 log_assert(gclk
== false);
1583 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1584 return module
->addAdff(name
, clock_sig
, disable_sig
, sig_d
, sig_q
, init_value
, posedge
);
1588 return module
->addFf(name
, sig_d
, sig_q
);
1590 return module
->addDff(name
, clock_sig
, sig_d
, sig_q
, posedge
);
1593 Cell
*VerificClocking::addAdff(IdString name
, RTLIL::SigSpec sig_arst
, SigSpec sig_d
, SigSpec sig_q
, Const arst_value
)
1595 log_assert(gclk
== false);
1596 log_assert(disable_sig
== State::S0
);
1598 if (enable_sig
!= State::S1
)
1599 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1601 return module
->addAdff(name
, clock_sig
, sig_arst
, sig_d
, sig_q
, arst_value
, posedge
);
1604 Cell
*VerificClocking::addDffsr(IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, SigSpec sig_d
, SigSpec sig_q
)
1606 log_assert(gclk
== false);
1607 log_assert(disable_sig
== State::S0
);
1609 if (enable_sig
!= State::S1
)
1610 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1612 return module
->addDffsr(name
, clock_sig
, sig_set
, sig_clr
, sig_d
, sig_q
, posedge
);
1615 // ==================================================================
1617 struct VerificExtNets
1619 int portname_cnt
= 0;
1621 // a map from Net to the same Net one level up in the design hierarchy
1622 std::map
<Net
*, Net
*> net_level_up_drive_up
;
1623 std::map
<Net
*, Net
*> net_level_up_drive_down
;
1625 Net
*route_up(Net
*net
, bool drive_up
, Net
*final_net
= nullptr)
1627 auto &net_level_up
= drive_up
? net_level_up_drive_up
: net_level_up_drive_down
;
1629 if (net_level_up
.count(net
) == 0)
1631 Netlist
*nl
= net
->Owner();
1633 // Simply return if Netlist is not unique
1634 log_assert(nl
->NumOfRefs() == 1);
1636 Instance
*up_inst
= (Instance
*)nl
->GetReferences()->GetLast();
1637 Netlist
*up_nl
= up_inst
->Owner();
1640 string name
= stringf("___extnets_%d", portname_cnt
++);
1641 Port
*new_port
= new Port(name
.c_str(), drive_up
? DIR_OUT
: DIR_IN
);
1643 net
->Connect(new_port
);
1645 // create new Net in up Netlist
1646 Net
*new_net
= final_net
;
1647 if (new_net
== nullptr || new_net
->Owner() != up_nl
) {
1648 new_net
= new Net(name
.c_str());
1649 up_nl
->Add(new_net
);
1651 up_inst
->Connect(new_port
, new_net
);
1653 net_level_up
[net
] = new_net
;
1656 return net_level_up
.at(net
);
1659 Net
*route_up(Net
*net
, bool drive_up
, Netlist
*dest
, Net
*final_net
= nullptr)
1661 while (net
->Owner() != dest
)
1662 net
= route_up(net
, drive_up
, final_net
);
1663 if (final_net
!= nullptr)
1664 log_assert(net
== final_net
);
1668 Netlist
*find_common_ancestor(Netlist
*A
, Netlist
*B
)
1670 std::set
<Netlist
*> ancestors_of_A
;
1672 Netlist
*cursor
= A
;
1674 ancestors_of_A
.insert(cursor
);
1675 if (cursor
->NumOfRefs() != 1)
1677 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1682 if (ancestors_of_A
.count(cursor
))
1684 if (cursor
->NumOfRefs() != 1)
1686 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1689 log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A
).c_str(), get_full_netlist_name(B
).c_str());
1692 void run(Netlist
*nl
)
1698 vector
<tuple
<Instance
*, Port
*, Net
*>> todo_connect
;
1700 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1703 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1704 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
)
1706 Port
*port
= pr
->GetPort();
1707 Net
*net
= pr
->GetNet();
1709 if (!net
->IsExternalTo(nl
))
1712 if (verific_verbose
)
1713 log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl
).c_str(), inst
->Name(), port
->Name());
1715 Netlist
*ext_nl
= net
->Owner();
1717 if (verific_verbose
)
1718 log(" external net owner: %s\n", get_full_netlist_name(ext_nl
).c_str());
1720 Netlist
*ca_nl
= find_common_ancestor(nl
, ext_nl
);
1722 if (verific_verbose
)
1723 log(" common ancestor: %s\n", get_full_netlist_name(ca_nl
).c_str());
1725 Net
*ca_net
= route_up(net
, !port
->IsOutput(), ca_nl
);
1726 Net
*new_net
= ca_net
;
1730 if (verific_verbose
)
1731 log(" net in common ancestor: %s\n", ca_net
->Name());
1733 string name
= stringf("___extnets_%d", portname_cnt
++);
1734 new_net
= new Net(name
.c_str());
1737 Net
*n
= route_up(new_net
, port
->IsOutput(), ca_nl
, ca_net
);
1738 log_assert(n
== ca_net
);
1741 if (verific_verbose
)
1742 log(" new local net: %s\n", new_net
->Name());
1744 log_assert(!new_net
->IsExternalTo(nl
));
1745 todo_connect
.push_back(tuple
<Instance
*, Port
*, Net
*>(inst
, port
, new_net
));
1748 for (auto it
: todo_connect
) {
1749 get
<0>(it
)->Disconnect(get
<1>(it
));
1750 get
<0>(it
)->Connect(get
<1>(it
), get
<2>(it
));
1755 void verific_import(Design
*design
, std::string top
)
1757 verific_sva_fsm_limit
= 16;
1759 std::set
<Netlist
*> nl_todo
, nl_done
;
1762 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary("work", 1);
1763 VeriLibrary
*veri_lib
= veri_file::GetLibrary("work", 1);
1765 Array veri_libs
, vhdl_libs
;
1766 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
1767 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
1769 Array
*netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
);
1773 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
1774 if (top
.empty() || nl
->Owner()->Name() == top
)
1781 if (!verific_error_msg
.empty())
1782 log_error("%s\n", verific_error_msg
.c_str());
1784 VerificExtNets worker
;
1785 for (auto nl
: nl_todo
)
1788 while (!nl_todo
.empty()) {
1789 Netlist
*nl
= *nl_todo
.begin();
1790 if (nl_done
.count(nl
) == 0) {
1791 VerificImporter
importer(false, false, false, false, false, false);
1792 importer
.import_netlist(design
, nl
, nl_todo
);
1801 verific_incdirs
.clear();
1802 verific_libdirs
.clear();
1803 verific_import_pending
= false;
1805 if (!verific_error_msg
.empty())
1806 log_error("%s\n", verific_error_msg
.c_str());
1810 #endif /* YOSYS_ENABLE_VERIFIC */
1812 PRIVATE_NAMESPACE_BEGIN
1814 #ifdef YOSYS_ENABLE_VERIFIC
1815 bool check_noverific_env()
1817 const char *e
= getenv("YOSYS_NOVERIFIC");
1826 struct VerificPass
: public Pass
{
1827 VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
1828 void help() YS_OVERRIDE
1830 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1832 log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
1834 log("Load the specified Verilog/SystemVerilog files into Verific.\n");
1836 log("All files specified in one call to this command are one compilation unit.\n");
1837 log("Files passed to different calls to this command are treated as belonging to\n");
1838 log("different compilation units.\n");
1840 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
1841 log("the language version (and before file names) to set additional verilog defines.\n");
1842 log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
1845 log(" verific -formal <verilog-file>..\n");
1847 log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
1850 log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
1852 log("Load the specified VHDL files into Verific.\n");
1855 log(" verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
1857 log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
1858 log("(default library when -work is not present: \"work\")\n");
1861 log(" verific -vlog-incdir <directory>..\n");
1863 log("Add Verilog include directories.\n");
1866 log(" verific -vlog-libdir <directory>..\n");
1868 log("Add Verilog library directories. Verific will search in this directories to\n");
1869 log("find undefined modules.\n");
1872 log(" verific -vlog-define <macro>[=<value>]..\n");
1874 log("Add Verilog defines.\n");
1877 log(" verific -vlog-undef <macro>..\n");
1879 log("Remove Verilog defines previously set with -vlog-define.\n");
1882 log(" verific -set-error <msg_id>..\n");
1883 log(" verific -set-warning <msg_id>..\n");
1884 log(" verific -set-info <msg_id>..\n");
1885 log(" verific -set-ignore <msg_id>..\n");
1887 log("Set message severity. <msg_id> is the string in square brackets when a message\n");
1888 log("is printed, such as VERI-1209.\n");
1891 log(" verific -import [options] <top-module>..\n");
1893 log("Elaborate the design for the specified top modules, import to Yosys and\n");
1894 log("reset the internal state of Verific.\n");
1896 log("Import options:\n");
1899 log(" Elaborate all modules, not just the hierarchy below the given top\n");
1900 log(" modules. With this option the list of modules to import is optional.\n");
1903 log(" Create a gate-level netlist.\n");
1906 log(" Flatten the design in Verific before importing.\n");
1909 log(" Resolve references to external nets by adding module ports as needed.\n");
1911 log(" -autocover\n");
1912 log(" Generate automatic cover statements for all asserts\n");
1914 log(" -chparam name value \n");
1915 log(" Elaborate the specified top modules (all modules when -all given) using\n");
1916 log(" this parameter value. Modules on which this parameter does not exist will\n");
1917 log(" cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
1918 log(" can be specified multiple times to override multiple parameters.\n");
1919 log(" String values must be passed in double quotes (\").\n");
1922 log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
1924 log("The following additional import options are useful for debugging the Verific\n");
1925 log("bindings (for Yosys and/or Verific developers):\n");
1928 log(" Keep going after an unsupported verific primitive is found. The\n");
1929 log(" unsupported primitive is added as blockbox module to the design.\n");
1930 log(" This will also add all SVA related cells to the design parallel to\n");
1931 log(" the checker logic inferred by it.\n");
1934 log(" Import Verific netlist as-is without translating to Yosys cell types. \n");
1937 log(" Ignore SVA properties, do not infer checker logic.\n");
1940 log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
1943 log(" Keep all Verific names on instances and nets. By default only\n");
1944 log(" user-declared names are preserved.\n");
1946 log(" -d <dump_file>\n");
1947 log(" Dump the Verific netlist as a verilog file.\n");
1949 log("Visit http://verific.com/ for more information on Verific.\n");
1952 #ifdef YOSYS_ENABLE_VERIFIC
1953 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1955 static bool set_verific_global_flags
= true;
1957 if (check_noverific_env())
1958 log_cmd_error("This version of Yosys is built without Verific support.\n");
1960 log_header(design
, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
1962 if (set_verific_global_flags
)
1964 Message::SetConsoleOutput(0);
1965 Message::RegisterCallBackMsg(msg_func
);
1967 RuntimeFlags::SetVar("db_preserve_user_nets", 1);
1968 RuntimeFlags::SetVar("db_allow_external_nets", 1);
1969 RuntimeFlags::SetVar("db_infer_wide_operators", 1);
1971 RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
1972 RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
1974 RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
1975 RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
1977 RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
1978 RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
1980 // Workaround for VIPER #13851
1981 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
1983 // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
1984 Message::SetMessageType("VERI-1063", VERIFIC_ERROR
);
1986 #ifndef DB_PRESERVE_INITIAL_VALUE
1987 # warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
1990 set_verific_global_flags
= false;
1993 verific_verbose
= 0;
1994 verific_sva_fsm_limit
= 16;
1996 const char *release_str
= Message::ReleaseString();
1997 time_t release_time
= Message::ReleaseDate();
1998 char *release_tmstr
= ctime(&release_time
);
2000 if (release_str
== nullptr)
2001 release_str
= "(no release string)";
2003 for (char *p
= release_tmstr
; *p
; p
++)
2004 if (*p
== '\n') *p
= 0;
2006 log("Built with Verific %s, released at %s.\n", release_str
, release_tmstr
);
2009 std::string work
= "work";
2011 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-set-error" || args
[argidx
] == "-set-warning" ||
2012 args
[argidx
] == "-set-info" || args
[argidx
] == "-set-ignore"))
2014 msg_type_t new_type
;
2016 if (args
[argidx
] == "-set-error")
2017 new_type
= VERIFIC_ERROR
;
2018 else if (args
[argidx
] == "-set-warning")
2019 new_type
= VERIFIC_WARNING
;
2020 else if (args
[argidx
] == "-set-info")
2021 new_type
= VERIFIC_INFO
;
2022 else if (args
[argidx
] == "-set-ignore")
2023 new_type
= VERIFIC_IGNORE
;
2027 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2028 Message::SetMessageType(args
[argidx
].c_str(), new_type
);
2033 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-incdir") {
2034 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2035 verific_incdirs
.push_back(args
[argidx
]);
2039 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-libdir") {
2040 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2041 verific_libdirs
.push_back(args
[argidx
]);
2045 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-define") {
2046 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2047 string name
= args
[argidx
];
2048 size_t equal
= name
.find('=');
2049 if (equal
!= std::string::npos
) {
2050 string value
= name
.substr(equal
+1);
2051 name
= name
.substr(0, equal
);
2052 veri_file::DefineCmdLineMacro(name
.c_str(), value
.c_str());
2054 veri_file::DefineCmdLineMacro(name
.c_str());
2060 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-undef") {
2061 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2062 string name
= args
[argidx
];
2063 veri_file::UndefineMacro(name
.c_str());
2068 for (; argidx
< GetSize(args
); argidx
++)
2070 if (args
[argidx
] == "-work" && argidx
+1 < GetSize(args
)) {
2071 work
= args
[++argidx
];
2077 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vlog95" || args
[argidx
] == "-vlog2k" || args
[argidx
] == "-sv2005" ||
2078 args
[argidx
] == "-sv2009" || args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal"))
2081 unsigned verilog_mode
;
2083 if (args
[argidx
] == "-vlog95")
2084 verilog_mode
= veri_file::VERILOG_95
;
2085 else if (args
[argidx
] == "-vlog2k")
2086 verilog_mode
= veri_file::VERILOG_2K
;
2087 else if (args
[argidx
] == "-sv2005")
2088 verilog_mode
= veri_file::SYSTEM_VERILOG_2005
;
2089 else if (args
[argidx
] == "-sv2009")
2090 verilog_mode
= veri_file::SYSTEM_VERILOG_2009
;
2091 else if (args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal")
2092 verilog_mode
= veri_file::SYSTEM_VERILOG
;
2096 veri_file::DefineMacro("VERIFIC");
2097 veri_file::DefineMacro(args
[argidx
] == "-formal" ? "FORMAL" : "SYNTHESIS");
2099 for (argidx
++; argidx
< GetSize(args
) && GetSize(args
[argidx
]) >= 2 && args
[argidx
].substr(0, 2) == "-D"; argidx
++) {
2100 std::string name
= args
[argidx
].substr(2);
2101 if (args
[argidx
] == "-D") {
2102 if (++argidx
>= GetSize(args
))
2104 name
= args
[argidx
];
2106 size_t equal
= name
.find('=');
2107 if (equal
!= std::string::npos
) {
2108 string value
= name
.substr(equal
+1);
2109 name
= name
.substr(0, equal
);
2110 veri_file::DefineMacro(name
.c_str(), value
.c_str());
2112 veri_file::DefineMacro(name
.c_str());
2116 for (auto &dir
: verific_incdirs
)
2117 veri_file::AddIncludeDir(dir
.c_str());
2118 for (auto &dir
: verific_libdirs
)
2119 veri_file::AddYDir(dir
.c_str());
2121 while (argidx
< GetSize(args
))
2122 file_names
.Insert(args
[argidx
++].c_str());
2124 if (!veri_file::AnalyzeMultipleFiles(&file_names
, verilog_mode
, work
.c_str(), veri_file::MFCU
))
2125 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2127 verific_import_pending
= true;
2131 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl87") {
2132 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
2133 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2134 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_87
))
2135 log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args
[argidx
].c_str());
2136 verific_import_pending
= true;
2140 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl93") {
2141 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2142 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2143 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_93
))
2144 log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args
[argidx
].c_str());
2145 verific_import_pending
= true;
2149 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl2k") {
2150 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2151 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2152 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2K
))
2153 log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args
[argidx
].c_str());
2154 verific_import_pending
= true;
2158 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vhdl2008" || args
[argidx
] == "-vhdl")) {
2159 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
2160 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2161 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2008
))
2162 log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args
[argidx
].c_str());
2163 verific_import_pending
= true;
2167 if (GetSize(args
) > argidx
&& args
[argidx
] == "-import")
2169 std::set
<Netlist
*> nl_todo
, nl_done
;
2170 bool mode_all
= false, mode_gates
= false, mode_keep
= false;
2171 bool mode_nosva
= false, mode_names
= false, mode_verific
= false;
2172 bool mode_autocover
= false;
2173 bool flatten
= false, extnets
= false;
2175 Map
parameters(STRING_HASH
);
2177 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2178 if (args
[argidx
] == "-all") {
2182 if (args
[argidx
] == "-gates") {
2186 if (args
[argidx
] == "-flatten") {
2190 if (args
[argidx
] == "-extnets") {
2194 if (args
[argidx
] == "-k") {
2198 if (args
[argidx
] == "-nosva") {
2202 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2203 verific_sva_fsm_limit
= atoi(args
[++argidx
].c_str());
2206 if (args
[argidx
] == "-n") {
2210 if (args
[argidx
] == "-autocover") {
2211 mode_autocover
= true;
2214 if (args
[argidx
] == "-chparam" && argidx
+2 < GetSize(args
)) {
2215 const std::string
&key
= args
[++argidx
];
2216 const std::string
&value
= args
[++argidx
];
2217 unsigned new_insertion
= parameters
.Insert(key
.c_str(), value
.c_str(),
2218 1 /* force_overwrite */);
2220 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key
.c_str());
2223 if (args
[argidx
] == "-V") {
2224 mode_verific
= true;
2227 if (args
[argidx
] == "-v") {
2228 verific_verbose
= 1;
2231 if (args
[argidx
] == "-vv") {
2232 verific_verbose
= 2;
2235 if (args
[argidx
] == "-d" && argidx
+1 < GetSize(args
)) {
2236 dumpfile
= args
[++argidx
];
2242 if (argidx
> GetSize(args
) && args
[argidx
].substr(0, 1) == "-")
2243 cmd_error(args
, argidx
, "unknown option");
2247 log("Running hier_tree::ElaborateAll().\n");
2249 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2250 VeriLibrary
*veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2252 Array veri_libs
, vhdl_libs
;
2253 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
2254 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
2256 Array
*netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, ¶meters
);
2260 FOREACH_ARRAY_ITEM(netlists
, i
, nl
)
2266 if (argidx
== GetSize(args
))
2267 log_cmd_error("No top module specified.\n");
2269 Array veri_modules
, vhdl_units
;
2270 for (; argidx
< GetSize(args
); argidx
++)
2272 const char *name
= args
[argidx
].c_str();
2274 VeriModule
*veri_module
= veri_file::GetModule(name
);
2276 log("Adding Verilog module '%s' to elaboration queue.\n", name
);
2277 veri_modules
.InsertLast(veri_module
);
2281 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2282 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(name
);
2284 log("Adding VHDL unit '%s' to elaboration queue.\n", name
);
2285 vhdl_units
.InsertLast(vhdl_unit
);
2289 log_error("Can't find module/unit '%s'.\n", name
);
2292 log("Running hier_tree::Elaborate().\n");
2293 Array
*netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, ¶meters
);
2297 FOREACH_ARRAY_ITEM(netlists
, i
, nl
)
2302 if (!verific_error_msg
.empty())
2306 for (auto nl
: nl_todo
)
2311 VerificExtNets worker
;
2312 for (auto nl
: nl_todo
)
2316 if (!dumpfile
.empty()) {
2317 VeriWrite veri_writer
;
2318 veri_writer
.WriteFile(dumpfile
.c_str(), Netlist::PresentDesign());
2321 while (!nl_todo
.empty()) {
2322 Netlist
*nl
= *nl_todo
.begin();
2323 if (nl_done
.count(nl
) == 0) {
2324 VerificImporter
importer(mode_gates
, mode_keep
, mode_nosva
,
2325 mode_names
, mode_verific
, mode_autocover
);
2326 importer
.import_netlist(design
, nl
, nl_todo
);
2335 verific_incdirs
.clear();
2336 verific_libdirs
.clear();
2337 verific_import_pending
= false;
2341 log_cmd_error("Missing or unsupported mode parameter.\n");
2344 if (!verific_error_msg
.empty())
2345 log_error("%s\n", verific_error_msg
.c_str());
2348 #else /* YOSYS_ENABLE_VERIFIC */
2349 void execute(std::vector
<std::string
>, RTLIL::Design
*) YS_OVERRIDE
{
2350 log_cmd_error("This version of Yosys is built without Verific support.\n");
2355 struct ReadPass
: public Pass
{
2356 ReadPass() : Pass("read", "load HDL designs") { }
2357 void help() YS_OVERRIDE
2359 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2361 log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
2363 log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
2364 log("is only available via Verific.)\n");
2366 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2367 log("the language version (and before file names) to set additional verilog defines.\n");
2370 log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2372 log("Load the specified VHDL files. (Requires Verific.)\n");
2375 log(" read -define <macro>[=<value>]..\n");
2377 log("Set global Verilog/SystemVerilog defines.\n");
2380 log(" read -undef <macro>..\n");
2382 log("Unset global Verilog/SystemVerilog defines.\n");
2385 log(" read -incdir <directory>\n");
2387 log("Add directory to global Verilog/SystemVerilog include directories.\n");
2390 log(" read -verific\n");
2391 log(" read -noverific\n");
2393 log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
2394 log("with -verific will result in an error on Yosys binaries that are built without\n");
2395 log("Verific support. The default is to use Verific if it is available.\n");
2398 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
2400 #ifdef YOSYS_ENABLE_VERIFIC
2401 static bool verific_available
= !check_noverific_env();
2403 static bool verific_available
= false;
2405 static bool use_verific
= verific_available
;
2407 if (args
.size() < 2 || args
[1][0] != '-')
2408 log_cmd_error("Missing mode parameter.\n");
2410 if (args
[1] == "-verific" || args
[1] == "-noverific") {
2411 if (args
.size() != 2)
2412 log_cmd_error("Additional arguments to -verific/-noverific.\n");
2413 if (args
[1] == "-verific") {
2414 if (!verific_available
)
2415 log_cmd_error("This version of Yosys is built without Verific support.\n");
2418 use_verific
= false;
2423 if (args
.size() < 3)
2424 log_cmd_error("Missing file name parameter.\n");
2426 if (args
[1] == "-vlog95" || args
[1] == "-vlog2k") {
2428 args
[0] = "verific";
2430 args
[0] = "read_verilog";
2431 args
.erase(args
.begin()+1, args
.begin()+2);
2433 Pass::call(design
, args
);
2437 if (args
[1] == "-sv2005" || args
[1] == "-sv2009" || args
[1] == "-sv2012" || args
[1] == "-sv" || args
[1] == "-formal") {
2439 args
[0] = "verific";
2441 args
[0] = "read_verilog";
2442 if (args
[1] == "-formal")
2443 args
.insert(args
.begin()+1, std::string());
2446 Pass::call(design
, args
);
2450 if (args
[1] == "-vhdl87" || args
[1] == "-vhdl93" || args
[1] == "-vhdl2k" || args
[1] == "-vhdl2008" || args
[1] == "-vhdl") {
2452 args
[0] = "verific";
2453 Pass::call(design
, args
);
2455 log_cmd_error("This version of Yosys is built without Verific support.\n");
2460 if (args
[1] == "-define") {
2462 args
[0] = "verific";
2463 args
[1] = "-vlog-define";
2464 Pass::call(design
, args
);
2466 args
[0] = "verilog_defines";
2467 args
.erase(args
.begin()+1, args
.begin()+2);
2468 for (int i
= 1; i
< GetSize(args
); i
++)
2469 args
[i
] = "-D" + args
[i
];
2470 Pass::call(design
, args
);
2474 if (args
[1] == "-undef") {
2476 args
[0] = "verific";
2477 args
[1] = "-vlog-undef";
2478 Pass::call(design
, args
);
2480 args
[0] = "verilog_defines";
2481 args
.erase(args
.begin()+1, args
.begin()+2);
2482 for (int i
= 1; i
< GetSize(args
); i
++)
2483 args
[i
] = "-U" + args
[i
];
2484 Pass::call(design
, args
);
2488 if (args
[1] == "-incdir") {
2490 args
[0] = "verific";
2491 args
[1] = "-vlog-incdir";
2492 Pass::call(design
, args
);
2494 args
[0] = "verilog_defaults";
2496 for (int i
= 2; i
< GetSize(args
); i
++)
2497 args
[i
] = "-I" + args
[i
];
2498 Pass::call(design
, args
);
2502 log_cmd_error("Missing or unsupported mode parameter.\n");
2506 PRIVATE_NAMESPACE_END