2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/log.h"
33 #include "frontends/verific/verific.h"
37 #ifdef YOSYS_ENABLE_VERIFIC
40 #pragma clang diagnostic push
41 #pragma clang diagnostic ignored "-Woverloaded-virtual"
44 #include "veri_file.h"
45 #include "vhdl_file.h"
46 #include "hier_tree.h"
47 #include "VeriModule.h"
48 #include "VeriWrite.h"
49 #include "VhdlUnits.h"
50 #include "VeriLibrary.h"
52 #ifndef SYMBIOTIC_VERIFIC_API_VERSION
53 # error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
56 #if SYMBIOTIC_VERIFIC_API_VERSION < 1
57 # error "Please update your version of Symbiotic EDA flavored Verific."
61 #pragma clang diagnostic pop
64 #ifdef VERIFIC_NAMESPACE
65 using namespace Verific
;
70 #ifdef YOSYS_ENABLE_VERIFIC
74 bool verific_import_pending
;
75 string verific_error_msg
;
76 int verific_sva_fsm_limit
;
78 vector
<string
> verific_incdirs
, verific_libdirs
;
80 void msg_func(msg_type_t msg_type
, const char *message_id
, linefile_type linefile
, const char *msg
, va_list args
)
82 string message_prefix
= stringf("VERIFIC-%s [%s] ",
83 msg_type
== VERIFIC_NONE
? "NONE" :
84 msg_type
== VERIFIC_ERROR
? "ERROR" :
85 msg_type
== VERIFIC_WARNING
? "WARNING" :
86 msg_type
== VERIFIC_IGNORE
? "IGNORE" :
87 msg_type
== VERIFIC_INFO
? "INFO" :
88 msg_type
== VERIFIC_COMMENT
? "COMMENT" :
89 msg_type
== VERIFIC_PROGRAM_ERROR
? "PROGRAM_ERROR" : "UNKNOWN", message_id
);
91 string message
= linefile
? stringf("%s:%d: ", LineFile::GetFileName(linefile
), LineFile::GetLineNo(linefile
)) : "";
92 message
+= vstringf(msg
, args
);
94 if (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_WARNING
|| msg_type
== VERIFIC_PROGRAM_ERROR
)
95 log_warning_noprefix("%s%s\n", message_prefix
.c_str(), message
.c_str());
97 log("%s%s\n", message_prefix
.c_str(), message
.c_str());
99 if (verific_error_msg
.empty() && (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_PROGRAM_ERROR
))
100 verific_error_msg
= message
;
103 string
get_full_netlist_name(Netlist
*nl
)
105 if (nl
->NumOfRefs() == 1) {
106 Instance
*inst
= (Instance
*)nl
->GetReferences()->GetLast();
107 return get_full_netlist_name(inst
->Owner()) + "." + inst
->Name();
110 return nl
->CellBaseName();
113 // ==================================================================
115 VerificImporter::VerificImporter(bool mode_gates
, bool mode_keep
, bool mode_nosva
, bool mode_names
, bool mode_verific
, bool mode_autocover
, bool mode_fullinit
) :
116 mode_gates(mode_gates
), mode_keep(mode_keep
), mode_nosva(mode_nosva
),
117 mode_names(mode_names
), mode_verific(mode_verific
), mode_autocover(mode_autocover
),
118 mode_fullinit(mode_fullinit
)
122 RTLIL::SigBit
VerificImporter::net_map_at(Net
*net
)
124 if (net
->IsExternalTo(netlist
))
125 log_error("Found external reference to '%s.%s' in netlist '%s', please use -flatten or -extnets.\n",
126 get_full_netlist_name(net
->Owner()).c_str(), net
->Name(), get_full_netlist_name(netlist
).c_str());
128 return net_map
.at(net
);
131 bool is_blackbox(Netlist
*nl
)
133 if (nl
->IsBlackBox() || nl
->IsEmptyBox())
136 const char *attr
= nl
->GetAttValue("blackbox");
137 if (attr
!= nullptr && strcmp(attr
, "0"))
143 RTLIL::IdString
VerificImporter::new_verific_id(Verific::DesignObj
*obj
)
145 std::string s
= stringf("$verific$%s", obj
->Name());
147 s
+= stringf("$%s:%d", Verific::LineFile::GetFileName(obj
->Linefile()), Verific::LineFile::GetLineNo(obj
->Linefile()));
148 s
+= stringf("$%d", autoidx
++);
152 void VerificImporter::import_attributes(dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, DesignObj
*obj
)
158 attributes
["\\src"] = stringf("%s:%d", LineFile::GetFileName(obj
->Linefile()), LineFile::GetLineNo(obj
->Linefile()));
160 // FIXME: Parse numeric attributes
161 FOREACH_ATTRIBUTE(obj
, mi
, attr
) {
162 if (attr
->Key()[0] == ' ' || attr
->Value() == nullptr)
164 attributes
[RTLIL::escape_id(attr
->Key())] = RTLIL::Const(std::string(attr
->Value()));
168 RTLIL::SigSpec
VerificImporter::operatorInput(Instance
*inst
)
171 for (int i
= int(inst
->InputSize())-1; i
>= 0; i
--)
172 if (inst
->GetInputBit(i
))
173 sig
.append(net_map_at(inst
->GetInputBit(i
)));
175 sig
.append(RTLIL::State::Sz
);
179 RTLIL::SigSpec
VerificImporter::operatorInput1(Instance
*inst
)
182 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--)
183 if (inst
->GetInput1Bit(i
))
184 sig
.append(net_map_at(inst
->GetInput1Bit(i
)));
186 sig
.append(RTLIL::State::Sz
);
190 RTLIL::SigSpec
VerificImporter::operatorInput2(Instance
*inst
)
193 for (int i
= int(inst
->Input2Size())-1; i
>= 0; i
--)
194 if (inst
->GetInput2Bit(i
))
195 sig
.append(net_map_at(inst
->GetInput2Bit(i
)));
197 sig
.append(RTLIL::State::Sz
);
201 RTLIL::SigSpec
VerificImporter::operatorInport(Instance
*inst
, const char *portname
)
203 PortBus
*portbus
= inst
->View()->GetPortBus(portname
);
206 for (unsigned i
= 0; i
< portbus
->Size(); i
++) {
207 Net
*net
= inst
->GetNet(portbus
->ElementAtIndex(i
));
210 sig
.append(RTLIL::State::S0
);
211 else if (net
->IsPwr())
212 sig
.append(RTLIL::State::S1
);
214 sig
.append(net_map_at(net
));
216 sig
.append(RTLIL::State::Sz
);
220 Port
*port
= inst
->View()->GetPort(portname
);
221 log_assert(port
!= NULL
);
222 Net
*net
= inst
->GetNet(port
);
223 return net_map_at(net
);
227 RTLIL::SigSpec
VerificImporter::operatorOutput(Instance
*inst
, const pool
<Net
*, hash_ptr_ops
> *any_all_nets
)
230 RTLIL::Wire
*dummy_wire
= NULL
;
231 for (int i
= int(inst
->OutputSize())-1; i
>= 0; i
--)
232 if (inst
->GetOutputBit(i
) && (!any_all_nets
|| !any_all_nets
->count(inst
->GetOutputBit(i
)))) {
233 sig
.append(net_map_at(inst
->GetOutputBit(i
)));
236 if (dummy_wire
== NULL
)
237 dummy_wire
= module
->addWire(new_verific_id(inst
));
240 sig
.append(RTLIL::SigSpec(dummy_wire
, dummy_wire
->width
- 1));
245 bool VerificImporter::import_netlist_instance_gates(Instance
*inst
, RTLIL::IdString inst_name
)
247 if (inst
->Type() == PRIM_AND
) {
248 module
->addAndGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
252 if (inst
->Type() == PRIM_NAND
) {
253 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
254 module
->addAndGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
255 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
259 if (inst
->Type() == PRIM_OR
) {
260 module
->addOrGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
264 if (inst
->Type() == PRIM_NOR
) {
265 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
266 module
->addOrGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
267 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
271 if (inst
->Type() == PRIM_XOR
) {
272 module
->addXorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
276 if (inst
->Type() == PRIM_XNOR
) {
277 module
->addXnorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
281 if (inst
->Type() == PRIM_BUF
) {
282 auto outnet
= inst
->GetOutput();
283 if (!any_all_nets
.count(outnet
))
284 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
288 if (inst
->Type() == PRIM_INV
) {
289 module
->addNotGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
293 if (inst
->Type() == PRIM_MUX
) {
294 module
->addMuxGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
298 if (inst
->Type() == PRIM_TRI
) {
299 module
->addMuxGate(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
303 if (inst
->Type() == PRIM_FADD
)
305 RTLIL::SigSpec a
= net_map_at(inst
->GetInput1()), b
= net_map_at(inst
->GetInput2()), c
= net_map_at(inst
->GetCin());
306 RTLIL::SigSpec x
= inst
->GetCout() ? net_map_at(inst
->GetCout()) : module
->addWire(new_verific_id(inst
));
307 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
308 RTLIL::SigSpec tmp1
= module
->addWire(new_verific_id(inst
));
309 RTLIL::SigSpec tmp2
= module
->addWire(new_verific_id(inst
));
310 RTLIL::SigSpec tmp3
= module
->addWire(new_verific_id(inst
));
311 module
->addXorGate(new_verific_id(inst
), a
, b
, tmp1
);
312 module
->addXorGate(inst_name
, tmp1
, c
, y
);
313 module
->addAndGate(new_verific_id(inst
), tmp1
, c
, tmp2
);
314 module
->addAndGate(new_verific_id(inst
), a
, b
, tmp3
);
315 module
->addOrGate(new_verific_id(inst
), tmp2
, tmp3
, x
);
319 if (inst
->Type() == PRIM_DFFRS
)
321 VerificClocking
clocking(this, inst
->GetClock());
322 log_assert(clocking
.disable_sig
== State::S0
);
323 log_assert(clocking
.body_net
== nullptr);
325 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
326 clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
327 else if (inst
->GetSet()->IsGnd())
328 clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S0
);
329 else if (inst
->GetReset()->IsGnd())
330 clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S1
);
332 clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
333 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
340 bool VerificImporter::import_netlist_instance_cells(Instance
*inst
, RTLIL::IdString inst_name
)
342 RTLIL::Cell
*cell
= nullptr;
344 if (inst
->Type() == PRIM_AND
) {
345 cell
= module
->addAnd(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
346 import_attributes(cell
->attributes
, inst
);
350 if (inst
->Type() == PRIM_NAND
) {
351 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
352 cell
= module
->addAnd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
353 import_attributes(cell
->attributes
, inst
);
354 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
355 import_attributes(cell
->attributes
, inst
);
359 if (inst
->Type() == PRIM_OR
) {
360 cell
= module
->addOr(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
361 import_attributes(cell
->attributes
, inst
);
365 if (inst
->Type() == PRIM_NOR
) {
366 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
367 cell
= module
->addOr(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
368 import_attributes(cell
->attributes
, inst
);
369 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
370 import_attributes(cell
->attributes
, inst
);
374 if (inst
->Type() == PRIM_XOR
) {
375 cell
= module
->addXor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
376 import_attributes(cell
->attributes
, inst
);
380 if (inst
->Type() == PRIM_XNOR
) {
381 cell
= module
->addXnor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
382 import_attributes(cell
->attributes
, inst
);
386 if (inst
->Type() == PRIM_INV
) {
387 cell
= module
->addNot(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
388 import_attributes(cell
->attributes
, inst
);
392 if (inst
->Type() == PRIM_MUX
) {
393 cell
= module
->addMux(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
394 import_attributes(cell
->attributes
, inst
);
398 if (inst
->Type() == PRIM_TRI
) {
399 cell
= module
->addMux(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
400 import_attributes(cell
->attributes
, inst
);
404 if (inst
->Type() == PRIM_FADD
)
406 RTLIL::SigSpec a_plus_b
= module
->addWire(new_verific_id(inst
), 2);
407 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
409 y
.append(net_map_at(inst
->GetCout()));
410 cell
= module
->addAdd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), a_plus_b
);
411 import_attributes(cell
->attributes
, inst
);
412 cell
= module
->addAdd(inst_name
, a_plus_b
, net_map_at(inst
->GetCin()), y
);
413 import_attributes(cell
->attributes
, inst
);
417 if (inst
->Type() == PRIM_DFFRS
)
419 VerificClocking
clocking(this, inst
->GetClock());
420 log_assert(clocking
.disable_sig
== State::S0
);
421 log_assert(clocking
.body_net
== nullptr);
423 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
424 cell
= clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
425 else if (inst
->GetSet()->IsGnd())
426 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
427 else if (inst
->GetReset()->IsGnd())
428 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
430 cell
= clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
431 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
432 import_attributes(cell
->attributes
, inst
);
436 if (inst
->Type() == PRIM_DLATCHRS
)
438 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
439 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
441 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
442 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
443 import_attributes(cell
->attributes
, inst
);
447 #define IN operatorInput(inst)
448 #define IN1 operatorInput1(inst)
449 #define IN2 operatorInput2(inst)
450 #define OUT operatorOutput(inst)
451 #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
452 #define SIGNED inst->View()->IsSigned()
454 if (inst
->Type() == OPER_ADDER
) {
455 RTLIL::SigSpec out
= OUT
;
456 if (inst
->GetCout() != NULL
)
457 out
.append(net_map_at(inst
->GetCout()));
458 if (inst
->GetCin()->IsGnd()) {
459 cell
= module
->addAdd(inst_name
, IN1
, IN2
, out
, SIGNED
);
460 import_attributes(cell
->attributes
, inst
);
462 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
), GetSize(out
));
463 cell
= module
->addAdd(new_verific_id(inst
), IN1
, IN2
, tmp
, SIGNED
);
464 import_attributes(cell
->attributes
, inst
);
465 cell
= module
->addAdd(inst_name
, tmp
, net_map_at(inst
->GetCin()), out
, false);
466 import_attributes(cell
->attributes
, inst
);
471 if (inst
->Type() == OPER_MULTIPLIER
) {
472 cell
= module
->addMul(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
473 import_attributes(cell
->attributes
, inst
);
477 if (inst
->Type() == OPER_DIVIDER
) {
478 cell
= module
->addDiv(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
479 import_attributes(cell
->attributes
, inst
);
483 if (inst
->Type() == OPER_MODULO
) {
484 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
485 import_attributes(cell
->attributes
, inst
);
489 if (inst
->Type() == OPER_REMAINDER
) {
490 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
491 import_attributes(cell
->attributes
, inst
);
495 if (inst
->Type() == OPER_SHIFT_LEFT
) {
496 cell
= module
->addShl(inst_name
, IN1
, IN2
, OUT
, false);
497 import_attributes(cell
->attributes
, inst
);
501 if (inst
->Type() == OPER_ENABLED_DECODER
) {
503 vec
.append(net_map_at(inst
->GetControl()));
504 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
505 vec
.append(RTLIL::State::S0
);
507 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
508 import_attributes(cell
->attributes
, inst
);
512 if (inst
->Type() == OPER_DECODER
) {
514 vec
.append(RTLIL::State::S1
);
515 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
516 vec
.append(RTLIL::State::S0
);
518 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
519 import_attributes(cell
->attributes
, inst
);
523 if (inst
->Type() == OPER_SHIFT_RIGHT
) {
524 Net
*net_cin
= inst
->GetCin();
525 Net
*net_a_msb
= inst
->GetInput1Bit(0);
526 if (net_cin
->IsGnd())
527 cell
= module
->addShr(inst_name
, IN1
, IN2
, OUT
, false);
528 else if (net_cin
== net_a_msb
)
529 cell
= module
->addSshr(inst_name
, IN1
, IN2
, OUT
, true);
531 log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst
->Name());
532 import_attributes(cell
->attributes
, inst
);
536 if (inst
->Type() == OPER_REDUCE_AND
) {
537 cell
= module
->addReduceAnd(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
538 import_attributes(cell
->attributes
, inst
);
542 if (inst
->Type() == OPER_REDUCE_NAND
) {
543 Wire
*tmp
= module
->addWire(NEW_ID
);
544 cell
= module
->addReduceAnd(inst_name
, IN
, tmp
, SIGNED
);
545 module
->addNot(NEW_ID
, tmp
, net_map_at(inst
->GetOutput()));
546 import_attributes(cell
->attributes
, inst
);
550 if (inst
->Type() == OPER_REDUCE_OR
) {
551 cell
= module
->addReduceOr(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
552 import_attributes(cell
->attributes
, inst
);
556 if (inst
->Type() == OPER_REDUCE_XOR
) {
557 cell
= module
->addReduceXor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
558 import_attributes(cell
->attributes
, inst
);
562 if (inst
->Type() == OPER_REDUCE_XNOR
) {
563 cell
= module
->addReduceXnor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
564 import_attributes(cell
->attributes
, inst
);
568 if (inst
->Type() == OPER_REDUCE_NOR
) {
569 SigSpec t
= module
->ReduceOr(new_verific_id(inst
), IN
, SIGNED
);
570 cell
= module
->addNot(inst_name
, t
, net_map_at(inst
->GetOutput()));
571 import_attributes(cell
->attributes
, inst
);
575 if (inst
->Type() == OPER_LESSTHAN
) {
576 Net
*net_cin
= inst
->GetCin();
577 if (net_cin
->IsGnd())
578 cell
= module
->addLt(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
579 else if (net_cin
->IsPwr())
580 cell
= module
->addLe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
582 log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst
->Name());
583 import_attributes(cell
->attributes
, inst
);
587 if (inst
->Type() == OPER_WIDE_AND
) {
588 cell
= module
->addAnd(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
589 import_attributes(cell
->attributes
, inst
);
593 if (inst
->Type() == OPER_WIDE_OR
) {
594 cell
= module
->addOr(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
595 import_attributes(cell
->attributes
, inst
);
599 if (inst
->Type() == OPER_WIDE_XOR
) {
600 cell
= module
->addXor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
601 import_attributes(cell
->attributes
, inst
);
605 if (inst
->Type() == OPER_WIDE_XNOR
) {
606 cell
= module
->addXnor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
607 import_attributes(cell
->attributes
, inst
);
611 if (inst
->Type() == OPER_WIDE_BUF
) {
612 cell
= module
->addPos(inst_name
, IN
, FILTERED_OUT
, SIGNED
);
613 import_attributes(cell
->attributes
, inst
);
617 if (inst
->Type() == OPER_WIDE_INV
) {
618 cell
= module
->addNot(inst_name
, IN
, OUT
, SIGNED
);
619 import_attributes(cell
->attributes
, inst
);
623 if (inst
->Type() == OPER_MINUS
) {
624 cell
= module
->addSub(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
625 import_attributes(cell
->attributes
, inst
);
629 if (inst
->Type() == OPER_UMINUS
) {
630 cell
= module
->addNeg(inst_name
, IN
, OUT
, SIGNED
);
631 import_attributes(cell
->attributes
, inst
);
635 if (inst
->Type() == OPER_EQUAL
) {
636 cell
= module
->addEq(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
637 import_attributes(cell
->attributes
, inst
);
641 if (inst
->Type() == OPER_NEQUAL
) {
642 cell
= module
->addNe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
643 import_attributes(cell
->attributes
, inst
);
647 if (inst
->Type() == OPER_WIDE_MUX
) {
648 cell
= module
->addMux(inst_name
, IN1
, IN2
, net_map_at(inst
->GetControl()), OUT
);
649 import_attributes(cell
->attributes
, inst
);
653 if (inst
->Type() == OPER_NTO1MUX
) {
654 cell
= module
->addShr(inst_name
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
655 import_attributes(cell
->attributes
, inst
);
659 if (inst
->Type() == OPER_WIDE_NTO1MUX
)
661 SigSpec data
= IN2
, out
= OUT
;
663 int wordsize_bits
= ceil_log2(GetSize(out
));
664 int wordsize
= 1 << wordsize_bits
;
666 SigSpec sel
= {IN1
, SigSpec(State::S0
, wordsize_bits
)};
669 for (int i
= 0; i
< GetSize(data
); i
+= GetSize(out
)) {
670 SigSpec d
= data
.extract(i
, GetSize(out
));
671 d
.extend_u0(wordsize
);
672 padded_data
.append(d
);
675 cell
= module
->addShr(inst_name
, padded_data
, sel
, out
);
676 import_attributes(cell
->attributes
, inst
);
680 if (inst
->Type() == OPER_SELECTOR
)
682 cell
= module
->addPmux(inst_name
, State::S0
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
683 import_attributes(cell
->attributes
, inst
);
687 if (inst
->Type() == OPER_WIDE_SELECTOR
)
690 cell
= module
->addPmux(inst_name
, SigSpec(State::S0
, GetSize(out
)), IN2
, IN1
, out
);
691 import_attributes(cell
->attributes
, inst
);
695 if (inst
->Type() == OPER_WIDE_TRI
) {
696 cell
= module
->addMux(inst_name
, RTLIL::SigSpec(RTLIL::State::Sz
, inst
->OutputSize()), IN
, net_map_at(inst
->GetControl()), OUT
);
697 import_attributes(cell
->attributes
, inst
);
701 if (inst
->Type() == OPER_WIDE_DFFRS
)
703 VerificClocking
clocking(this, inst
->GetClock());
704 log_assert(clocking
.disable_sig
== State::S0
);
705 log_assert(clocking
.body_net
== nullptr);
707 RTLIL::SigSpec sig_set
= operatorInport(inst
, "set");
708 RTLIL::SigSpec sig_reset
= operatorInport(inst
, "reset");
710 if (sig_set
.is_fully_const() && !sig_set
.as_bool() && sig_reset
.is_fully_const() && !sig_reset
.as_bool())
711 cell
= clocking
.addDff(inst_name
, IN
, OUT
);
713 cell
= clocking
.addDffsr(inst_name
, sig_set
, sig_reset
, IN
, OUT
);
714 import_attributes(cell
->attributes
, inst
);
728 void VerificImporter::merge_past_ffs_clock(pool
<RTLIL::Cell
*> &candidates
, SigBit clock
, bool clock_pol
)
730 bool keep_running
= true;
735 keep_running
= false;
737 dict
<SigBit
, pool
<RTLIL::Cell
*>> dbits_db
;
740 for (auto cell
: candidates
) {
741 SigBit bit
= sigmap(cell
->getPort("\\D"));
742 dbits_db
[bit
].insert(cell
);
746 dbits
.sort_and_unify();
748 for (auto chunk
: dbits
.chunks())
750 SigSpec sig_d
= chunk
;
752 if (chunk
.wire
== nullptr || GetSize(sig_d
) == 1)
755 SigSpec sig_q
= module
->addWire(NEW_ID
, GetSize(sig_d
));
756 RTLIL::Cell
*new_ff
= module
->addDff(NEW_ID
, clock
, sig_d
, sig_q
, clock_pol
);
759 log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d
), log_id(new_ff
));
761 for (int i
= 0; i
< GetSize(sig_d
); i
++)
762 for (auto old_ff
: dbits_db
[sig_d
[i
]])
765 log(" replacing old ff %s on bit %d.\n", log_id(old_ff
), i
);
767 SigBit old_q
= old_ff
->getPort("\\Q");
768 SigBit new_q
= sig_q
[i
];
770 sigmap
.add(old_q
, new_q
);
771 module
->connect(old_q
, new_q
);
772 candidates
.erase(old_ff
);
773 module
->remove(old_ff
);
780 void VerificImporter::merge_past_ffs(pool
<RTLIL::Cell
*> &candidates
)
782 dict
<pair
<SigBit
, int>, pool
<RTLIL::Cell
*>> database
;
784 for (auto cell
: candidates
)
786 SigBit clock
= cell
->getPort("\\CLK");
787 bool clock_pol
= cell
->getParam("\\CLK_POLARITY").as_bool();
788 database
[make_pair(clock
, int(clock_pol
))].insert(cell
);
791 for (auto it
: database
)
792 merge_past_ffs_clock(it
.second
, it
.first
.first
, it
.first
.second
);
795 void VerificImporter::import_netlist(RTLIL::Design
*design
, Netlist
*nl
, std::set
<Netlist
*> &nl_todo
, bool norename
)
797 std::string netlist_name
= nl
->GetAtt(" \\top") ? nl
->CellBaseName() : nl
->Owner()->Name();
798 std::string module_name
= netlist_name
;
800 if (nl
->IsOperator() || nl
->IsPrimitive()) {
801 module_name
= "$verific$" + module_name
;
803 if (!norename
&& *nl
->Name()) {
805 module_name
+= nl
->Name();
808 module_name
= "\\" + module_name
;
813 if (design
->has(module_name
)) {
814 if (!nl
->IsOperator() && !is_blackbox(nl
))
815 log_cmd_error("Re-definition of module `%s'.\n", netlist_name
.c_str());
819 module
= new RTLIL::Module
;
820 module
->name
= module_name
;
823 if (is_blackbox(nl
)) {
824 log("Importing blackbox module %s.\n", RTLIL::id2cstr(module
->name
));
825 module
->set_bool_attribute("\\blackbox");
827 log("Importing module %s.\n", RTLIL::id2cstr(module
->name
));
839 FOREACH_PORT_OF_NETLIST(nl
, mi
, port
)
845 log(" importing port %s.\n", port
->Name());
847 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(port
->Name()));
848 import_attributes(wire
->attributes
, port
);
850 wire
->port_id
= nl
->IndexOf(port
) + 1;
852 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_IN
)
853 wire
->port_input
= true;
854 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_OUT
)
855 wire
->port_output
= true;
857 if (port
->GetNet()) {
858 net
= port
->GetNet();
859 if (net_map
.count(net
) == 0)
861 else if (wire
->port_input
)
862 module
->connect(net_map_at(net
), wire
);
864 module
->connect(wire
, net_map_at(net
));
868 FOREACH_PORTBUS_OF_NETLIST(nl
, mi
, portbus
)
871 log(" importing portbus %s.\n", portbus
->Name());
873 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(portbus
->Name()), portbus
->Size());
874 wire
->start_offset
= min(portbus
->LeftIndex(), portbus
->RightIndex());
875 import_attributes(wire
->attributes
, portbus
);
877 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_IN
)
878 wire
->port_input
= true;
879 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_OUT
)
880 wire
->port_output
= true;
882 for (int i
= portbus
->LeftIndex();; i
+= portbus
->IsUp() ? +1 : -1) {
883 if (portbus
->ElementAtIndex(i
) && portbus
->ElementAtIndex(i
)->GetNet()) {
884 net
= portbus
->ElementAtIndex(i
)->GetNet();
885 RTLIL::SigBit
bit(wire
, i
- wire
->start_offset
);
886 if (net_map
.count(net
) == 0)
888 else if (wire
->port_input
)
889 module
->connect(net_map_at(net
), bit
);
891 module
->connect(bit
, net_map_at(net
));
893 if (i
== portbus
->RightIndex())
898 module
->fixup_ports();
900 dict
<Net
*, char, hash_ptr_ops
> init_nets
;
901 pool
<Net
*, hash_ptr_ops
> anyconst_nets
, anyseq_nets
;
902 pool
<Net
*, hash_ptr_ops
> allconst_nets
, allseq_nets
;
903 any_all_nets
.clear();
905 FOREACH_NET_OF_NETLIST(nl
, mi
, net
)
909 RTLIL::Memory
*memory
= new RTLIL::Memory
;
910 memory
->name
= RTLIL::escape_id(net
->Name());
911 log_assert(module
->count_id(memory
->name
) == 0);
912 module
->memories
[memory
->name
] = memory
;
914 int number_of_bits
= net
->Size();
915 int bits_in_word
= number_of_bits
;
916 FOREACH_PORTREF_OF_NET(net
, si
, pr
) {
917 if (pr
->GetInst()->Type() == OPER_READ_PORT
) {
918 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->OutputSize());
921 if (pr
->GetInst()->Type() == OPER_WRITE_PORT
|| pr
->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT
) {
922 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->Input2Size());
925 log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
926 net
->Name(), pr
->GetInst()->View()->Owner()->Name(), pr
->GetInst()->Name());
929 memory
->width
= bits_in_word
;
930 memory
->size
= number_of_bits
/ bits_in_word
;
932 const char *ascii_initdata
= net
->GetWideInitialValue();
933 if (ascii_initdata
) {
934 while (*ascii_initdata
!= 0 && *ascii_initdata
!= '\'')
936 if (*ascii_initdata
== '\'')
938 if (*ascii_initdata
!= 0) {
939 log_assert(*ascii_initdata
== 'b');
942 for (int word_idx
= 0; word_idx
< memory
->size
; word_idx
++) {
943 Const initval
= Const(State::Sx
, memory
->width
);
944 bool initval_valid
= false;
945 for (int bit_idx
= memory
->width
-1; bit_idx
>= 0; bit_idx
--) {
946 if (*ascii_initdata
== 0)
948 if (*ascii_initdata
== '0' || *ascii_initdata
== '1') {
949 initval
[bit_idx
] = (*ascii_initdata
== '0') ? State::S0
: State::S1
;
950 initval_valid
= true;
955 RTLIL::Cell
*cell
= module
->addCell(new_verific_id(net
), "$meminit");
956 cell
->parameters
["\\WORDS"] = 1;
957 if (net
->GetOrigTypeRange()->LeftRangeBound() < net
->GetOrigTypeRange()->RightRangeBound())
958 cell
->setPort("\\ADDR", word_idx
);
960 cell
->setPort("\\ADDR", memory
->size
- word_idx
- 1);
961 cell
->setPort("\\DATA", initval
);
962 cell
->parameters
["\\MEMID"] = RTLIL::Const(memory
->name
.str());
963 cell
->parameters
["\\ABITS"] = 32;
964 cell
->parameters
["\\WIDTH"] = memory
->width
;
965 cell
->parameters
["\\PRIORITY"] = RTLIL::Const(autoidx
-1);
972 if (net
->GetInitialValue())
973 init_nets
[net
] = net
->GetInitialValue();
975 const char *rand_const_attr
= net
->GetAttValue(" rand_const");
976 const char *rand_attr
= net
->GetAttValue(" rand");
978 const char *anyconst_attr
= net
->GetAttValue("anyconst");
979 const char *anyseq_attr
= net
->GetAttValue("anyseq");
981 const char *allconst_attr
= net
->GetAttValue("allconst");
982 const char *allseq_attr
= net
->GetAttValue("allseq");
984 if (rand_const_attr
!= nullptr && (!strcmp(rand_const_attr
, "1") || !strcmp(rand_const_attr
, "'1'"))) {
985 anyconst_nets
.insert(net
);
986 any_all_nets
.insert(net
);
988 else if (rand_attr
!= nullptr && (!strcmp(rand_attr
, "1") || !strcmp(rand_attr
, "'1'"))) {
989 anyseq_nets
.insert(net
);
990 any_all_nets
.insert(net
);
992 else if (anyconst_attr
!= nullptr && (!strcmp(anyconst_attr
, "1") || !strcmp(anyconst_attr
, "'1'"))) {
993 anyconst_nets
.insert(net
);
994 any_all_nets
.insert(net
);
996 else if (anyseq_attr
!= nullptr && (!strcmp(anyseq_attr
, "1") || !strcmp(anyseq_attr
, "'1'"))) {
997 anyseq_nets
.insert(net
);
998 any_all_nets
.insert(net
);
1000 else if (allconst_attr
!= nullptr && (!strcmp(allconst_attr
, "1") || !strcmp(allconst_attr
, "'1'"))) {
1001 allconst_nets
.insert(net
);
1002 any_all_nets
.insert(net
);
1004 else if (allseq_attr
!= nullptr && (!strcmp(allseq_attr
, "1") || !strcmp(allseq_attr
, "'1'"))) {
1005 allseq_nets
.insert(net
);
1006 any_all_nets
.insert(net
);
1009 if (net_map
.count(net
)) {
1010 if (verific_verbose
)
1011 log(" skipping net %s.\n", net
->Name());
1018 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| net
->IsUserDeclared() ? RTLIL::escape_id(net
->Name()) : new_verific_id(net
));
1020 if (verific_verbose
)
1021 log(" importing net %s as %s.\n", net
->Name(), log_id(wire_name
));
1023 RTLIL::Wire
*wire
= module
->addWire(wire_name
);
1024 import_attributes(wire
->attributes
, net
);
1026 net_map
[net
] = wire
;
1029 FOREACH_NETBUS_OF_NETLIST(nl
, mi
, netbus
)
1031 bool found_new_net
= false;
1032 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1) {
1033 net
= netbus
->ElementAtIndex(i
);
1034 if (net_map
.count(net
) == 0)
1035 found_new_net
= true;
1036 if (i
== netbus
->RightIndex())
1042 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| netbus
->IsUserDeclared() ? RTLIL::escape_id(netbus
->Name()) : new_verific_id(netbus
));
1044 if (verific_verbose
)
1045 log(" importing netbus %s as %s.\n", netbus
->Name(), log_id(wire_name
));
1047 RTLIL::Wire
*wire
= module
->addWire(wire_name
, netbus
->Size());
1048 wire
->start_offset
= min(netbus
->LeftIndex(), netbus
->RightIndex());
1049 import_attributes(wire
->attributes
, netbus
);
1051 RTLIL::Const initval
= Const(State::Sx
, GetSize(wire
));
1052 bool initval_valid
= false;
1054 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1)
1056 if (netbus
->ElementAtIndex(i
))
1058 int bitidx
= i
- wire
->start_offset
;
1059 net
= netbus
->ElementAtIndex(i
);
1060 RTLIL::SigBit
bit(wire
, bitidx
);
1062 if (init_nets
.count(net
)) {
1063 if (init_nets
.at(net
) == '0')
1064 initval
.bits
.at(bitidx
) = State::S0
;
1065 if (init_nets
.at(net
) == '1')
1066 initval
.bits
.at(bitidx
) = State::S1
;
1067 initval_valid
= true;
1068 init_nets
.erase(net
);
1071 if (net_map
.count(net
) == 0)
1074 module
->connect(bit
, net_map_at(net
));
1077 if (i
== netbus
->RightIndex())
1082 wire
->attributes
["\\init"] = initval
;
1086 if (verific_verbose
)
1087 log(" skipping netbus %s.\n", netbus
->Name());
1090 SigSpec anyconst_sig
;
1092 SigSpec allconst_sig
;
1095 for (int i
= netbus
->RightIndex();; i
+= netbus
->IsUp() ? -1 : +1) {
1096 net
= netbus
->ElementAtIndex(i
);
1097 if (net
!= nullptr && anyconst_nets
.count(net
)) {
1098 anyconst_sig
.append(net_map_at(net
));
1099 anyconst_nets
.erase(net
);
1101 if (net
!= nullptr && anyseq_nets
.count(net
)) {
1102 anyseq_sig
.append(net_map_at(net
));
1103 anyseq_nets
.erase(net
);
1105 if (net
!= nullptr && allconst_nets
.count(net
)) {
1106 allconst_sig
.append(net_map_at(net
));
1107 allconst_nets
.erase(net
);
1109 if (net
!= nullptr && allseq_nets
.count(net
)) {
1110 allseq_sig
.append(net_map_at(net
));
1111 allseq_nets
.erase(net
);
1113 if (i
== netbus
->LeftIndex())
1117 if (GetSize(anyconst_sig
))
1118 module
->connect(anyconst_sig
, module
->Anyconst(new_verific_id(netbus
), GetSize(anyconst_sig
)));
1120 if (GetSize(anyseq_sig
))
1121 module
->connect(anyseq_sig
, module
->Anyseq(new_verific_id(netbus
), GetSize(anyseq_sig
)));
1123 if (GetSize(allconst_sig
))
1124 module
->connect(allconst_sig
, module
->Allconst(new_verific_id(netbus
), GetSize(allconst_sig
)));
1126 if (GetSize(allseq_sig
))
1127 module
->connect(allseq_sig
, module
->Allseq(new_verific_id(netbus
), GetSize(allseq_sig
)));
1130 for (auto it
: init_nets
)
1133 SigBit bit
= net_map_at(it
.first
);
1134 log_assert(bit
.wire
);
1136 if (bit
.wire
->attributes
.count("\\init"))
1137 initval
= bit
.wire
->attributes
.at("\\init");
1139 while (GetSize(initval
) < GetSize(bit
.wire
))
1140 initval
.bits
.push_back(State::Sx
);
1142 if (it
.second
== '0')
1143 initval
.bits
.at(bit
.offset
) = State::S0
;
1144 if (it
.second
== '1')
1145 initval
.bits
.at(bit
.offset
) = State::S1
;
1147 bit
.wire
->attributes
["\\init"] = initval
;
1150 for (auto net
: anyconst_nets
)
1151 module
->connect(net_map_at(net
), module
->Anyconst(new_verific_id(net
)));
1153 for (auto net
: anyseq_nets
)
1154 module
->connect(net_map_at(net
), module
->Anyseq(new_verific_id(net
)));
1156 pool
<Instance
*, hash_ptr_ops
> sva_asserts
;
1157 pool
<Instance
*, hash_ptr_ops
> sva_assumes
;
1158 pool
<Instance
*, hash_ptr_ops
> sva_covers
;
1159 pool
<Instance
*, hash_ptr_ops
> sva_triggers
;
1161 pool
<RTLIL::Cell
*> past_ffs
;
1163 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1165 RTLIL::IdString inst_name
= module
->uniquify(mode_names
|| inst
->IsUserDeclared() ? RTLIL::escape_id(inst
->Name()) : new_verific_id(inst
));
1167 if (verific_verbose
)
1168 log(" importing cell %s (%s) as %s.\n", inst
->Name(), inst
->View()->Owner()->Name(), log_id(inst_name
));
1171 goto import_verific_cells
;
1173 if (inst
->Type() == PRIM_PWR
) {
1174 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
1178 if (inst
->Type() == PRIM_GND
) {
1179 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
1183 if (inst
->Type() == PRIM_BUF
) {
1184 auto outnet
= inst
->GetOutput();
1185 if (!any_all_nets
.count(outnet
))
1186 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
1190 if (inst
->Type() == PRIM_X
) {
1191 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sx
);
1195 if (inst
->Type() == PRIM_Z
) {
1196 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sz
);
1200 if (inst
->Type() == OPER_READ_PORT
)
1202 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetInput()->Name()));
1203 int numchunks
= int(inst
->OutputSize()) / memory
->width
;
1204 int chunksbits
= ceil_log2(numchunks
);
1206 if ((numchunks
* memory
->width
) != int(inst
->OutputSize()) || (numchunks
& (numchunks
- 1)) != 0)
1207 log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst
->Name(), inst
->GetInput()->Name());
1209 for (int i
= 0; i
< numchunks
; i
++)
1211 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1212 RTLIL::SigSpec data
= operatorOutput(inst
).extract(i
* memory
->width
, memory
->width
);
1214 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1215 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), "$memrd");
1216 cell
->parameters
["\\MEMID"] = memory
->name
.str();
1217 cell
->parameters
["\\CLK_ENABLE"] = false;
1218 cell
->parameters
["\\CLK_POLARITY"] = true;
1219 cell
->parameters
["\\TRANSPARENT"] = false;
1220 cell
->parameters
["\\ABITS"] = GetSize(addr
);
1221 cell
->parameters
["\\WIDTH"] = GetSize(data
);
1222 cell
->setPort("\\CLK", RTLIL::State::Sx
);
1223 cell
->setPort("\\EN", RTLIL::State::Sx
);
1224 cell
->setPort("\\ADDR", addr
);
1225 cell
->setPort("\\DATA", data
);
1230 if (inst
->Type() == OPER_WRITE_PORT
|| inst
->Type() == OPER_CLOCKED_WRITE_PORT
)
1232 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetOutput()->Name()));
1233 int numchunks
= int(inst
->Input2Size()) / memory
->width
;
1234 int chunksbits
= ceil_log2(numchunks
);
1236 if ((numchunks
* memory
->width
) != int(inst
->Input2Size()) || (numchunks
& (numchunks
- 1)) != 0)
1237 log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst
->Name(), inst
->GetOutput()->Name());
1239 for (int i
= 0; i
< numchunks
; i
++)
1241 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1242 RTLIL::SigSpec data
= operatorInput2(inst
).extract(i
* memory
->width
, memory
->width
);
1244 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1245 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), "$memwr");
1246 cell
->parameters
["\\MEMID"] = memory
->name
.str();
1247 cell
->parameters
["\\CLK_ENABLE"] = false;
1248 cell
->parameters
["\\CLK_POLARITY"] = true;
1249 cell
->parameters
["\\PRIORITY"] = 0;
1250 cell
->parameters
["\\ABITS"] = GetSize(addr
);
1251 cell
->parameters
["\\WIDTH"] = GetSize(data
);
1252 cell
->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst
->GetControl())).repeat(GetSize(data
)));
1253 cell
->setPort("\\CLK", RTLIL::State::S0
);
1254 cell
->setPort("\\ADDR", addr
);
1255 cell
->setPort("\\DATA", data
);
1257 if (inst
->Type() == OPER_CLOCKED_WRITE_PORT
) {
1258 cell
->parameters
["\\CLK_ENABLE"] = true;
1259 cell
->setPort("\\CLK", net_map_at(inst
->GetClock()));
1266 if (import_netlist_instance_cells(inst
, inst_name
))
1268 if (inst
->IsOperator() && !verific_sva_prims
.count(inst
->Type()))
1269 log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst
->View()->Owner()->Name());
1271 if (import_netlist_instance_gates(inst
, inst_name
))
1275 if (inst
->Type() == PRIM_SVA_ASSERT
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSERT
)
1276 sva_asserts
.insert(inst
);
1278 if (inst
->Type() == PRIM_SVA_ASSUME
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSUME
|| inst
->Type() == PRIM_SVA_RESTRICT
)
1279 sva_assumes
.insert(inst
);
1281 if (inst
->Type() == PRIM_SVA_COVER
|| inst
->Type() == PRIM_SVA_IMMEDIATE_COVER
)
1282 sva_covers
.insert(inst
);
1284 if (inst
->Type() == PRIM_SVA_TRIGGERED
)
1285 sva_triggers
.insert(inst
);
1287 if (inst
->Type() == OPER_SVA_STABLE
)
1289 VerificClocking
clocking(this, inst
->GetInput2Bit(0));
1290 log_assert(clocking
.disable_sig
== State::S0
);
1291 log_assert(clocking
.body_net
== nullptr);
1293 log_assert(inst
->Input1Size() == inst
->OutputSize());
1295 SigSpec sig_d
, sig_q
, sig_o
;
1296 sig_q
= module
->addWire(new_verific_id(inst
), inst
->Input1Size());
1298 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--){
1299 sig_d
.append(net_map_at(inst
->GetInput1Bit(i
)));
1300 sig_o
.append(net_map_at(inst
->GetOutputBit(i
)));
1303 if (verific_verbose
) {
1304 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1305 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1306 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1307 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1310 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1311 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1317 if (inst
->Type() == PRIM_SVA_STABLE
)
1319 VerificClocking
clocking(this, inst
->GetInput2());
1320 log_assert(clocking
.disable_sig
== State::S0
);
1321 log_assert(clocking
.body_net
== nullptr);
1323 SigSpec sig_d
= net_map_at(inst
->GetInput1());
1324 SigSpec sig_o
= net_map_at(inst
->GetOutput());
1325 SigSpec sig_q
= module
->addWire(new_verific_id(inst
));
1327 if (verific_verbose
) {
1328 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1329 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1330 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1331 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1334 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1335 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1341 if (inst
->Type() == PRIM_SVA_PAST
)
1343 VerificClocking
clocking(this, inst
->GetInput2());
1344 log_assert(clocking
.disable_sig
== State::S0
);
1345 log_assert(clocking
.body_net
== nullptr);
1347 SigBit sig_d
= net_map_at(inst
->GetInput1());
1348 SigBit sig_q
= net_map_at(inst
->GetOutput());
1350 if (verific_verbose
)
1351 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1352 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1354 past_ffs
.insert(clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
));
1360 if ((inst
->Type() == PRIM_SVA_ROSE
|| inst
->Type() == PRIM_SVA_FELL
))
1362 VerificClocking
clocking(this, inst
->GetInput2());
1363 log_assert(clocking
.disable_sig
== State::S0
);
1364 log_assert(clocking
.body_net
== nullptr);
1366 SigBit sig_d
= net_map_at(inst
->GetInput1());
1367 SigBit sig_o
= net_map_at(inst
->GetOutput());
1368 SigBit sig_q
= module
->addWire(new_verific_id(inst
));
1370 if (verific_verbose
)
1371 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1372 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1374 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1375 module
->addEq(new_verific_id(inst
), {sig_q
, sig_d
}, Const(inst
->Type() == PRIM_SVA_ROSE
? 1 : 2, 2), sig_o
);
1381 if (!mode_keep
&& verific_sva_prims
.count(inst
->Type())) {
1382 if (verific_verbose
)
1383 log(" skipping SVA cell in non k-mode\n");
1387 if (inst
->Type() == PRIM_HDL_ASSERTION
)
1389 SigBit cond
= net_map_at(inst
->GetInput());
1391 if (verific_verbose
)
1392 log(" assert condition %s.\n", log_signal(cond
));
1394 const char *assume_attr
= nullptr; // inst->GetAttValue("assume");
1396 Cell
*cell
= nullptr;
1397 if (assume_attr
!= nullptr && !strcmp(assume_attr
, "1"))
1398 cell
= module
->addAssume(new_verific_id(inst
), cond
, State::S1
);
1400 cell
= module
->addAssert(new_verific_id(inst
), cond
, State::S1
);
1402 import_attributes(cell
->attributes
, inst
);
1406 if (inst
->IsPrimitive())
1409 log_error("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1411 if (!verific_sva_prims
.count(inst
->Type()))
1412 log_warning("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1415 import_verific_cells
:
1416 nl_todo
.insert(inst
->View());
1418 std::string inst_type
= inst
->View()->Owner()->Name();
1420 if (inst
->View()->IsOperator() || inst
->View()->IsPrimitive()) {
1421 inst_type
= "$verific$" + inst_type
;
1423 if (*inst
->View()->Name()) {
1425 inst_type
+= inst
->View()->Name();
1428 inst_type
= "\\" + inst_type
;
1431 RTLIL::Cell
*cell
= module
->addCell(inst_name
, inst_type
);
1433 if (inst
->IsPrimitive() && mode_keep
)
1434 cell
->attributes
["\\keep"] = 1;
1436 dict
<IdString
, vector
<SigBit
>> cell_port_conns
;
1438 if (verific_verbose
)
1439 log(" ports in verific db:\n");
1441 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
) {
1442 if (verific_verbose
)
1443 log(" .%s(%s)\n", pr
->GetPort()->Name(), pr
->GetNet()->Name());
1444 const char *port_name
= pr
->GetPort()->Name();
1445 int port_offset
= 0;
1446 if (pr
->GetPort()->Bus()) {
1447 port_name
= pr
->GetPort()->Bus()->Name();
1448 port_offset
= pr
->GetPort()->Bus()->IndexOf(pr
->GetPort()) -
1449 min(pr
->GetPort()->Bus()->LeftIndex(), pr
->GetPort()->Bus()->RightIndex());
1451 IdString port_name_id
= RTLIL::escape_id(port_name
);
1452 auto &sigvec
= cell_port_conns
[port_name_id
];
1453 if (GetSize(sigvec
) <= port_offset
) {
1454 SigSpec zwires
= module
->addWire(new_verific_id(inst
), port_offset
+1-GetSize(sigvec
));
1455 for (auto bit
: zwires
)
1456 sigvec
.push_back(bit
);
1458 sigvec
[port_offset
] = net_map_at(pr
->GetNet());
1461 if (verific_verbose
)
1462 log(" ports in yosys db:\n");
1464 for (auto &it
: cell_port_conns
) {
1465 if (verific_verbose
)
1466 log(" .%s(%s)\n", log_id(it
.first
), log_signal(it
.second
));
1467 cell
->setPort(it
.first
, it
.second
);
1473 for (auto inst
: sva_asserts
) {
1475 verific_import_sva_cover(this, inst
);
1476 verific_import_sva_assert(this, inst
);
1479 for (auto inst
: sva_assumes
)
1480 verific_import_sva_assume(this, inst
);
1482 for (auto inst
: sva_covers
)
1483 verific_import_sva_cover(this, inst
);
1485 for (auto inst
: sva_triggers
)
1486 verific_import_sva_trigger(this, inst
);
1488 merge_past_ffs(past_ffs
);
1493 pool
<SigBit
> non_ff_bits
;
1496 ff_types
.setup_internals_ff();
1497 ff_types
.setup_stdcells_mem();
1499 for (auto cell
: module
->cells())
1501 if (ff_types
.cell_known(cell
->type
))
1504 for (auto conn
: cell
->connections())
1506 if (!cell
->output(conn
.first
))
1509 for (auto bit
: conn
.second
)
1510 if (bit
.wire
!= nullptr)
1511 non_ff_bits
.insert(bit
);
1515 for (auto wire
: module
->wires())
1517 if (!wire
->attributes
.count("\\init"))
1520 Const
&initval
= wire
->attributes
.at("\\init");
1521 for (int i
= 0; i
< GetSize(initval
); i
++)
1523 if (initval
[i
] != State::S0
&& initval
[i
] != State::S1
)
1526 if (non_ff_bits
.count(SigBit(wire
, i
)))
1527 initval
[i
] = State::Sx
;
1530 if (initval
.is_fully_undef())
1531 wire
->attributes
.erase("\\init");
1536 // ==================================================================
1538 VerificClocking::VerificClocking(VerificImporter
*importer
, Net
*net
, bool sva_at_only
)
1540 module
= importer
->module
;
1542 log_assert(importer
!= nullptr);
1543 log_assert(net
!= nullptr);
1545 Instance
*inst
= net
->Driver();
1547 if (inst
!= nullptr && inst
->Type() == PRIM_SVA_AT
)
1549 net
= inst
->GetInput1();
1550 body_net
= inst
->GetInput2();
1552 inst
= net
->Driver();
1554 Instance
*body_inst
= body_net
->Driver();
1555 if (body_inst
!= nullptr && body_inst
->Type() == PRIM_SVA_DISABLE_IFF
) {
1556 disable_net
= body_inst
->GetInput1();
1557 disable_sig
= importer
->net_map_at(disable_net
);
1558 body_net
= body_inst
->GetInput2();
1567 // Use while() instead of if() to work around VIPER #13453
1568 while (inst
!= nullptr && inst
->Type() == PRIM_SVA_POSEDGE
)
1570 net
= inst
->GetInput();
1571 inst
= net
->Driver();;
1574 if (inst
!= nullptr && inst
->Type() == PRIM_INV
)
1576 net
= inst
->GetInput();
1577 inst
= net
->Driver();;
1581 // Detect clock-enable circuit
1583 if (inst
== nullptr || inst
->Type() != PRIM_AND
)
1586 Net
*net_dlatch
= inst
->GetInput1();
1587 Instance
*inst_dlatch
= net_dlatch
->Driver();
1589 if (inst_dlatch
== nullptr || inst_dlatch
->Type() != PRIM_DLATCHRS
)
1592 if (!inst_dlatch
->GetSet()->IsGnd() || !inst_dlatch
->GetReset()->IsGnd())
1595 Net
*net_enable
= inst_dlatch
->GetInput();
1596 Net
*net_not_clock
= inst_dlatch
->GetControl();
1598 if (net_enable
== nullptr || net_not_clock
== nullptr)
1601 Instance
*inst_not_clock
= net_not_clock
->Driver();
1603 if (inst_not_clock
== nullptr || inst_not_clock
->Type() != PRIM_INV
)
1606 Net
*net_clock1
= inst_not_clock
->GetInput();
1607 Net
*net_clock2
= inst
->GetInput2();
1609 if (net_clock1
== nullptr || net_clock1
!= net_clock2
)
1612 enable_net
= net_enable
;
1613 enable_sig
= importer
->net_map_at(enable_net
);
1616 inst
= net
->Driver();;
1619 // Detect condition expression
1621 if (body_net
== nullptr)
1624 Instance
*inst_mux
= body_net
->Driver();
1626 if (inst_mux
== nullptr || inst_mux
->Type() != PRIM_MUX
)
1629 if (!inst_mux
->GetInput1()->IsPwr())
1632 Net
*sva_net
= inst_mux
->GetInput2();
1633 if (!verific_is_sva_net(importer
, sva_net
))
1637 cond_net
= inst_mux
->GetControl();
1641 clock_sig
= importer
->net_map_at(clock_net
);
1643 const char *gclk_attr
= clock_net
->GetAttValue("gclk");
1644 if (gclk_attr
!= nullptr && (!strcmp(gclk_attr
, "1") || !strcmp(gclk_attr
, "'1'")))
1648 Cell
*VerificClocking::addDff(IdString name
, SigSpec sig_d
, SigSpec sig_q
, Const init_value
)
1650 log_assert(GetSize(sig_d
) == GetSize(sig_q
));
1652 if (GetSize(init_value
) != 0) {
1653 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1654 if (sig_q
.is_wire()) {
1655 sig_q
.as_wire()->attributes
["\\init"] = init_value
;
1657 Wire
*w
= module
->addWire(NEW_ID
, GetSize(sig_q
));
1658 w
->attributes
["\\init"] = init_value
;
1659 module
->connect(sig_q
, w
);
1664 if (enable_sig
!= State::S1
)
1665 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1667 if (disable_sig
!= State::S0
) {
1668 log_assert(gclk
== false);
1669 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1670 return module
->addAdff(name
, clock_sig
, disable_sig
, sig_d
, sig_q
, init_value
, posedge
);
1674 return module
->addFf(name
, sig_d
, sig_q
);
1676 return module
->addDff(name
, clock_sig
, sig_d
, sig_q
, posedge
);
1679 Cell
*VerificClocking::addAdff(IdString name
, RTLIL::SigSpec sig_arst
, SigSpec sig_d
, SigSpec sig_q
, Const arst_value
)
1681 log_assert(gclk
== false);
1682 log_assert(disable_sig
== State::S0
);
1684 if (enable_sig
!= State::S1
)
1685 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1687 return module
->addAdff(name
, clock_sig
, sig_arst
, sig_d
, sig_q
, arst_value
, posedge
);
1690 Cell
*VerificClocking::addDffsr(IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, SigSpec sig_d
, SigSpec sig_q
)
1692 log_assert(gclk
== false);
1693 log_assert(disable_sig
== State::S0
);
1695 if (enable_sig
!= State::S1
)
1696 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1698 return module
->addDffsr(name
, clock_sig
, sig_set
, sig_clr
, sig_d
, sig_q
, posedge
);
1701 // ==================================================================
1703 struct VerificExtNets
1705 int portname_cnt
= 0;
1707 // a map from Net to the same Net one level up in the design hierarchy
1708 std::map
<Net
*, Net
*> net_level_up_drive_up
;
1709 std::map
<Net
*, Net
*> net_level_up_drive_down
;
1711 Net
*route_up(Net
*net
, bool drive_up
, Net
*final_net
= nullptr)
1713 auto &net_level_up
= drive_up
? net_level_up_drive_up
: net_level_up_drive_down
;
1715 if (net_level_up
.count(net
) == 0)
1717 Netlist
*nl
= net
->Owner();
1719 // Simply return if Netlist is not unique
1720 log_assert(nl
->NumOfRefs() == 1);
1722 Instance
*up_inst
= (Instance
*)nl
->GetReferences()->GetLast();
1723 Netlist
*up_nl
= up_inst
->Owner();
1726 string name
= stringf("___extnets_%d", portname_cnt
++);
1727 Port
*new_port
= new Port(name
.c_str(), drive_up
? DIR_OUT
: DIR_IN
);
1729 net
->Connect(new_port
);
1731 // create new Net in up Netlist
1732 Net
*new_net
= final_net
;
1733 if (new_net
== nullptr || new_net
->Owner() != up_nl
) {
1734 new_net
= new Net(name
.c_str());
1735 up_nl
->Add(new_net
);
1737 up_inst
->Connect(new_port
, new_net
);
1739 net_level_up
[net
] = new_net
;
1742 return net_level_up
.at(net
);
1745 Net
*route_up(Net
*net
, bool drive_up
, Netlist
*dest
, Net
*final_net
= nullptr)
1747 while (net
->Owner() != dest
)
1748 net
= route_up(net
, drive_up
, final_net
);
1749 if (final_net
!= nullptr)
1750 log_assert(net
== final_net
);
1754 Netlist
*find_common_ancestor(Netlist
*A
, Netlist
*B
)
1756 std::set
<Netlist
*> ancestors_of_A
;
1758 Netlist
*cursor
= A
;
1760 ancestors_of_A
.insert(cursor
);
1761 if (cursor
->NumOfRefs() != 1)
1763 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1768 if (ancestors_of_A
.count(cursor
))
1770 if (cursor
->NumOfRefs() != 1)
1772 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1775 log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A
).c_str(), get_full_netlist_name(B
).c_str());
1778 void run(Netlist
*nl
)
1784 vector
<tuple
<Instance
*, Port
*, Net
*>> todo_connect
;
1786 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1789 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1790 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
)
1792 Port
*port
= pr
->GetPort();
1793 Net
*net
= pr
->GetNet();
1795 if (!net
->IsExternalTo(nl
))
1798 if (verific_verbose
)
1799 log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl
).c_str(), inst
->Name(), port
->Name());
1801 Netlist
*ext_nl
= net
->Owner();
1803 if (verific_verbose
)
1804 log(" external net owner: %s\n", get_full_netlist_name(ext_nl
).c_str());
1806 Netlist
*ca_nl
= find_common_ancestor(nl
, ext_nl
);
1808 if (verific_verbose
)
1809 log(" common ancestor: %s\n", get_full_netlist_name(ca_nl
).c_str());
1811 Net
*ca_net
= route_up(net
, !port
->IsOutput(), ca_nl
);
1812 Net
*new_net
= ca_net
;
1816 if (verific_verbose
)
1817 log(" net in common ancestor: %s\n", ca_net
->Name());
1819 string name
= stringf("___extnets_%d", portname_cnt
++);
1820 new_net
= new Net(name
.c_str());
1823 Net
*n
YS_ATTRIBUTE(unused
) = route_up(new_net
, port
->IsOutput(), ca_nl
, ca_net
);
1824 log_assert(n
== ca_net
);
1827 if (verific_verbose
)
1828 log(" new local net: %s\n", new_net
->Name());
1830 log_assert(!new_net
->IsExternalTo(nl
));
1831 todo_connect
.push_back(tuple
<Instance
*, Port
*, Net
*>(inst
, port
, new_net
));
1834 for (auto it
: todo_connect
) {
1835 get
<0>(it
)->Disconnect(get
<1>(it
));
1836 get
<0>(it
)->Connect(get
<1>(it
), get
<2>(it
));
1841 void verific_import(Design
*design
, const std::map
<std::string
,std::string
> ¶meters
, std::string top
)
1843 verific_sva_fsm_limit
= 16;
1845 std::set
<Netlist
*> nl_todo
, nl_done
;
1847 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary("work", 1);
1848 VeriLibrary
*veri_lib
= veri_file::GetLibrary("work", 1);
1849 Array
*netlists
= NULL
;
1850 Array veri_libs
, vhdl_libs
;
1851 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
1852 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
1854 Map
verific_params(STRING_HASH
);
1855 for (const auto &i
: parameters
)
1856 verific_params
.Insert(i
.first
.c_str(), i
.second
.c_str());
1859 netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, &verific_params
);
1862 Array veri_modules
, vhdl_units
;
1865 VeriModule
*veri_module
= veri_lib
->GetModule(top
.c_str(), 1);
1867 veri_modules
.InsertLast(veri_module
);
1870 // Also elaborate all root modules since they may contain bind statements
1872 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
1873 if (!veri_module
->IsRootModule()) continue;
1874 veri_modules
.InsertLast(veri_module
);
1879 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(top
.c_str());
1881 vhdl_units
.InsertLast(vhdl_unit
);
1884 netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, &verific_params
);
1890 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
1891 if (top
.empty() && nl
->CellBaseName() != top
)
1893 nl
->AddAtt(new Att(" \\top", NULL
));
1899 if (!verific_error_msg
.empty())
1900 log_error("%s\n", verific_error_msg
.c_str());
1902 for (auto nl
: nl_todo
)
1903 nl
->ChangePortBusStructures(1 /* hierarchical */);
1905 VerificExtNets worker
;
1906 for (auto nl
: nl_todo
)
1909 while (!nl_todo
.empty()) {
1910 Netlist
*nl
= *nl_todo
.begin();
1911 if (nl_done
.count(nl
) == 0) {
1912 VerificImporter
importer(false, false, false, false, false, false, false);
1913 importer
.import_netlist(design
, nl
, nl_todo
, nl
->Owner()->Name() == top
);
1922 verific_incdirs
.clear();
1923 verific_libdirs
.clear();
1924 verific_import_pending
= false;
1926 if (!verific_error_msg
.empty())
1927 log_error("%s\n", verific_error_msg
.c_str());
1931 #endif /* YOSYS_ENABLE_VERIFIC */
1933 PRIVATE_NAMESPACE_BEGIN
1935 #ifdef YOSYS_ENABLE_VERIFIC
1936 bool check_noverific_env()
1938 const char *e
= getenv("YOSYS_NOVERIFIC");
1947 struct VerificPass
: public Pass
{
1948 VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
1949 void help() YS_OVERRIDE
1951 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1953 log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
1955 log("Load the specified Verilog/SystemVerilog files into Verific.\n");
1957 log("All files specified in one call to this command are one compilation unit.\n");
1958 log("Files passed to different calls to this command are treated as belonging to\n");
1959 log("different compilation units.\n");
1961 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
1962 log("the language version (and before file names) to set additional verilog defines.\n");
1963 log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
1966 log(" verific -formal <verilog-file>..\n");
1968 log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
1971 log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
1973 log("Load the specified VHDL files into Verific.\n");
1976 log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
1978 log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
1979 log("(default library when -work is not present: \"work\")\n");
1982 log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
1984 log("Look up external definitions in the specified library.\n");
1985 log("(-L may be used more than once)\n");
1988 log(" verific -vlog-incdir <directory>..\n");
1990 log("Add Verilog include directories.\n");
1993 log(" verific -vlog-libdir <directory>..\n");
1995 log("Add Verilog library directories. Verific will search in this directories to\n");
1996 log("find undefined modules.\n");
1999 log(" verific -vlog-define <macro>[=<value>]..\n");
2001 log("Add Verilog defines.\n");
2004 log(" verific -vlog-undef <macro>..\n");
2006 log("Remove Verilog defines previously set with -vlog-define.\n");
2009 log(" verific -set-error <msg_id>..\n");
2010 log(" verific -set-warning <msg_id>..\n");
2011 log(" verific -set-info <msg_id>..\n");
2012 log(" verific -set-ignore <msg_id>..\n");
2014 log("Set message severity. <msg_id> is the string in square brackets when a message\n");
2015 log("is printed, such as VERI-1209.\n");
2018 log(" verific -import [options] <top-module>..\n");
2020 log("Elaborate the design for the specified top modules, import to Yosys and\n");
2021 log("reset the internal state of Verific.\n");
2023 log("Import options:\n");
2026 log(" Elaborate all modules, not just the hierarchy below the given top\n");
2027 log(" modules. With this option the list of modules to import is optional.\n");
2030 log(" Create a gate-level netlist.\n");
2033 log(" Flatten the design in Verific before importing.\n");
2036 log(" Resolve references to external nets by adding module ports as needed.\n");
2038 log(" -autocover\n");
2039 log(" Generate automatic cover statements for all asserts\n");
2041 log(" -fullinit\n");
2042 log(" Keep all register initializations, even those for non-FF registers.\n");
2044 log(" -chparam name value \n");
2045 log(" Elaborate the specified top modules (all modules when -all given) using\n");
2046 log(" this parameter value. Modules on which this parameter does not exist will\n");
2047 log(" cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
2048 log(" can be specified multiple times to override multiple parameters.\n");
2049 log(" String values must be passed in double quotes (\").\n");
2052 log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
2054 log("The following additional import options are useful for debugging the Verific\n");
2055 log("bindings (for Yosys and/or Verific developers):\n");
2058 log(" Keep going after an unsupported verific primitive is found. The\n");
2059 log(" unsupported primitive is added as blockbox module to the design.\n");
2060 log(" This will also add all SVA related cells to the design parallel to\n");
2061 log(" the checker logic inferred by it.\n");
2064 log(" Import Verific netlist as-is without translating to Yosys cell types. \n");
2067 log(" Ignore SVA properties, do not infer checker logic.\n");
2070 log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
2073 log(" Keep all Verific names on instances and nets. By default only\n");
2074 log(" user-declared names are preserved.\n");
2076 log(" -d <dump_file>\n");
2077 log(" Dump the Verific netlist as a verilog file.\n");
2080 log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n");
2081 log("https://www.symbioticeda.com/seda-suite\n");
2083 log("Contact office@symbioticeda.com for free evaluation\n");
2084 log("binaries of Symbiotic EDA Suite.\n");
2087 #ifdef YOSYS_ENABLE_VERIFIC
2088 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
2090 static bool set_verific_global_flags
= true;
2092 if (check_noverific_env())
2093 log_cmd_error("This version of Yosys is built without Verific support.\n"
2095 "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
2096 "https://www.symbioticeda.com/seda-suite\n"
2098 "Contact office@symbioticeda.com for free evaluation\n"
2099 "binaries of Symbiotic EDA Suite.\n");
2101 log_header(design
, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
2103 if (set_verific_global_flags
)
2105 Message::SetConsoleOutput(0);
2106 Message::RegisterCallBackMsg(msg_func
);
2108 RuntimeFlags::SetVar("db_preserve_user_nets", 1);
2109 RuntimeFlags::SetVar("db_allow_external_nets", 1);
2110 RuntimeFlags::SetVar("db_infer_wide_operators", 1);
2112 RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
2113 RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
2115 RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
2116 RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
2118 RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
2119 RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
2121 // Workaround for VIPER #13851
2122 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
2124 // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
2125 Message::SetMessageType("VERI-1063", VERIFIC_ERROR
);
2127 // https://github.com/YosysHQ/yosys/issues/1055
2128 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
2130 #ifndef DB_PRESERVE_INITIAL_VALUE
2131 # warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
2134 set_verific_global_flags
= false;
2137 verific_verbose
= 0;
2138 verific_sva_fsm_limit
= 16;
2140 const char *release_str
= Message::ReleaseString();
2141 time_t release_time
= Message::ReleaseDate();
2142 char *release_tmstr
= ctime(&release_time
);
2144 if (release_str
== nullptr)
2145 release_str
= "(no release string)";
2147 for (char *p
= release_tmstr
; *p
; p
++)
2148 if (*p
== '\n') *p
= 0;
2150 log("Built with Verific %s, released at %s.\n", release_str
, release_tmstr
);
2153 std::string work
= "work";
2155 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-set-error" || args
[argidx
] == "-set-warning" ||
2156 args
[argidx
] == "-set-info" || args
[argidx
] == "-set-ignore"))
2158 msg_type_t new_type
;
2160 if (args
[argidx
] == "-set-error")
2161 new_type
= VERIFIC_ERROR
;
2162 else if (args
[argidx
] == "-set-warning")
2163 new_type
= VERIFIC_WARNING
;
2164 else if (args
[argidx
] == "-set-info")
2165 new_type
= VERIFIC_INFO
;
2166 else if (args
[argidx
] == "-set-ignore")
2167 new_type
= VERIFIC_IGNORE
;
2171 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2172 Message::SetMessageType(args
[argidx
].c_str(), new_type
);
2177 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-incdir") {
2178 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2179 verific_incdirs
.push_back(args
[argidx
]);
2183 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-libdir") {
2184 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2185 verific_libdirs
.push_back(args
[argidx
]);
2189 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-define") {
2190 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2191 string name
= args
[argidx
];
2192 size_t equal
= name
.find('=');
2193 if (equal
!= std::string::npos
) {
2194 string value
= name
.substr(equal
+1);
2195 name
= name
.substr(0, equal
);
2196 veri_file::DefineCmdLineMacro(name
.c_str(), value
.c_str());
2198 veri_file::DefineCmdLineMacro(name
.c_str());
2204 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-undef") {
2205 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2206 string name
= args
[argidx
];
2207 veri_file::UndefineMacro(name
.c_str());
2212 veri_file::RemoveAllLOptions();
2213 for (; argidx
< GetSize(args
); argidx
++)
2215 if (args
[argidx
] == "-work" && argidx
+1 < GetSize(args
)) {
2216 work
= args
[++argidx
];
2219 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2220 veri_file::AddLOption(args
[++argidx
].c_str());
2226 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vlog95" || args
[argidx
] == "-vlog2k" || args
[argidx
] == "-sv2005" ||
2227 args
[argidx
] == "-sv2009" || args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal"))
2230 unsigned verilog_mode
;
2232 if (args
[argidx
] == "-vlog95")
2233 verilog_mode
= veri_file::VERILOG_95
;
2234 else if (args
[argidx
] == "-vlog2k")
2235 verilog_mode
= veri_file::VERILOG_2K
;
2236 else if (args
[argidx
] == "-sv2005")
2237 verilog_mode
= veri_file::SYSTEM_VERILOG_2005
;
2238 else if (args
[argidx
] == "-sv2009")
2239 verilog_mode
= veri_file::SYSTEM_VERILOG_2009
;
2240 else if (args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal")
2241 verilog_mode
= veri_file::SYSTEM_VERILOG
;
2245 veri_file::DefineMacro("VERIFIC");
2246 veri_file::DefineMacro(args
[argidx
] == "-formal" ? "FORMAL" : "SYNTHESIS");
2248 for (argidx
++; argidx
< GetSize(args
) && GetSize(args
[argidx
]) >= 2 && args
[argidx
].compare(0, 2, "-D") == 0; argidx
++) {
2249 std::string name
= args
[argidx
].substr(2);
2250 if (args
[argidx
] == "-D") {
2251 if (++argidx
>= GetSize(args
))
2253 name
= args
[argidx
];
2255 size_t equal
= name
.find('=');
2256 if (equal
!= std::string::npos
) {
2257 string value
= name
.substr(equal
+1);
2258 name
= name
.substr(0, equal
);
2259 veri_file::DefineMacro(name
.c_str(), value
.c_str());
2261 veri_file::DefineMacro(name
.c_str());
2265 for (auto &dir
: verific_incdirs
)
2266 veri_file::AddIncludeDir(dir
.c_str());
2267 for (auto &dir
: verific_libdirs
)
2268 veri_file::AddYDir(dir
.c_str());
2270 while (argidx
< GetSize(args
))
2271 file_names
.Insert(args
[argidx
++].c_str());
2273 if (!veri_file::AnalyzeMultipleFiles(&file_names
, verilog_mode
, work
.c_str(), veri_file::MFCU
))
2274 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2276 verific_import_pending
= true;
2280 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl87") {
2281 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
2282 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2283 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_87
))
2284 log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args
[argidx
].c_str());
2285 verific_import_pending
= true;
2289 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl93") {
2290 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2291 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2292 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_93
))
2293 log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args
[argidx
].c_str());
2294 verific_import_pending
= true;
2298 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl2k") {
2299 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2300 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2301 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2K
))
2302 log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args
[argidx
].c_str());
2303 verific_import_pending
= true;
2307 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vhdl2008" || args
[argidx
] == "-vhdl")) {
2308 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
2309 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2310 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2008
))
2311 log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args
[argidx
].c_str());
2312 verific_import_pending
= true;
2316 if (GetSize(args
) > argidx
&& args
[argidx
] == "-import")
2318 std::set
<Netlist
*> nl_todo
, nl_done
;
2319 bool mode_all
= false, mode_gates
= false, mode_keep
= false;
2320 bool mode_nosva
= false, mode_names
= false, mode_verific
= false;
2321 bool mode_autocover
= false, mode_fullinit
= false;
2322 bool flatten
= false, extnets
= false;
2324 Map
parameters(STRING_HASH
);
2326 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2327 if (args
[argidx
] == "-all") {
2331 if (args
[argidx
] == "-gates") {
2335 if (args
[argidx
] == "-flatten") {
2339 if (args
[argidx
] == "-extnets") {
2343 if (args
[argidx
] == "-k") {
2347 if (args
[argidx
] == "-nosva") {
2351 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2352 verific_sva_fsm_limit
= atoi(args
[++argidx
].c_str());
2355 if (args
[argidx
] == "-n") {
2359 if (args
[argidx
] == "-autocover") {
2360 mode_autocover
= true;
2363 if (args
[argidx
] == "-fullinit") {
2364 mode_fullinit
= true;
2367 if (args
[argidx
] == "-chparam" && argidx
+2 < GetSize(args
)) {
2368 const std::string
&key
= args
[++argidx
];
2369 const std::string
&value
= args
[++argidx
];
2370 unsigned new_insertion
= parameters
.Insert(key
.c_str(), value
.c_str(),
2371 1 /* force_overwrite */);
2373 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key
.c_str());
2376 if (args
[argidx
] == "-V") {
2377 mode_verific
= true;
2380 if (args
[argidx
] == "-v") {
2381 verific_verbose
= 1;
2384 if (args
[argidx
] == "-vv") {
2385 verific_verbose
= 2;
2388 if (args
[argidx
] == "-d" && argidx
+1 < GetSize(args
)) {
2389 dumpfile
= args
[++argidx
];
2395 if (argidx
> GetSize(args
) && args
[argidx
].compare(0, 1, "-") == 0)
2396 cmd_error(args
, argidx
, "unknown option");
2398 std::set
<std::string
> top_mod_names
;
2402 log("Running hier_tree::ElaborateAll().\n");
2404 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2405 VeriLibrary
*veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2407 Array veri_libs
, vhdl_libs
;
2408 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
2409 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
2411 Array
*netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, ¶meters
);
2415 FOREACH_ARRAY_ITEM(netlists
, i
, nl
)
2421 if (argidx
== GetSize(args
))
2422 cmd_error(args
, argidx
, "No top module specified.\n");
2424 Array veri_modules
, vhdl_units
;
2425 for (; argidx
< GetSize(args
); argidx
++)
2427 const char *name
= args
[argidx
].c_str();
2428 top_mod_names
.insert(name
);
2429 VeriLibrary
* veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2432 VeriModule
*veri_module
= veri_lib
->GetModule(name
, 1);
2434 log("Adding Verilog module '%s' to elaboration queue.\n", name
);
2435 veri_modules
.InsertLast(veri_module
);
2439 // Also elaborate all root modules since they may contain bind statements
2441 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
2442 if (!veri_module
->IsRootModule()) continue;
2443 veri_modules
.InsertLast(veri_module
);
2447 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2448 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(name
);
2450 log("Adding VHDL unit '%s' to elaboration queue.\n", name
);
2451 vhdl_units
.InsertLast(vhdl_unit
);
2455 log_error("Can't find module/unit '%s'.\n", name
);
2458 log("Running hier_tree::Elaborate().\n");
2459 Array
*netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, ¶meters
);
2463 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
2464 nl
->AddAtt(new Att(" \\top", NULL
));
2470 if (!verific_error_msg
.empty())
2474 for (auto nl
: nl_todo
)
2479 VerificExtNets worker
;
2480 for (auto nl
: nl_todo
)
2484 for (auto nl
: nl_todo
)
2485 nl
->ChangePortBusStructures(1 /* hierarchical */);
2487 if (!dumpfile
.empty()) {
2488 VeriWrite veri_writer
;
2489 veri_writer
.WriteFile(dumpfile
.c_str(), Netlist::PresentDesign());
2492 while (!nl_todo
.empty()) {
2493 Netlist
*nl
= *nl_todo
.begin();
2494 if (nl_done
.count(nl
) == 0) {
2495 VerificImporter
importer(mode_gates
, mode_keep
, mode_nosva
,
2496 mode_names
, mode_verific
, mode_autocover
, mode_fullinit
);
2497 importer
.import_netlist(design
, nl
, nl_todo
, top_mod_names
.count(nl
->Owner()->Name()));
2506 verific_incdirs
.clear();
2507 verific_libdirs
.clear();
2508 verific_import_pending
= false;
2512 cmd_error(args
, argidx
, "Missing or unsupported mode parameter.\n");
2515 if (!verific_error_msg
.empty())
2516 log_error("%s\n", verific_error_msg
.c_str());
2519 #else /* YOSYS_ENABLE_VERIFIC */
2520 void execute(std::vector
<std::string
>, RTLIL::Design
*) YS_OVERRIDE
{
2521 log_cmd_error("This version of Yosys is built without Verific support.\n"
2523 "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
2524 "https://www.symbioticeda.com/seda-suite\n"
2526 "Contact office@symbioticeda.com for free evaluation\n"
2527 "binaries of Symbiotic EDA Suite.\n");
2532 struct ReadPass
: public Pass
{
2533 ReadPass() : Pass("read", "load HDL designs") { }
2534 void help() YS_OVERRIDE
2536 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2538 log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
2540 log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
2541 log("is only available via Verific.)\n");
2543 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2544 log("the language version (and before file names) to set additional verilog defines.\n");
2547 log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2549 log("Load the specified VHDL files. (Requires Verific.)\n");
2552 log(" read -define <macro>[=<value>]..\n");
2554 log("Set global Verilog/SystemVerilog defines.\n");
2557 log(" read -undef <macro>..\n");
2559 log("Unset global Verilog/SystemVerilog defines.\n");
2562 log(" read -incdir <directory>\n");
2564 log("Add directory to global Verilog/SystemVerilog include directories.\n");
2567 log(" read -verific\n");
2568 log(" read -noverific\n");
2570 log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
2571 log("with -verific will result in an error on Yosys binaries that are built without\n");
2572 log("Verific support. The default is to use Verific if it is available.\n");
2575 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
2577 #ifdef YOSYS_ENABLE_VERIFIC
2578 static bool verific_available
= !check_noverific_env();
2580 static bool verific_available
= false;
2582 static bool use_verific
= verific_available
;
2584 if (args
.size() < 2 || args
[1][0] != '-')
2585 cmd_error(args
, 1, "Missing mode parameter.\n");
2587 if (args
[1] == "-verific" || args
[1] == "-noverific") {
2588 if (args
.size() != 2)
2589 cmd_error(args
, 1, "Additional arguments to -verific/-noverific.\n");
2590 if (args
[1] == "-verific") {
2591 if (!verific_available
)
2592 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
2595 use_verific
= false;
2600 if (args
.size() < 3)
2601 cmd_error(args
, 3, "Missing file name parameter.\n");
2603 if (args
[1] == "-vlog95" || args
[1] == "-vlog2k") {
2605 args
[0] = "verific";
2607 args
[0] = "read_verilog";
2610 Pass::call(design
, args
);
2614 if (args
[1] == "-sv2005" || args
[1] == "-sv2009" || args
[1] == "-sv2012" || args
[1] == "-sv" || args
[1] == "-formal") {
2616 args
[0] = "verific";
2618 args
[0] = "read_verilog";
2619 if (args
[1] == "-formal")
2620 args
.insert(args
.begin()+1, std::string());
2622 args
.insert(args
.begin()+1, "-defer");
2624 Pass::call(design
, args
);
2628 if (args
[1] == "-vhdl87" || args
[1] == "-vhdl93" || args
[1] == "-vhdl2k" || args
[1] == "-vhdl2008" || args
[1] == "-vhdl") {
2630 args
[0] = "verific";
2631 Pass::call(design
, args
);
2633 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
2638 if (args
[1] == "-define") {
2640 args
[0] = "verific";
2641 args
[1] = "-vlog-define";
2642 Pass::call(design
, args
);
2644 args
[0] = "verilog_defines";
2645 args
.erase(args
.begin()+1, args
.begin()+2);
2646 for (int i
= 1; i
< GetSize(args
); i
++)
2647 args
[i
] = "-D" + args
[i
];
2648 Pass::call(design
, args
);
2652 if (args
[1] == "-undef") {
2654 args
[0] = "verific";
2655 args
[1] = "-vlog-undef";
2656 Pass::call(design
, args
);
2658 args
[0] = "verilog_defines";
2659 args
.erase(args
.begin()+1, args
.begin()+2);
2660 for (int i
= 1; i
< GetSize(args
); i
++)
2661 args
[i
] = "-U" + args
[i
];
2662 Pass::call(design
, args
);
2666 if (args
[1] == "-incdir") {
2668 args
[0] = "verific";
2669 args
[1] = "-vlog-incdir";
2670 Pass::call(design
, args
);
2672 args
[0] = "verilog_defaults";
2674 for (int i
= 2; i
< GetSize(args
); i
++)
2675 args
[i
] = "-I" + args
[i
];
2676 Pass::call(design
, args
);
2680 cmd_error(args
, 1, "Missing or unsupported mode parameter.\n");
2684 PRIVATE_NAMESPACE_END