2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/celltypes.h"
23 #include "kernel/log.h"
33 #include "frontends/verific/verific.h"
37 #ifdef YOSYS_ENABLE_VERIFIC
40 #pragma clang diagnostic push
41 #pragma clang diagnostic ignored "-Woverloaded-virtual"
44 #include "veri_file.h"
45 #include "vhdl_file.h"
46 #include "hier_tree.h"
47 #include "VeriModule.h"
48 #include "VeriWrite.h"
49 #include "VhdlUnits.h"
50 #include "VeriLibrary.h"
52 #ifndef SYMBIOTIC_VERIFIC_API_VERSION
53 # error "Only Symbiotic EDA flavored Verific is supported. Please contact office@symbioticeda.com for commercial support for Yosys+Verific."
56 #if SYMBIOTIC_VERIFIC_API_VERSION < 1
57 # error "Please update your version of Symbiotic EDA flavored Verific."
61 #pragma clang diagnostic pop
64 #ifdef VERIFIC_NAMESPACE
65 using namespace Verific
;
70 #ifdef YOSYS_ENABLE_VERIFIC
74 bool verific_import_pending
;
75 string verific_error_msg
;
76 int verific_sva_fsm_limit
;
78 vector
<string
> verific_incdirs
, verific_libdirs
;
80 void msg_func(msg_type_t msg_type
, const char *message_id
, linefile_type linefile
, const char *msg
, va_list args
)
82 string message_prefix
= stringf("VERIFIC-%s [%s] ",
83 msg_type
== VERIFIC_NONE
? "NONE" :
84 msg_type
== VERIFIC_ERROR
? "ERROR" :
85 msg_type
== VERIFIC_WARNING
? "WARNING" :
86 msg_type
== VERIFIC_IGNORE
? "IGNORE" :
87 msg_type
== VERIFIC_INFO
? "INFO" :
88 msg_type
== VERIFIC_COMMENT
? "COMMENT" :
89 msg_type
== VERIFIC_PROGRAM_ERROR
? "PROGRAM_ERROR" : "UNKNOWN", message_id
);
91 string message
= linefile
? stringf("%s:%d: ", LineFile::GetFileName(linefile
), LineFile::GetLineNo(linefile
)) : "";
92 message
+= vstringf(msg
, args
);
94 if (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_WARNING
|| msg_type
== VERIFIC_PROGRAM_ERROR
)
95 log_warning_noprefix("%s%s\n", message_prefix
.c_str(), message
.c_str());
97 log("%s%s\n", message_prefix
.c_str(), message
.c_str());
99 if (verific_error_msg
.empty() && (msg_type
== VERIFIC_ERROR
|| msg_type
== VERIFIC_PROGRAM_ERROR
))
100 verific_error_msg
= message
;
103 string
get_full_netlist_name(Netlist
*nl
)
105 if (nl
->NumOfRefs() == 1) {
106 Instance
*inst
= (Instance
*)nl
->GetReferences()->GetLast();
107 return get_full_netlist_name(inst
->Owner()) + "." + inst
->Name();
110 return nl
->CellBaseName();
113 // ==================================================================
115 VerificImporter::VerificImporter(bool mode_gates
, bool mode_keep
, bool mode_nosva
, bool mode_names
, bool mode_verific
, bool mode_autocover
, bool mode_fullinit
) :
116 mode_gates(mode_gates
), mode_keep(mode_keep
), mode_nosva(mode_nosva
),
117 mode_names(mode_names
), mode_verific(mode_verific
), mode_autocover(mode_autocover
),
118 mode_fullinit(mode_fullinit
)
122 RTLIL::SigBit
VerificImporter::net_map_at(Net
*net
)
124 if (net
->IsExternalTo(netlist
))
125 log_error("Found external reference to '%s.%s' in netlist '%s', please use -flatten or -extnets.\n",
126 get_full_netlist_name(net
->Owner()).c_str(), net
->Name(), get_full_netlist_name(netlist
).c_str());
128 return net_map
.at(net
);
131 bool is_blackbox(Netlist
*nl
)
133 if (nl
->IsBlackBox() || nl
->IsEmptyBox())
136 const char *attr
= nl
->GetAttValue("blackbox");
137 if (attr
!= nullptr && strcmp(attr
, "0"))
143 RTLIL::IdString
VerificImporter::new_verific_id(Verific::DesignObj
*obj
)
145 std::string s
= stringf("$verific$%s", obj
->Name());
147 s
+= stringf("$%s:%d", Verific::LineFile::GetFileName(obj
->Linefile()), Verific::LineFile::GetLineNo(obj
->Linefile()));
148 s
+= stringf("$%d", autoidx
++);
152 void VerificImporter::import_attributes(dict
<RTLIL::IdString
, RTLIL::Const
> &attributes
, DesignObj
*obj
, Netlist
*nl
)
158 attributes
[ID::src
] = stringf("%s:%d", LineFile::GetFileName(obj
->Linefile()), LineFile::GetLineNo(obj
->Linefile()));
160 // FIXME: Parse numeric attributes
161 FOREACH_ATTRIBUTE(obj
, mi
, attr
) {
162 if (attr
->Key()[0] == ' ' || attr
->Value() == nullptr)
164 attributes
[RTLIL::escape_id(attr
->Key())] = RTLIL::Const(std::string(attr
->Value()));
168 auto type_range
= nl
->GetTypeRange(obj
->Name());
171 if (!type_range
->IsTypeEnum())
173 if (nl
->IsFromVhdl() && strcmp(type_range
->GetTypeName(), "STD_LOGIC") == 0)
175 auto type_name
= type_range
->GetTypeName();
178 attributes
.emplace(ID::wiretype
, RTLIL::escape_id(type_name
));
182 FOREACH_MAP_ITEM(type_range
->GetEnumIdMap(), mi
, &k
, &v
) {
183 if (nl
->IsFromVerilog()) {
184 // Expect <decimal>'b<binary>
185 auto p
= strchr(v
, '\'');
190 for (auto q
= p
+2; *q
!= '\0'; q
++)
191 if (*q
!= '0' && *q
!= '1') {
197 log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v
);
198 attributes
.emplace(stringf("\\enum_value_%s", p
+2), RTLIL::escape_id(k
));
200 else if (nl
->IsFromVhdl()) {
208 for (; *q
!= '"'; q
++)
209 if (*q
!= '0' && *q
!= '1') {
213 if (p
&& *(q
+1) != '\0')
218 log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v
);
220 auto q
= (char*)malloc(l
+1-2);
221 strncpy(q
, p
+1, l
-2);
223 attributes
.emplace(stringf("\\enum_value_%s", q
), RTLIL::escape_id(k
));
230 RTLIL::SigSpec
VerificImporter::operatorInput(Instance
*inst
)
233 for (int i
= int(inst
->InputSize())-1; i
>= 0; i
--)
234 if (inst
->GetInputBit(i
))
235 sig
.append(net_map_at(inst
->GetInputBit(i
)));
237 sig
.append(RTLIL::State::Sz
);
241 RTLIL::SigSpec
VerificImporter::operatorInput1(Instance
*inst
)
244 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--)
245 if (inst
->GetInput1Bit(i
))
246 sig
.append(net_map_at(inst
->GetInput1Bit(i
)));
248 sig
.append(RTLIL::State::Sz
);
252 RTLIL::SigSpec
VerificImporter::operatorInput2(Instance
*inst
)
255 for (int i
= int(inst
->Input2Size())-1; i
>= 0; i
--)
256 if (inst
->GetInput2Bit(i
))
257 sig
.append(net_map_at(inst
->GetInput2Bit(i
)));
259 sig
.append(RTLIL::State::Sz
);
263 RTLIL::SigSpec
VerificImporter::operatorInport(Instance
*inst
, const char *portname
)
265 PortBus
*portbus
= inst
->View()->GetPortBus(portname
);
268 for (unsigned i
= 0; i
< portbus
->Size(); i
++) {
269 Net
*net
= inst
->GetNet(portbus
->ElementAtIndex(i
));
272 sig
.append(RTLIL::State::S0
);
273 else if (net
->IsPwr())
274 sig
.append(RTLIL::State::S1
);
276 sig
.append(net_map_at(net
));
278 sig
.append(RTLIL::State::Sz
);
282 Port
*port
= inst
->View()->GetPort(portname
);
283 log_assert(port
!= NULL
);
284 Net
*net
= inst
->GetNet(port
);
285 return net_map_at(net
);
289 RTLIL::SigSpec
VerificImporter::operatorOutput(Instance
*inst
, const pool
<Net
*, hash_ptr_ops
> *any_all_nets
)
292 RTLIL::Wire
*dummy_wire
= NULL
;
293 for (int i
= int(inst
->OutputSize())-1; i
>= 0; i
--)
294 if (inst
->GetOutputBit(i
) && (!any_all_nets
|| !any_all_nets
->count(inst
->GetOutputBit(i
)))) {
295 sig
.append(net_map_at(inst
->GetOutputBit(i
)));
298 if (dummy_wire
== NULL
)
299 dummy_wire
= module
->addWire(new_verific_id(inst
));
302 sig
.append(RTLIL::SigSpec(dummy_wire
, dummy_wire
->width
- 1));
307 bool VerificImporter::import_netlist_instance_gates(Instance
*inst
, RTLIL::IdString inst_name
)
309 if (inst
->Type() == PRIM_AND
) {
310 module
->addAndGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
314 if (inst
->Type() == PRIM_NAND
) {
315 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
316 module
->addAndGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
317 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
321 if (inst
->Type() == PRIM_OR
) {
322 module
->addOrGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
326 if (inst
->Type() == PRIM_NOR
) {
327 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
328 module
->addOrGate(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
329 module
->addNotGate(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
333 if (inst
->Type() == PRIM_XOR
) {
334 module
->addXorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
338 if (inst
->Type() == PRIM_XNOR
) {
339 module
->addXnorGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
343 if (inst
->Type() == PRIM_BUF
) {
344 auto outnet
= inst
->GetOutput();
345 if (!any_all_nets
.count(outnet
))
346 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
350 if (inst
->Type() == PRIM_INV
) {
351 module
->addNotGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
355 if (inst
->Type() == PRIM_MUX
) {
356 module
->addMuxGate(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
360 if (inst
->Type() == PRIM_TRI
) {
361 module
->addMuxGate(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
365 if (inst
->Type() == PRIM_FADD
)
367 RTLIL::SigSpec a
= net_map_at(inst
->GetInput1()), b
= net_map_at(inst
->GetInput2()), c
= net_map_at(inst
->GetCin());
368 RTLIL::SigSpec x
= inst
->GetCout() ? net_map_at(inst
->GetCout()) : module
->addWire(new_verific_id(inst
));
369 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
370 RTLIL::SigSpec tmp1
= module
->addWire(new_verific_id(inst
));
371 RTLIL::SigSpec tmp2
= module
->addWire(new_verific_id(inst
));
372 RTLIL::SigSpec tmp3
= module
->addWire(new_verific_id(inst
));
373 module
->addXorGate(new_verific_id(inst
), a
, b
, tmp1
);
374 module
->addXorGate(inst_name
, tmp1
, c
, y
);
375 module
->addAndGate(new_verific_id(inst
), tmp1
, c
, tmp2
);
376 module
->addAndGate(new_verific_id(inst
), a
, b
, tmp3
);
377 module
->addOrGate(new_verific_id(inst
), tmp2
, tmp3
, x
);
381 if (inst
->Type() == PRIM_DFFRS
)
383 VerificClocking
clocking(this, inst
->GetClock());
384 log_assert(clocking
.disable_sig
== State::S0
);
385 log_assert(clocking
.body_net
== nullptr);
387 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
388 clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
389 else if (inst
->GetSet()->IsGnd())
390 clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S0
);
391 else if (inst
->GetReset()->IsGnd())
392 clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), State::S1
);
394 clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
395 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
402 bool VerificImporter::import_netlist_instance_cells(Instance
*inst
, RTLIL::IdString inst_name
)
404 RTLIL::Cell
*cell
= nullptr;
406 if (inst
->Type() == PRIM_AND
) {
407 cell
= module
->addAnd(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
408 import_attributes(cell
->attributes
, inst
);
412 if (inst
->Type() == PRIM_NAND
) {
413 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
414 cell
= module
->addAnd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
415 import_attributes(cell
->attributes
, inst
);
416 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
417 import_attributes(cell
->attributes
, inst
);
421 if (inst
->Type() == PRIM_OR
) {
422 cell
= module
->addOr(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
423 import_attributes(cell
->attributes
, inst
);
427 if (inst
->Type() == PRIM_NOR
) {
428 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
));
429 cell
= module
->addOr(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), tmp
);
430 import_attributes(cell
->attributes
, inst
);
431 cell
= module
->addNot(inst_name
, tmp
, net_map_at(inst
->GetOutput()));
432 import_attributes(cell
->attributes
, inst
);
436 if (inst
->Type() == PRIM_XOR
) {
437 cell
= module
->addXor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
438 import_attributes(cell
->attributes
, inst
);
442 if (inst
->Type() == PRIM_XNOR
) {
443 cell
= module
->addXnor(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetOutput()));
444 import_attributes(cell
->attributes
, inst
);
448 if (inst
->Type() == PRIM_INV
) {
449 cell
= module
->addNot(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
450 import_attributes(cell
->attributes
, inst
);
454 if (inst
->Type() == PRIM_MUX
) {
455 cell
= module
->addMux(inst_name
, net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
456 import_attributes(cell
->attributes
, inst
);
460 if (inst
->Type() == PRIM_TRI
) {
461 cell
= module
->addMux(inst_name
, RTLIL::State::Sz
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetControl()), net_map_at(inst
->GetOutput()));
462 import_attributes(cell
->attributes
, inst
);
466 if (inst
->Type() == PRIM_FADD
)
468 RTLIL::SigSpec a_plus_b
= module
->addWire(new_verific_id(inst
), 2);
469 RTLIL::SigSpec y
= inst
->GetOutput() ? net_map_at(inst
->GetOutput()) : module
->addWire(new_verific_id(inst
));
471 y
.append(net_map_at(inst
->GetCout()));
472 cell
= module
->addAdd(new_verific_id(inst
), net_map_at(inst
->GetInput1()), net_map_at(inst
->GetInput2()), a_plus_b
);
473 import_attributes(cell
->attributes
, inst
);
474 cell
= module
->addAdd(inst_name
, a_plus_b
, net_map_at(inst
->GetCin()), y
);
475 import_attributes(cell
->attributes
, inst
);
479 if (inst
->Type() == PRIM_DFFRS
)
481 VerificClocking
clocking(this, inst
->GetClock());
482 log_assert(clocking
.disable_sig
== State::S0
);
483 log_assert(clocking
.body_net
== nullptr);
485 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
486 cell
= clocking
.addDff(inst_name
, net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
487 else if (inst
->GetSet()->IsGnd())
488 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetReset()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
489 else if (inst
->GetReset()->IsGnd())
490 cell
= clocking
.addAdff(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
492 cell
= clocking
.addDffsr(inst_name
, net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
493 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
494 import_attributes(cell
->attributes
, inst
);
498 if (inst
->Type() == PRIM_DLATCHRS
)
500 if (inst
->GetSet()->IsGnd() && inst
->GetReset()->IsGnd())
501 cell
= module
->addDlatch(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
503 cell
= module
->addDlatchsr(inst_name
, net_map_at(inst
->GetControl()), net_map_at(inst
->GetSet()), net_map_at(inst
->GetReset()),
504 net_map_at(inst
->GetInput()), net_map_at(inst
->GetOutput()));
505 import_attributes(cell
->attributes
, inst
);
509 #define IN operatorInput(inst)
510 #define IN1 operatorInput1(inst)
511 #define IN2 operatorInput2(inst)
512 #define OUT operatorOutput(inst)
513 #define FILTERED_OUT operatorOutput(inst, &any_all_nets)
514 #define SIGNED inst->View()->IsSigned()
516 if (inst
->Type() == OPER_ADDER
) {
517 RTLIL::SigSpec out
= OUT
;
518 if (inst
->GetCout() != NULL
)
519 out
.append(net_map_at(inst
->GetCout()));
520 if (inst
->GetCin()->IsGnd()) {
521 cell
= module
->addAdd(inst_name
, IN1
, IN2
, out
, SIGNED
);
522 import_attributes(cell
->attributes
, inst
);
524 RTLIL::SigSpec tmp
= module
->addWire(new_verific_id(inst
), GetSize(out
));
525 cell
= module
->addAdd(new_verific_id(inst
), IN1
, IN2
, tmp
, SIGNED
);
526 import_attributes(cell
->attributes
, inst
);
527 cell
= module
->addAdd(inst_name
, tmp
, net_map_at(inst
->GetCin()), out
, false);
528 import_attributes(cell
->attributes
, inst
);
533 if (inst
->Type() == OPER_MULTIPLIER
) {
534 cell
= module
->addMul(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
535 import_attributes(cell
->attributes
, inst
);
539 if (inst
->Type() == OPER_DIVIDER
) {
540 cell
= module
->addDiv(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
541 import_attributes(cell
->attributes
, inst
);
545 if (inst
->Type() == OPER_MODULO
) {
546 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
547 import_attributes(cell
->attributes
, inst
);
551 if (inst
->Type() == OPER_REMAINDER
) {
552 cell
= module
->addMod(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
553 import_attributes(cell
->attributes
, inst
);
557 if (inst
->Type() == OPER_SHIFT_LEFT
) {
558 cell
= module
->addShl(inst_name
, IN1
, IN2
, OUT
, false);
559 import_attributes(cell
->attributes
, inst
);
563 if (inst
->Type() == OPER_ENABLED_DECODER
) {
565 vec
.append(net_map_at(inst
->GetControl()));
566 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
567 vec
.append(RTLIL::State::S0
);
569 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
570 import_attributes(cell
->attributes
, inst
);
574 if (inst
->Type() == OPER_DECODER
) {
576 vec
.append(RTLIL::State::S1
);
577 for (unsigned i
= 1; i
< inst
->OutputSize(); i
++) {
578 vec
.append(RTLIL::State::S0
);
580 cell
= module
->addShl(inst_name
, vec
, IN
, OUT
, false);
581 import_attributes(cell
->attributes
, inst
);
585 if (inst
->Type() == OPER_SHIFT_RIGHT
) {
586 Net
*net_cin
= inst
->GetCin();
587 Net
*net_a_msb
= inst
->GetInput1Bit(0);
588 if (net_cin
->IsGnd())
589 cell
= module
->addShr(inst_name
, IN1
, IN2
, OUT
, false);
590 else if (net_cin
== net_a_msb
)
591 cell
= module
->addSshr(inst_name
, IN1
, IN2
, OUT
, true);
593 log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst
->Name());
594 import_attributes(cell
->attributes
, inst
);
598 if (inst
->Type() == OPER_REDUCE_AND
) {
599 cell
= module
->addReduceAnd(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
600 import_attributes(cell
->attributes
, inst
);
604 if (inst
->Type() == OPER_REDUCE_NAND
) {
605 Wire
*tmp
= module
->addWire(NEW_ID
);
606 cell
= module
->addReduceAnd(inst_name
, IN
, tmp
, SIGNED
);
607 module
->addNot(NEW_ID
, tmp
, net_map_at(inst
->GetOutput()));
608 import_attributes(cell
->attributes
, inst
);
612 if (inst
->Type() == OPER_REDUCE_OR
) {
613 cell
= module
->addReduceOr(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
614 import_attributes(cell
->attributes
, inst
);
618 if (inst
->Type() == OPER_REDUCE_XOR
) {
619 cell
= module
->addReduceXor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
620 import_attributes(cell
->attributes
, inst
);
624 if (inst
->Type() == OPER_REDUCE_XNOR
) {
625 cell
= module
->addReduceXnor(inst_name
, IN
, net_map_at(inst
->GetOutput()), SIGNED
);
626 import_attributes(cell
->attributes
, inst
);
630 if (inst
->Type() == OPER_REDUCE_NOR
) {
631 SigSpec t
= module
->ReduceOr(new_verific_id(inst
), IN
, SIGNED
);
632 cell
= module
->addNot(inst_name
, t
, net_map_at(inst
->GetOutput()));
633 import_attributes(cell
->attributes
, inst
);
637 if (inst
->Type() == OPER_LESSTHAN
) {
638 Net
*net_cin
= inst
->GetCin();
639 if (net_cin
->IsGnd())
640 cell
= module
->addLt(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
641 else if (net_cin
->IsPwr())
642 cell
= module
->addLe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
644 log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst
->Name());
645 import_attributes(cell
->attributes
, inst
);
649 if (inst
->Type() == OPER_WIDE_AND
) {
650 cell
= module
->addAnd(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
651 import_attributes(cell
->attributes
, inst
);
655 if (inst
->Type() == OPER_WIDE_OR
) {
656 cell
= module
->addOr(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
657 import_attributes(cell
->attributes
, inst
);
661 if (inst
->Type() == OPER_WIDE_XOR
) {
662 cell
= module
->addXor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
663 import_attributes(cell
->attributes
, inst
);
667 if (inst
->Type() == OPER_WIDE_XNOR
) {
668 cell
= module
->addXnor(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
669 import_attributes(cell
->attributes
, inst
);
673 if (inst
->Type() == OPER_WIDE_BUF
) {
674 cell
= module
->addPos(inst_name
, IN
, FILTERED_OUT
, SIGNED
);
675 import_attributes(cell
->attributes
, inst
);
679 if (inst
->Type() == OPER_WIDE_INV
) {
680 cell
= module
->addNot(inst_name
, IN
, OUT
, SIGNED
);
681 import_attributes(cell
->attributes
, inst
);
685 if (inst
->Type() == OPER_MINUS
) {
686 cell
= module
->addSub(inst_name
, IN1
, IN2
, OUT
, SIGNED
);
687 import_attributes(cell
->attributes
, inst
);
691 if (inst
->Type() == OPER_UMINUS
) {
692 cell
= module
->addNeg(inst_name
, IN
, OUT
, SIGNED
);
693 import_attributes(cell
->attributes
, inst
);
697 if (inst
->Type() == OPER_EQUAL
) {
698 cell
= module
->addEq(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
699 import_attributes(cell
->attributes
, inst
);
703 if (inst
->Type() == OPER_NEQUAL
) {
704 cell
= module
->addNe(inst_name
, IN1
, IN2
, net_map_at(inst
->GetOutput()), SIGNED
);
705 import_attributes(cell
->attributes
, inst
);
709 if (inst
->Type() == OPER_WIDE_MUX
) {
710 cell
= module
->addMux(inst_name
, IN1
, IN2
, net_map_at(inst
->GetControl()), OUT
);
711 import_attributes(cell
->attributes
, inst
);
715 if (inst
->Type() == OPER_NTO1MUX
) {
716 cell
= module
->addShr(inst_name
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
717 import_attributes(cell
->attributes
, inst
);
721 if (inst
->Type() == OPER_WIDE_NTO1MUX
)
723 SigSpec data
= IN2
, out
= OUT
;
725 int wordsize_bits
= ceil_log2(GetSize(out
));
726 int wordsize
= 1 << wordsize_bits
;
728 SigSpec sel
= {IN1
, SigSpec(State::S0
, wordsize_bits
)};
731 for (int i
= 0; i
< GetSize(data
); i
+= GetSize(out
)) {
732 SigSpec d
= data
.extract(i
, GetSize(out
));
733 d
.extend_u0(wordsize
);
734 padded_data
.append(d
);
737 cell
= module
->addShr(inst_name
, padded_data
, sel
, out
);
738 import_attributes(cell
->attributes
, inst
);
742 if (inst
->Type() == OPER_SELECTOR
)
744 cell
= module
->addPmux(inst_name
, State::S0
, IN2
, IN1
, net_map_at(inst
->GetOutput()));
745 import_attributes(cell
->attributes
, inst
);
749 if (inst
->Type() == OPER_WIDE_SELECTOR
)
752 cell
= module
->addPmux(inst_name
, SigSpec(State::S0
, GetSize(out
)), IN2
, IN1
, out
);
753 import_attributes(cell
->attributes
, inst
);
757 if (inst
->Type() == OPER_WIDE_TRI
) {
758 cell
= module
->addMux(inst_name
, RTLIL::SigSpec(RTLIL::State::Sz
, inst
->OutputSize()), IN
, net_map_at(inst
->GetControl()), OUT
);
759 import_attributes(cell
->attributes
, inst
);
763 if (inst
->Type() == OPER_WIDE_DFFRS
)
765 VerificClocking
clocking(this, inst
->GetClock());
766 log_assert(clocking
.disable_sig
== State::S0
);
767 log_assert(clocking
.body_net
== nullptr);
769 RTLIL::SigSpec sig_set
= operatorInport(inst
, "set");
770 RTLIL::SigSpec sig_reset
= operatorInport(inst
, "reset");
772 if (sig_set
.is_fully_const() && !sig_set
.as_bool() && sig_reset
.is_fully_const() && !sig_reset
.as_bool())
773 cell
= clocking
.addDff(inst_name
, IN
, OUT
);
775 cell
= clocking
.addDffsr(inst_name
, sig_set
, sig_reset
, IN
, OUT
);
776 import_attributes(cell
->attributes
, inst
);
790 void VerificImporter::merge_past_ffs_clock(pool
<RTLIL::Cell
*> &candidates
, SigBit clock
, bool clock_pol
)
792 bool keep_running
= true;
797 keep_running
= false;
799 dict
<SigBit
, pool
<RTLIL::Cell
*>> dbits_db
;
802 for (auto cell
: candidates
) {
803 SigBit bit
= sigmap(cell
->getPort(ID::D
));
804 dbits_db
[bit
].insert(cell
);
808 dbits
.sort_and_unify();
810 for (auto chunk
: dbits
.chunks())
812 SigSpec sig_d
= chunk
;
814 if (chunk
.wire
== nullptr || GetSize(sig_d
) == 1)
817 SigSpec sig_q
= module
->addWire(NEW_ID
, GetSize(sig_d
));
818 RTLIL::Cell
*new_ff
= module
->addDff(NEW_ID
, clock
, sig_d
, sig_q
, clock_pol
);
821 log(" merging single-bit past_ffs into new %d-bit ff %s.\n", GetSize(sig_d
), log_id(new_ff
));
823 for (int i
= 0; i
< GetSize(sig_d
); i
++)
824 for (auto old_ff
: dbits_db
[sig_d
[i
]])
827 log(" replacing old ff %s on bit %d.\n", log_id(old_ff
), i
);
829 SigBit old_q
= old_ff
->getPort(ID::Q
);
830 SigBit new_q
= sig_q
[i
];
832 sigmap
.add(old_q
, new_q
);
833 module
->connect(old_q
, new_q
);
834 candidates
.erase(old_ff
);
835 module
->remove(old_ff
);
842 void VerificImporter::merge_past_ffs(pool
<RTLIL::Cell
*> &candidates
)
844 dict
<pair
<SigBit
, int>, pool
<RTLIL::Cell
*>> database
;
846 for (auto cell
: candidates
)
848 SigBit clock
= cell
->getPort(ID::CLK
);
849 bool clock_pol
= cell
->getParam(ID::CLK_POLARITY
).as_bool();
850 database
[make_pair(clock
, int(clock_pol
))].insert(cell
);
853 for (auto it
: database
)
854 merge_past_ffs_clock(it
.second
, it
.first
.first
, it
.first
.second
);
857 void VerificImporter::import_netlist(RTLIL::Design
*design
, Netlist
*nl
, std::set
<Netlist
*> &nl_todo
, bool norename
)
859 std::string netlist_name
= nl
->GetAtt(" \\top") ? nl
->CellBaseName() : nl
->Owner()->Name();
860 std::string module_name
= netlist_name
;
862 if (nl
->IsOperator() || nl
->IsPrimitive()) {
863 module_name
= "$verific$" + module_name
;
865 if (!norename
&& *nl
->Name()) {
867 module_name
+= nl
->Name();
870 module_name
= "\\" + module_name
;
875 if (design
->has(module_name
)) {
876 if (!nl
->IsOperator() && !is_blackbox(nl
))
877 log_cmd_error("Re-definition of module `%s'.\n", netlist_name
.c_str());
881 module
= new RTLIL::Module
;
882 module
->name
= module_name
;
885 if (is_blackbox(nl
)) {
886 log("Importing blackbox module %s.\n", RTLIL::id2cstr(module
->name
));
887 module
->set_bool_attribute(ID::blackbox
);
889 log("Importing module %s.\n", RTLIL::id2cstr(module
->name
));
901 FOREACH_PORT_OF_NETLIST(nl
, mi
, port
)
907 log(" importing port %s.\n", port
->Name());
909 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(port
->Name()));
910 import_attributes(wire
->attributes
, port
, nl
);
912 wire
->port_id
= nl
->IndexOf(port
) + 1;
914 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_IN
)
915 wire
->port_input
= true;
916 if (port
->GetDir() == DIR_INOUT
|| port
->GetDir() == DIR_OUT
)
917 wire
->port_output
= true;
919 if (port
->GetNet()) {
920 net
= port
->GetNet();
921 if (net_map
.count(net
) == 0)
923 else if (wire
->port_input
)
924 module
->connect(net_map_at(net
), wire
);
926 module
->connect(wire
, net_map_at(net
));
930 FOREACH_PORTBUS_OF_NETLIST(nl
, mi
, portbus
)
933 log(" importing portbus %s.\n", portbus
->Name());
935 RTLIL::Wire
*wire
= module
->addWire(RTLIL::escape_id(portbus
->Name()), portbus
->Size());
936 wire
->start_offset
= min(portbus
->LeftIndex(), portbus
->RightIndex());
937 import_attributes(wire
->attributes
, portbus
, nl
);
939 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_IN
)
940 wire
->port_input
= true;
941 if (portbus
->GetDir() == DIR_INOUT
|| portbus
->GetDir() == DIR_OUT
)
942 wire
->port_output
= true;
944 for (int i
= portbus
->LeftIndex();; i
+= portbus
->IsUp() ? +1 : -1) {
945 if (portbus
->ElementAtIndex(i
) && portbus
->ElementAtIndex(i
)->GetNet()) {
946 net
= portbus
->ElementAtIndex(i
)->GetNet();
947 RTLIL::SigBit
bit(wire
, i
- wire
->start_offset
);
948 if (net_map
.count(net
) == 0)
950 else if (wire
->port_input
)
951 module
->connect(net_map_at(net
), bit
);
953 module
->connect(bit
, net_map_at(net
));
955 if (i
== portbus
->RightIndex())
960 module
->fixup_ports();
962 dict
<Net
*, char, hash_ptr_ops
> init_nets
;
963 pool
<Net
*, hash_ptr_ops
> anyconst_nets
, anyseq_nets
;
964 pool
<Net
*, hash_ptr_ops
> allconst_nets
, allseq_nets
;
965 any_all_nets
.clear();
967 FOREACH_NET_OF_NETLIST(nl
, mi
, net
)
971 RTLIL::Memory
*memory
= new RTLIL::Memory
;
972 memory
->name
= RTLIL::escape_id(net
->Name());
973 log_assert(module
->count_id(memory
->name
) == 0);
974 module
->memories
[memory
->name
] = memory
;
976 int number_of_bits
= net
->Size();
977 number_of_bits
= 1 << ceil_log2(number_of_bits
);
978 int bits_in_word
= number_of_bits
;
979 FOREACH_PORTREF_OF_NET(net
, si
, pr
) {
980 if (pr
->GetInst()->Type() == OPER_READ_PORT
) {
981 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->OutputSize());
984 if (pr
->GetInst()->Type() == OPER_WRITE_PORT
|| pr
->GetInst()->Type() == OPER_CLOCKED_WRITE_PORT
) {
985 bits_in_word
= min
<int>(bits_in_word
, pr
->GetInst()->Input2Size());
988 log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
989 net
->Name(), pr
->GetInst()->View()->Owner()->Name(), pr
->GetInst()->Name());
992 memory
->width
= bits_in_word
;
993 memory
->size
= number_of_bits
/ bits_in_word
;
995 const char *ascii_initdata
= net
->GetWideInitialValue();
996 if (ascii_initdata
) {
997 while (*ascii_initdata
!= 0 && *ascii_initdata
!= '\'')
999 if (*ascii_initdata
== '\'')
1001 if (*ascii_initdata
!= 0) {
1002 log_assert(*ascii_initdata
== 'b');
1005 for (int word_idx
= 0; word_idx
< memory
->size
; word_idx
++) {
1006 Const initval
= Const(State::Sx
, memory
->width
);
1007 bool initval_valid
= false;
1008 for (int bit_idx
= memory
->width
-1; bit_idx
>= 0; bit_idx
--) {
1009 if (*ascii_initdata
== 0)
1011 if (*ascii_initdata
== '0' || *ascii_initdata
== '1') {
1012 initval
[bit_idx
] = (*ascii_initdata
== '0') ? State::S0
: State::S1
;
1013 initval_valid
= true;
1017 if (initval_valid
) {
1018 RTLIL::Cell
*cell
= module
->addCell(new_verific_id(net
), ID($meminit
));
1019 cell
->parameters
[ID::WORDS
] = 1;
1020 if (net
->GetOrigTypeRange()->LeftRangeBound() < net
->GetOrigTypeRange()->RightRangeBound())
1021 cell
->setPort(ID::ADDR
, word_idx
);
1023 cell
->setPort(ID::ADDR
, memory
->size
- word_idx
- 1);
1024 cell
->setPort(ID::DATA
, initval
);
1025 cell
->parameters
[ID::MEMID
] = RTLIL::Const(memory
->name
.str());
1026 cell
->parameters
[ID::ABITS
] = 32;
1027 cell
->parameters
[ID::WIDTH
] = memory
->width
;
1028 cell
->parameters
[ID::PRIORITY
] = RTLIL::Const(autoidx
-1);
1035 if (net
->GetInitialValue())
1036 init_nets
[net
] = net
->GetInitialValue();
1038 const char *rand_const_attr
= net
->GetAttValue(" rand_const");
1039 const char *rand_attr
= net
->GetAttValue(" rand");
1041 const char *anyconst_attr
= net
->GetAttValue("anyconst");
1042 const char *anyseq_attr
= net
->GetAttValue("anyseq");
1044 const char *allconst_attr
= net
->GetAttValue("allconst");
1045 const char *allseq_attr
= net
->GetAttValue("allseq");
1047 if (rand_const_attr
!= nullptr && (!strcmp(rand_const_attr
, "1") || !strcmp(rand_const_attr
, "'1'"))) {
1048 anyconst_nets
.insert(net
);
1049 any_all_nets
.insert(net
);
1051 else if (rand_attr
!= nullptr && (!strcmp(rand_attr
, "1") || !strcmp(rand_attr
, "'1'"))) {
1052 anyseq_nets
.insert(net
);
1053 any_all_nets
.insert(net
);
1055 else if (anyconst_attr
!= nullptr && (!strcmp(anyconst_attr
, "1") || !strcmp(anyconst_attr
, "'1'"))) {
1056 anyconst_nets
.insert(net
);
1057 any_all_nets
.insert(net
);
1059 else if (anyseq_attr
!= nullptr && (!strcmp(anyseq_attr
, "1") || !strcmp(anyseq_attr
, "'1'"))) {
1060 anyseq_nets
.insert(net
);
1061 any_all_nets
.insert(net
);
1063 else if (allconst_attr
!= nullptr && (!strcmp(allconst_attr
, "1") || !strcmp(allconst_attr
, "'1'"))) {
1064 allconst_nets
.insert(net
);
1065 any_all_nets
.insert(net
);
1067 else if (allseq_attr
!= nullptr && (!strcmp(allseq_attr
, "1") || !strcmp(allseq_attr
, "'1'"))) {
1068 allseq_nets
.insert(net
);
1069 any_all_nets
.insert(net
);
1072 if (net_map
.count(net
)) {
1073 if (verific_verbose
)
1074 log(" skipping net %s.\n", net
->Name());
1081 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| net
->IsUserDeclared() ? RTLIL::escape_id(net
->Name()) : new_verific_id(net
));
1083 if (verific_verbose
)
1084 log(" importing net %s as %s.\n", net
->Name(), log_id(wire_name
));
1086 RTLIL::Wire
*wire
= module
->addWire(wire_name
);
1087 import_attributes(wire
->attributes
, net
, nl
);
1089 net_map
[net
] = wire
;
1092 FOREACH_NETBUS_OF_NETLIST(nl
, mi
, netbus
)
1094 bool found_new_net
= false;
1095 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1) {
1096 net
= netbus
->ElementAtIndex(i
);
1097 if (net_map
.count(net
) == 0)
1098 found_new_net
= true;
1099 if (i
== netbus
->RightIndex())
1105 RTLIL::IdString wire_name
= module
->uniquify(mode_names
|| netbus
->IsUserDeclared() ? RTLIL::escape_id(netbus
->Name()) : new_verific_id(netbus
));
1107 if (verific_verbose
)
1108 log(" importing netbus %s as %s.\n", netbus
->Name(), log_id(wire_name
));
1110 RTLIL::Wire
*wire
= module
->addWire(wire_name
, netbus
->Size());
1111 wire
->start_offset
= min(netbus
->LeftIndex(), netbus
->RightIndex());
1112 import_attributes(wire
->attributes
, netbus
, nl
);
1114 RTLIL::Const initval
= Const(State::Sx
, GetSize(wire
));
1115 bool initval_valid
= false;
1117 for (int i
= netbus
->LeftIndex();; i
+= netbus
->IsUp() ? +1 : -1)
1119 if (netbus
->ElementAtIndex(i
))
1121 int bitidx
= i
- wire
->start_offset
;
1122 net
= netbus
->ElementAtIndex(i
);
1123 RTLIL::SigBit
bit(wire
, bitidx
);
1125 if (init_nets
.count(net
)) {
1126 if (init_nets
.at(net
) == '0')
1127 initval
.bits
.at(bitidx
) = State::S0
;
1128 if (init_nets
.at(net
) == '1')
1129 initval
.bits
.at(bitidx
) = State::S1
;
1130 initval_valid
= true;
1131 init_nets
.erase(net
);
1134 if (net_map
.count(net
) == 0)
1137 module
->connect(bit
, net_map_at(net
));
1140 if (i
== netbus
->RightIndex())
1145 wire
->attributes
[ID::init
] = initval
;
1149 if (verific_verbose
)
1150 log(" skipping netbus %s.\n", netbus
->Name());
1153 SigSpec anyconst_sig
;
1155 SigSpec allconst_sig
;
1158 for (int i
= netbus
->RightIndex();; i
+= netbus
->IsUp() ? -1 : +1) {
1159 net
= netbus
->ElementAtIndex(i
);
1160 if (net
!= nullptr && anyconst_nets
.count(net
)) {
1161 anyconst_sig
.append(net_map_at(net
));
1162 anyconst_nets
.erase(net
);
1164 if (net
!= nullptr && anyseq_nets
.count(net
)) {
1165 anyseq_sig
.append(net_map_at(net
));
1166 anyseq_nets
.erase(net
);
1168 if (net
!= nullptr && allconst_nets
.count(net
)) {
1169 allconst_sig
.append(net_map_at(net
));
1170 allconst_nets
.erase(net
);
1172 if (net
!= nullptr && allseq_nets
.count(net
)) {
1173 allseq_sig
.append(net_map_at(net
));
1174 allseq_nets
.erase(net
);
1176 if (i
== netbus
->LeftIndex())
1180 if (GetSize(anyconst_sig
))
1181 module
->connect(anyconst_sig
, module
->Anyconst(new_verific_id(netbus
), GetSize(anyconst_sig
)));
1183 if (GetSize(anyseq_sig
))
1184 module
->connect(anyseq_sig
, module
->Anyseq(new_verific_id(netbus
), GetSize(anyseq_sig
)));
1186 if (GetSize(allconst_sig
))
1187 module
->connect(allconst_sig
, module
->Allconst(new_verific_id(netbus
), GetSize(allconst_sig
)));
1189 if (GetSize(allseq_sig
))
1190 module
->connect(allseq_sig
, module
->Allseq(new_verific_id(netbus
), GetSize(allseq_sig
)));
1193 for (auto it
: init_nets
)
1196 SigBit bit
= net_map_at(it
.first
);
1197 log_assert(bit
.wire
);
1199 if (bit
.wire
->attributes
.count(ID::init
))
1200 initval
= bit
.wire
->attributes
.at(ID::init
);
1202 while (GetSize(initval
) < GetSize(bit
.wire
))
1203 initval
.bits
.push_back(State::Sx
);
1205 if (it
.second
== '0')
1206 initval
.bits
.at(bit
.offset
) = State::S0
;
1207 if (it
.second
== '1')
1208 initval
.bits
.at(bit
.offset
) = State::S1
;
1210 bit
.wire
->attributes
[ID::init
] = initval
;
1213 for (auto net
: anyconst_nets
)
1214 module
->connect(net_map_at(net
), module
->Anyconst(new_verific_id(net
)));
1216 for (auto net
: anyseq_nets
)
1217 module
->connect(net_map_at(net
), module
->Anyseq(new_verific_id(net
)));
1219 pool
<Instance
*, hash_ptr_ops
> sva_asserts
;
1220 pool
<Instance
*, hash_ptr_ops
> sva_assumes
;
1221 pool
<Instance
*, hash_ptr_ops
> sva_covers
;
1222 pool
<Instance
*, hash_ptr_ops
> sva_triggers
;
1224 pool
<RTLIL::Cell
*> past_ffs
;
1226 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1228 RTLIL::IdString inst_name
= module
->uniquify(mode_names
|| inst
->IsUserDeclared() ? RTLIL::escape_id(inst
->Name()) : new_verific_id(inst
));
1230 if (verific_verbose
)
1231 log(" importing cell %s (%s) as %s.\n", inst
->Name(), inst
->View()->Owner()->Name(), log_id(inst_name
));
1234 goto import_verific_cells
;
1236 if (inst
->Type() == PRIM_PWR
) {
1237 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S1
);
1241 if (inst
->Type() == PRIM_GND
) {
1242 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::S0
);
1246 if (inst
->Type() == PRIM_BUF
) {
1247 auto outnet
= inst
->GetOutput();
1248 if (!any_all_nets
.count(outnet
))
1249 module
->addBufGate(inst_name
, net_map_at(inst
->GetInput()), net_map_at(outnet
));
1253 if (inst
->Type() == PRIM_X
) {
1254 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sx
);
1258 if (inst
->Type() == PRIM_Z
) {
1259 module
->connect(net_map_at(inst
->GetOutput()), RTLIL::State::Sz
);
1263 if (inst
->Type() == OPER_READ_PORT
)
1265 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetInput()->Name()), nullptr);
1267 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst
->GetInput()->Name());
1269 int numchunks
= int(inst
->OutputSize()) / memory
->width
;
1270 int chunksbits
= ceil_log2(numchunks
);
1272 for (int i
= 0; i
< numchunks
; i
++)
1274 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1275 RTLIL::SigSpec data
= operatorOutput(inst
).extract(i
* memory
->width
, memory
->width
);
1277 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1278 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), ID($memrd
));
1279 cell
->parameters
[ID::MEMID
] = memory
->name
.str();
1280 cell
->parameters
[ID::CLK_ENABLE
] = false;
1281 cell
->parameters
[ID::CLK_POLARITY
] = true;
1282 cell
->parameters
[ID::TRANSPARENT
] = false;
1283 cell
->parameters
[ID::ABITS
] = GetSize(addr
);
1284 cell
->parameters
[ID::WIDTH
] = GetSize(data
);
1285 cell
->setPort(ID::CLK
, RTLIL::State::Sx
);
1286 cell
->setPort(ID::EN
, RTLIL::State::Sx
);
1287 cell
->setPort(ID::ADDR
, addr
);
1288 cell
->setPort(ID::DATA
, data
);
1293 if (inst
->Type() == OPER_WRITE_PORT
|| inst
->Type() == OPER_CLOCKED_WRITE_PORT
)
1295 RTLIL::Memory
*memory
= module
->memories
.at(RTLIL::escape_id(inst
->GetOutput()->Name()), nullptr);
1297 log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst
->GetInput()->Name());
1298 int numchunks
= int(inst
->Input2Size()) / memory
->width
;
1299 int chunksbits
= ceil_log2(numchunks
);
1301 for (int i
= 0; i
< numchunks
; i
++)
1303 RTLIL::SigSpec addr
= {operatorInput1(inst
), RTLIL::Const(i
, chunksbits
)};
1304 RTLIL::SigSpec data
= operatorInput2(inst
).extract(i
* memory
->width
, memory
->width
);
1306 RTLIL::Cell
*cell
= module
->addCell(numchunks
== 1 ? inst_name
:
1307 RTLIL::IdString(stringf("%s_%d", inst_name
.c_str(), i
)), ID($memwr
));
1308 cell
->parameters
[ID::MEMID
] = memory
->name
.str();
1309 cell
->parameters
[ID::CLK_ENABLE
] = false;
1310 cell
->parameters
[ID::CLK_POLARITY
] = true;
1311 cell
->parameters
[ID::PRIORITY
] = 0;
1312 cell
->parameters
[ID::ABITS
] = GetSize(addr
);
1313 cell
->parameters
[ID::WIDTH
] = GetSize(data
);
1314 cell
->setPort(ID::EN
, RTLIL::SigSpec(net_map_at(inst
->GetControl())).repeat(GetSize(data
)));
1315 cell
->setPort(ID::CLK
, RTLIL::State::S0
);
1316 cell
->setPort(ID::ADDR
, addr
);
1317 cell
->setPort(ID::DATA
, data
);
1319 if (inst
->Type() == OPER_CLOCKED_WRITE_PORT
) {
1320 cell
->parameters
[ID::CLK_ENABLE
] = true;
1321 cell
->setPort(ID::CLK
, net_map_at(inst
->GetClock()));
1328 if (import_netlist_instance_cells(inst
, inst_name
))
1330 if (inst
->IsOperator() && !verific_sva_prims
.count(inst
->Type()))
1331 log_warning("Unsupported Verific operator: %s (fallback to gate level implementation provided by verific)\n", inst
->View()->Owner()->Name());
1333 if (import_netlist_instance_gates(inst
, inst_name
))
1337 if (inst
->Type() == PRIM_SVA_ASSERT
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSERT
)
1338 sva_asserts
.insert(inst
);
1340 if (inst
->Type() == PRIM_SVA_ASSUME
|| inst
->Type() == PRIM_SVA_IMMEDIATE_ASSUME
|| inst
->Type() == PRIM_SVA_RESTRICT
)
1341 sva_assumes
.insert(inst
);
1343 if (inst
->Type() == PRIM_SVA_COVER
|| inst
->Type() == PRIM_SVA_IMMEDIATE_COVER
)
1344 sva_covers
.insert(inst
);
1346 if (inst
->Type() == PRIM_SVA_TRIGGERED
)
1347 sva_triggers
.insert(inst
);
1349 if (inst
->Type() == OPER_SVA_STABLE
)
1351 VerificClocking
clocking(this, inst
->GetInput2Bit(0));
1352 log_assert(clocking
.disable_sig
== State::S0
);
1353 log_assert(clocking
.body_net
== nullptr);
1355 log_assert(inst
->Input1Size() == inst
->OutputSize());
1357 SigSpec sig_d
, sig_q
, sig_o
;
1358 sig_q
= module
->addWire(new_verific_id(inst
), inst
->Input1Size());
1360 for (int i
= int(inst
->Input1Size())-1; i
>= 0; i
--){
1361 sig_d
.append(net_map_at(inst
->GetInput1Bit(i
)));
1362 sig_o
.append(net_map_at(inst
->GetOutputBit(i
)));
1365 if (verific_verbose
) {
1366 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1367 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1368 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1369 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1372 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1373 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1379 if (inst
->Type() == PRIM_SVA_STABLE
)
1381 VerificClocking
clocking(this, inst
->GetInput2());
1382 log_assert(clocking
.disable_sig
== State::S0
);
1383 log_assert(clocking
.body_net
== nullptr);
1385 SigSpec sig_d
= net_map_at(inst
->GetInput1());
1386 SigSpec sig_o
= net_map_at(inst
->GetOutput());
1387 SigSpec sig_q
= module
->addWire(new_verific_id(inst
));
1389 if (verific_verbose
) {
1390 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1391 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1392 log(" XNOR with A=%s, B=%s, Y=%s.\n",
1393 log_signal(sig_d
), log_signal(sig_q
), log_signal(sig_o
));
1396 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1397 module
->addXnor(new_verific_id(inst
), sig_d
, sig_q
, sig_o
);
1403 if (inst
->Type() == PRIM_SVA_PAST
)
1405 VerificClocking
clocking(this, inst
->GetInput2());
1406 log_assert(clocking
.disable_sig
== State::S0
);
1407 log_assert(clocking
.body_net
== nullptr);
1409 SigBit sig_d
= net_map_at(inst
->GetInput1());
1410 SigBit sig_q
= net_map_at(inst
->GetOutput());
1412 if (verific_verbose
)
1413 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1414 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1416 past_ffs
.insert(clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
));
1422 if ((inst
->Type() == PRIM_SVA_ROSE
|| inst
->Type() == PRIM_SVA_FELL
))
1424 VerificClocking
clocking(this, inst
->GetInput2());
1425 log_assert(clocking
.disable_sig
== State::S0
);
1426 log_assert(clocking
.body_net
== nullptr);
1428 SigBit sig_d
= net_map_at(inst
->GetInput1());
1429 SigBit sig_o
= net_map_at(inst
->GetOutput());
1430 SigBit sig_q
= module
->addWire(new_verific_id(inst
));
1432 if (verific_verbose
)
1433 log(" %sedge FF with D=%s, Q=%s, C=%s.\n", clocking
.posedge
? "pos" : "neg",
1434 log_signal(sig_d
), log_signal(sig_q
), log_signal(clocking
.clock_sig
));
1436 clocking
.addDff(new_verific_id(inst
), sig_d
, sig_q
);
1437 module
->addEq(new_verific_id(inst
), {sig_q
, sig_d
}, Const(inst
->Type() == PRIM_SVA_ROSE
? 1 : 2, 2), sig_o
);
1443 if (!mode_keep
&& verific_sva_prims
.count(inst
->Type())) {
1444 if (verific_verbose
)
1445 log(" skipping SVA cell in non k-mode\n");
1449 if (inst
->Type() == PRIM_HDL_ASSERTION
)
1451 SigBit cond
= net_map_at(inst
->GetInput());
1453 if (verific_verbose
)
1454 log(" assert condition %s.\n", log_signal(cond
));
1456 const char *assume_attr
= nullptr; // inst->GetAttValue("assume");
1458 Cell
*cell
= nullptr;
1459 if (assume_attr
!= nullptr && !strcmp(assume_attr
, "1"))
1460 cell
= module
->addAssume(new_verific_id(inst
), cond
, State::S1
);
1462 cell
= module
->addAssert(new_verific_id(inst
), cond
, State::S1
);
1464 import_attributes(cell
->attributes
, inst
);
1468 if (inst
->IsPrimitive())
1471 log_error("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1473 if (!verific_sva_prims
.count(inst
->Type()))
1474 log_warning("Unsupported Verific primitive %s of type %s\n", inst
->Name(), inst
->View()->Owner()->Name());
1477 import_verific_cells
:
1478 nl_todo
.insert(inst
->View());
1480 std::string inst_type
= inst
->View()->Owner()->Name();
1482 if (inst
->View()->IsOperator() || inst
->View()->IsPrimitive()) {
1483 inst_type
= "$verific$" + inst_type
;
1485 if (*inst
->View()->Name()) {
1487 inst_type
+= inst
->View()->Name();
1490 inst_type
= "\\" + inst_type
;
1493 RTLIL::Cell
*cell
= module
->addCell(inst_name
, inst_type
);
1495 if (inst
->IsPrimitive() && mode_keep
)
1496 cell
->attributes
[ID::keep
] = 1;
1498 dict
<IdString
, vector
<SigBit
>> cell_port_conns
;
1500 if (verific_verbose
)
1501 log(" ports in verific db:\n");
1503 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
) {
1504 if (verific_verbose
)
1505 log(" .%s(%s)\n", pr
->GetPort()->Name(), pr
->GetNet()->Name());
1506 const char *port_name
= pr
->GetPort()->Name();
1507 int port_offset
= 0;
1508 if (pr
->GetPort()->Bus()) {
1509 port_name
= pr
->GetPort()->Bus()->Name();
1510 port_offset
= pr
->GetPort()->Bus()->IndexOf(pr
->GetPort()) -
1511 min(pr
->GetPort()->Bus()->LeftIndex(), pr
->GetPort()->Bus()->RightIndex());
1513 IdString port_name_id
= RTLIL::escape_id(port_name
);
1514 auto &sigvec
= cell_port_conns
[port_name_id
];
1515 if (GetSize(sigvec
) <= port_offset
) {
1516 SigSpec zwires
= module
->addWire(new_verific_id(inst
), port_offset
+1-GetSize(sigvec
));
1517 for (auto bit
: zwires
)
1518 sigvec
.push_back(bit
);
1520 sigvec
[port_offset
] = net_map_at(pr
->GetNet());
1523 if (verific_verbose
)
1524 log(" ports in yosys db:\n");
1526 for (auto &it
: cell_port_conns
) {
1527 if (verific_verbose
)
1528 log(" .%s(%s)\n", log_id(it
.first
), log_signal(it
.second
));
1529 cell
->setPort(it
.first
, it
.second
);
1535 for (auto inst
: sva_asserts
) {
1537 verific_import_sva_cover(this, inst
);
1538 verific_import_sva_assert(this, inst
);
1541 for (auto inst
: sva_assumes
)
1542 verific_import_sva_assume(this, inst
);
1544 for (auto inst
: sva_covers
)
1545 verific_import_sva_cover(this, inst
);
1547 for (auto inst
: sva_triggers
)
1548 verific_import_sva_trigger(this, inst
);
1550 merge_past_ffs(past_ffs
);
1555 pool
<SigBit
> non_ff_bits
;
1558 ff_types
.setup_internals_ff();
1559 ff_types
.setup_stdcells_mem();
1561 for (auto cell
: module
->cells())
1563 if (ff_types
.cell_known(cell
->type
))
1566 for (auto conn
: cell
->connections())
1568 if (!cell
->output(conn
.first
))
1571 for (auto bit
: conn
.second
)
1572 if (bit
.wire
!= nullptr)
1573 non_ff_bits
.insert(bit
);
1577 for (auto wire
: module
->wires())
1579 if (!wire
->attributes
.count(ID::init
))
1582 Const
&initval
= wire
->attributes
.at(ID::init
);
1583 for (int i
= 0; i
< GetSize(initval
); i
++)
1585 if (initval
[i
] != State::S0
&& initval
[i
] != State::S1
)
1588 if (non_ff_bits
.count(SigBit(wire
, i
)))
1589 initval
[i
] = State::Sx
;
1592 if (initval
.is_fully_undef())
1593 wire
->attributes
.erase(ID::init
);
1598 // ==================================================================
1600 VerificClocking::VerificClocking(VerificImporter
*importer
, Net
*net
, bool sva_at_only
)
1602 module
= importer
->module
;
1604 log_assert(importer
!= nullptr);
1605 log_assert(net
!= nullptr);
1607 Instance
*inst
= net
->Driver();
1609 if (inst
!= nullptr && inst
->Type() == PRIM_SVA_AT
)
1611 net
= inst
->GetInput1();
1612 body_net
= inst
->GetInput2();
1614 inst
= net
->Driver();
1616 Instance
*body_inst
= body_net
->Driver();
1617 if (body_inst
!= nullptr && body_inst
->Type() == PRIM_SVA_DISABLE_IFF
) {
1618 disable_net
= body_inst
->GetInput1();
1619 disable_sig
= importer
->net_map_at(disable_net
);
1620 body_net
= body_inst
->GetInput2();
1629 // Use while() instead of if() to work around VIPER #13453
1630 while (inst
!= nullptr && inst
->Type() == PRIM_SVA_POSEDGE
)
1632 net
= inst
->GetInput();
1633 inst
= net
->Driver();;
1636 if (inst
!= nullptr && inst
->Type() == PRIM_INV
)
1638 net
= inst
->GetInput();
1639 inst
= net
->Driver();;
1643 // Detect clock-enable circuit
1645 if (inst
== nullptr || inst
->Type() != PRIM_AND
)
1648 Net
*net_dlatch
= inst
->GetInput1();
1649 Instance
*inst_dlatch
= net_dlatch
->Driver();
1651 if (inst_dlatch
== nullptr || inst_dlatch
->Type() != PRIM_DLATCHRS
)
1654 if (!inst_dlatch
->GetSet()->IsGnd() || !inst_dlatch
->GetReset()->IsGnd())
1657 Net
*net_enable
= inst_dlatch
->GetInput();
1658 Net
*net_not_clock
= inst_dlatch
->GetControl();
1660 if (net_enable
== nullptr || net_not_clock
== nullptr)
1663 Instance
*inst_not_clock
= net_not_clock
->Driver();
1665 if (inst_not_clock
== nullptr || inst_not_clock
->Type() != PRIM_INV
)
1668 Net
*net_clock1
= inst_not_clock
->GetInput();
1669 Net
*net_clock2
= inst
->GetInput2();
1671 if (net_clock1
== nullptr || net_clock1
!= net_clock2
)
1674 enable_net
= net_enable
;
1675 enable_sig
= importer
->net_map_at(enable_net
);
1678 inst
= net
->Driver();;
1681 // Detect condition expression
1683 if (body_net
== nullptr)
1686 Instance
*inst_mux
= body_net
->Driver();
1688 if (inst_mux
== nullptr || inst_mux
->Type() != PRIM_MUX
)
1691 if (!inst_mux
->GetInput1()->IsPwr())
1694 Net
*sva_net
= inst_mux
->GetInput2();
1695 if (!verific_is_sva_net(importer
, sva_net
))
1699 cond_net
= inst_mux
->GetControl();
1703 clock_sig
= importer
->net_map_at(clock_net
);
1705 const char *gclk_attr
= clock_net
->GetAttValue("gclk");
1706 if (gclk_attr
!= nullptr && (!strcmp(gclk_attr
, "1") || !strcmp(gclk_attr
, "'1'")))
1710 Cell
*VerificClocking::addDff(IdString name
, SigSpec sig_d
, SigSpec sig_q
, Const init_value
)
1712 log_assert(GetSize(sig_d
) == GetSize(sig_q
));
1714 if (GetSize(init_value
) != 0) {
1715 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1716 if (sig_q
.is_wire()) {
1717 sig_q
.as_wire()->attributes
[ID::init
] = init_value
;
1719 Wire
*w
= module
->addWire(NEW_ID
, GetSize(sig_q
));
1720 w
->attributes
[ID::init
] = init_value
;
1721 module
->connect(sig_q
, w
);
1726 if (enable_sig
!= State::S1
)
1727 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1729 if (disable_sig
!= State::S0
) {
1730 log_assert(gclk
== false);
1731 log_assert(GetSize(sig_q
) == GetSize(init_value
));
1732 return module
->addAdff(name
, clock_sig
, disable_sig
, sig_d
, sig_q
, init_value
, posedge
);
1736 return module
->addFf(name
, sig_d
, sig_q
);
1738 return module
->addDff(name
, clock_sig
, sig_d
, sig_q
, posedge
);
1741 Cell
*VerificClocking::addAdff(IdString name
, RTLIL::SigSpec sig_arst
, SigSpec sig_d
, SigSpec sig_q
, Const arst_value
)
1743 log_assert(gclk
== false);
1744 log_assert(disable_sig
== State::S0
);
1746 if (enable_sig
!= State::S1
)
1747 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1749 return module
->addAdff(name
, clock_sig
, sig_arst
, sig_d
, sig_q
, arst_value
, posedge
);
1752 Cell
*VerificClocking::addDffsr(IdString name
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_clr
, SigSpec sig_d
, SigSpec sig_q
)
1754 log_assert(gclk
== false);
1755 log_assert(disable_sig
== State::S0
);
1757 if (enable_sig
!= State::S1
)
1758 sig_d
= module
->Mux(NEW_ID
, sig_q
, sig_d
, enable_sig
);
1760 return module
->addDffsr(name
, clock_sig
, sig_set
, sig_clr
, sig_d
, sig_q
, posedge
);
1763 // ==================================================================
1765 struct VerificExtNets
1767 int portname_cnt
= 0;
1769 // a map from Net to the same Net one level up in the design hierarchy
1770 std::map
<Net
*, Net
*> net_level_up_drive_up
;
1771 std::map
<Net
*, Net
*> net_level_up_drive_down
;
1773 Net
*route_up(Net
*net
, bool drive_up
, Net
*final_net
= nullptr)
1775 auto &net_level_up
= drive_up
? net_level_up_drive_up
: net_level_up_drive_down
;
1777 if (net_level_up
.count(net
) == 0)
1779 Netlist
*nl
= net
->Owner();
1781 // Simply return if Netlist is not unique
1782 log_assert(nl
->NumOfRefs() == 1);
1784 Instance
*up_inst
= (Instance
*)nl
->GetReferences()->GetLast();
1785 Netlist
*up_nl
= up_inst
->Owner();
1788 string name
= stringf("___extnets_%d", portname_cnt
++);
1789 Port
*new_port
= new Port(name
.c_str(), drive_up
? DIR_OUT
: DIR_IN
);
1791 net
->Connect(new_port
);
1793 // create new Net in up Netlist
1794 Net
*new_net
= final_net
;
1795 if (new_net
== nullptr || new_net
->Owner() != up_nl
) {
1796 new_net
= new Net(name
.c_str());
1797 up_nl
->Add(new_net
);
1799 up_inst
->Connect(new_port
, new_net
);
1801 net_level_up
[net
] = new_net
;
1804 return net_level_up
.at(net
);
1807 Net
*route_up(Net
*net
, bool drive_up
, Netlist
*dest
, Net
*final_net
= nullptr)
1809 while (net
->Owner() != dest
)
1810 net
= route_up(net
, drive_up
, final_net
);
1811 if (final_net
!= nullptr)
1812 log_assert(net
== final_net
);
1816 Netlist
*find_common_ancestor(Netlist
*A
, Netlist
*B
)
1818 std::set
<Netlist
*> ancestors_of_A
;
1820 Netlist
*cursor
= A
;
1822 ancestors_of_A
.insert(cursor
);
1823 if (cursor
->NumOfRefs() != 1)
1825 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1830 if (ancestors_of_A
.count(cursor
))
1832 if (cursor
->NumOfRefs() != 1)
1834 cursor
= ((Instance
*)cursor
->GetReferences()->GetLast())->Owner();
1837 log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A
).c_str(), get_full_netlist_name(B
).c_str());
1840 void run(Netlist
*nl
)
1846 vector
<tuple
<Instance
*, Port
*, Net
*>> todo_connect
;
1848 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1851 FOREACH_INSTANCE_OF_NETLIST(nl
, mi
, inst
)
1852 FOREACH_PORTREF_OF_INST(inst
, mi2
, pr
)
1854 Port
*port
= pr
->GetPort();
1855 Net
*net
= pr
->GetNet();
1857 if (!net
->IsExternalTo(nl
))
1860 if (verific_verbose
)
1861 log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl
).c_str(), inst
->Name(), port
->Name());
1863 Netlist
*ext_nl
= net
->Owner();
1865 if (verific_verbose
)
1866 log(" external net owner: %s\n", get_full_netlist_name(ext_nl
).c_str());
1868 Netlist
*ca_nl
= find_common_ancestor(nl
, ext_nl
);
1870 if (verific_verbose
)
1871 log(" common ancestor: %s\n", get_full_netlist_name(ca_nl
).c_str());
1873 Net
*ca_net
= route_up(net
, !port
->IsOutput(), ca_nl
);
1874 Net
*new_net
= ca_net
;
1878 if (verific_verbose
)
1879 log(" net in common ancestor: %s\n", ca_net
->Name());
1881 string name
= stringf("___extnets_%d", portname_cnt
++);
1882 new_net
= new Net(name
.c_str());
1885 Net
*n
YS_ATTRIBUTE(unused
) = route_up(new_net
, port
->IsOutput(), ca_nl
, ca_net
);
1886 log_assert(n
== ca_net
);
1889 if (verific_verbose
)
1890 log(" new local net: %s\n", new_net
->Name());
1892 log_assert(!new_net
->IsExternalTo(nl
));
1893 todo_connect
.push_back(tuple
<Instance
*, Port
*, Net
*>(inst
, port
, new_net
));
1896 for (auto it
: todo_connect
) {
1897 get
<0>(it
)->Disconnect(get
<1>(it
));
1898 get
<0>(it
)->Connect(get
<1>(it
), get
<2>(it
));
1903 void verific_import(Design
*design
, const std::map
<std::string
,std::string
> ¶meters
, std::string top
)
1905 verific_sva_fsm_limit
= 16;
1907 std::set
<Netlist
*> nl_todo
, nl_done
;
1909 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary("work", 1);
1910 VeriLibrary
*veri_lib
= veri_file::GetLibrary("work", 1);
1911 Array
*netlists
= NULL
;
1912 Array veri_libs
, vhdl_libs
;
1913 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
1914 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
1916 Map
verific_params(STRING_HASH
);
1917 for (const auto &i
: parameters
)
1918 verific_params
.Insert(i
.first
.c_str(), i
.second
.c_str());
1921 netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, &verific_params
);
1924 Array veri_modules
, vhdl_units
;
1927 VeriModule
*veri_module
= veri_lib
->GetModule(top
.c_str(), 1);
1929 veri_modules
.InsertLast(veri_module
);
1932 // Also elaborate all root modules since they may contain bind statements
1934 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
1935 if (!veri_module
->IsRootModule()) continue;
1936 veri_modules
.InsertLast(veri_module
);
1941 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(top
.c_str());
1943 vhdl_units
.InsertLast(vhdl_unit
);
1946 netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, &verific_params
);
1952 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
1953 if (top
.empty() && nl
->CellBaseName() != top
)
1955 nl
->AddAtt(new Att(" \\top", NULL
));
1961 if (!verific_error_msg
.empty())
1962 log_error("%s\n", verific_error_msg
.c_str());
1964 for (auto nl
: nl_todo
)
1965 nl
->ChangePortBusStructures(1 /* hierarchical */);
1967 VerificExtNets worker
;
1968 for (auto nl
: nl_todo
)
1971 while (!nl_todo
.empty()) {
1972 Netlist
*nl
= *nl_todo
.begin();
1973 if (nl_done
.count(nl
) == 0) {
1974 VerificImporter
importer(false, false, false, false, false, false, false);
1975 importer
.import_netlist(design
, nl
, nl_todo
, nl
->Owner()->Name() == top
);
1984 verific_incdirs
.clear();
1985 verific_libdirs
.clear();
1986 verific_import_pending
= false;
1988 if (!verific_error_msg
.empty())
1989 log_error("%s\n", verific_error_msg
.c_str());
1993 #endif /* YOSYS_ENABLE_VERIFIC */
1995 PRIVATE_NAMESPACE_BEGIN
1997 #ifdef YOSYS_ENABLE_VERIFIC
1998 bool check_noverific_env()
2000 const char *e
= getenv("YOSYS_NOVERIFIC");
2009 struct VerificPass
: public Pass
{
2010 VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
2011 void help() YS_OVERRIDE
2013 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2015 log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
2017 log("Load the specified Verilog/SystemVerilog files into Verific.\n");
2019 log("All files specified in one call to this command are one compilation unit.\n");
2020 log("Files passed to different calls to this command are treated as belonging to\n");
2021 log("different compilation units.\n");
2023 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2024 log("the language version (and before file names) to set additional verilog defines.\n");
2025 log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
2028 log(" verific -formal <verilog-file>..\n");
2030 log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
2033 log(" verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2035 log("Load the specified VHDL files into Verific.\n");
2038 log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2040 log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
2041 log("(default library when -work is not present: \"work\")\n");
2044 log(" verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>\n");
2046 log("Look up external definitions in the specified library.\n");
2047 log("(-L may be used more than once)\n");
2050 log(" verific -vlog-incdir <directory>..\n");
2052 log("Add Verilog include directories.\n");
2055 log(" verific -vlog-libdir <directory>..\n");
2057 log("Add Verilog library directories. Verific will search in this directories to\n");
2058 log("find undefined modules.\n");
2061 log(" verific -vlog-define <macro>[=<value>]..\n");
2063 log("Add Verilog defines.\n");
2066 log(" verific -vlog-undef <macro>..\n");
2068 log("Remove Verilog defines previously set with -vlog-define.\n");
2071 log(" verific -set-error <msg_id>..\n");
2072 log(" verific -set-warning <msg_id>..\n");
2073 log(" verific -set-info <msg_id>..\n");
2074 log(" verific -set-ignore <msg_id>..\n");
2076 log("Set message severity. <msg_id> is the string in square brackets when a message\n");
2077 log("is printed, such as VERI-1209.\n");
2080 log(" verific -import [options] <top-module>..\n");
2082 log("Elaborate the design for the specified top modules, import to Yosys and\n");
2083 log("reset the internal state of Verific.\n");
2085 log("Import options:\n");
2088 log(" Elaborate all modules, not just the hierarchy below the given top\n");
2089 log(" modules. With this option the list of modules to import is optional.\n");
2092 log(" Create a gate-level netlist.\n");
2095 log(" Flatten the design in Verific before importing.\n");
2098 log(" Resolve references to external nets by adding module ports as needed.\n");
2100 log(" -autocover\n");
2101 log(" Generate automatic cover statements for all asserts\n");
2103 log(" -fullinit\n");
2104 log(" Keep all register initializations, even those for non-FF registers.\n");
2106 log(" -chparam name value \n");
2107 log(" Elaborate the specified top modules (all modules when -all given) using\n");
2108 log(" this parameter value. Modules on which this parameter does not exist will\n");
2109 log(" cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
2110 log(" can be specified multiple times to override multiple parameters.\n");
2111 log(" String values must be passed in double quotes (\").\n");
2114 log(" Verbose log messages. (-vv is even more verbose than -v.)\n");
2116 log("The following additional import options are useful for debugging the Verific\n");
2117 log("bindings (for Yosys and/or Verific developers):\n");
2120 log(" Keep going after an unsupported verific primitive is found. The\n");
2121 log(" unsupported primitive is added as blockbox module to the design.\n");
2122 log(" This will also add all SVA related cells to the design parallel to\n");
2123 log(" the checker logic inferred by it.\n");
2126 log(" Import Verific netlist as-is without translating to Yosys cell types. \n");
2129 log(" Ignore SVA properties, do not infer checker logic.\n");
2132 log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
2135 log(" Keep all Verific names on instances and nets. By default only\n");
2136 log(" user-declared names are preserved.\n");
2138 log(" -d <dump_file>\n");
2139 log(" Dump the Verific netlist as a verilog file.\n");
2142 log("Use Symbiotic EDA Suite if you need Yosys+Verifc.\n");
2143 log("https://www.symbioticeda.com/seda-suite\n");
2145 log("Contact office@symbioticeda.com for free evaluation\n");
2146 log("binaries of Symbiotic EDA Suite.\n");
2149 #ifdef YOSYS_ENABLE_VERIFIC
2150 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
2152 static bool set_verific_global_flags
= true;
2154 if (check_noverific_env())
2155 log_cmd_error("This version of Yosys is built without Verific support.\n"
2157 "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
2158 "https://www.symbioticeda.com/seda-suite\n"
2160 "Contact office@symbioticeda.com for free evaluation\n"
2161 "binaries of Symbiotic EDA Suite.\n");
2163 log_header(design
, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
2165 if (set_verific_global_flags
)
2167 Message::SetConsoleOutput(0);
2168 Message::RegisterCallBackMsg(msg_func
);
2170 RuntimeFlags::SetVar("db_preserve_user_nets", 1);
2171 RuntimeFlags::SetVar("db_allow_external_nets", 1);
2172 RuntimeFlags::SetVar("db_infer_wide_operators", 1);
2174 RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
2175 RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
2177 RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
2178 RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
2180 RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
2181 RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
2183 RuntimeFlags::SetVar("veri_preserve_assignments", 1);
2184 RuntimeFlags::SetVar("vhdl_preserve_assignments", 1);
2186 // Workaround for VIPER #13851
2187 RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
2189 // WARNING: instantiating unknown module 'XYZ' (VERI-1063)
2190 Message::SetMessageType("VERI-1063", VERIFIC_ERROR
);
2192 // https://github.com/YosysHQ/yosys/issues/1055
2193 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ;
2195 #ifndef DB_PRESERVE_INITIAL_VALUE
2196 # warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
2199 set_verific_global_flags
= false;
2202 verific_verbose
= 0;
2203 verific_sva_fsm_limit
= 16;
2205 const char *release_str
= Message::ReleaseString();
2206 time_t release_time
= Message::ReleaseDate();
2207 char *release_tmstr
= ctime(&release_time
);
2209 if (release_str
== nullptr)
2210 release_str
= "(no release string)";
2212 for (char *p
= release_tmstr
; *p
; p
++)
2213 if (*p
== '\n') *p
= 0;
2215 log("Built with Verific %s, released at %s.\n", release_str
, release_tmstr
);
2218 std::string work
= "work";
2220 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-set-error" || args
[argidx
] == "-set-warning" ||
2221 args
[argidx
] == "-set-info" || args
[argidx
] == "-set-ignore"))
2223 msg_type_t new_type
;
2225 if (args
[argidx
] == "-set-error")
2226 new_type
= VERIFIC_ERROR
;
2227 else if (args
[argidx
] == "-set-warning")
2228 new_type
= VERIFIC_WARNING
;
2229 else if (args
[argidx
] == "-set-info")
2230 new_type
= VERIFIC_INFO
;
2231 else if (args
[argidx
] == "-set-ignore")
2232 new_type
= VERIFIC_IGNORE
;
2236 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2237 Message::SetMessageType(args
[argidx
].c_str(), new_type
);
2242 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-incdir") {
2243 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2244 verific_incdirs
.push_back(args
[argidx
]);
2248 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-libdir") {
2249 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2250 verific_libdirs
.push_back(args
[argidx
]);
2254 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-define") {
2255 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2256 string name
= args
[argidx
];
2257 size_t equal
= name
.find('=');
2258 if (equal
!= std::string::npos
) {
2259 string value
= name
.substr(equal
+1);
2260 name
= name
.substr(0, equal
);
2261 veri_file::DefineCmdLineMacro(name
.c_str(), value
.c_str());
2263 veri_file::DefineCmdLineMacro(name
.c_str());
2269 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vlog-undef") {
2270 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2271 string name
= args
[argidx
];
2272 veri_file::UndefineMacro(name
.c_str());
2277 veri_file::RemoveAllLOptions();
2278 for (; argidx
< GetSize(args
); argidx
++)
2280 if (args
[argidx
] == "-work" && argidx
+1 < GetSize(args
)) {
2281 work
= args
[++argidx
];
2284 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2285 veri_file::AddLOption(args
[++argidx
].c_str());
2291 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vlog95" || args
[argidx
] == "-vlog2k" || args
[argidx
] == "-sv2005" ||
2292 args
[argidx
] == "-sv2009" || args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal"))
2295 unsigned verilog_mode
;
2297 if (args
[argidx
] == "-vlog95")
2298 verilog_mode
= veri_file::VERILOG_95
;
2299 else if (args
[argidx
] == "-vlog2k")
2300 verilog_mode
= veri_file::VERILOG_2K
;
2301 else if (args
[argidx
] == "-sv2005")
2302 verilog_mode
= veri_file::SYSTEM_VERILOG_2005
;
2303 else if (args
[argidx
] == "-sv2009")
2304 verilog_mode
= veri_file::SYSTEM_VERILOG_2009
;
2305 else if (args
[argidx
] == "-sv2012" || args
[argidx
] == "-sv" || args
[argidx
] == "-formal")
2306 verilog_mode
= veri_file::SYSTEM_VERILOG
;
2310 veri_file::DefineMacro("VERIFIC");
2311 veri_file::DefineMacro(args
[argidx
] == "-formal" ? "FORMAL" : "SYNTHESIS");
2313 for (argidx
++; argidx
< GetSize(args
) && GetSize(args
[argidx
]) >= 2 && args
[argidx
].compare(0, 2, "-D") == 0; argidx
++) {
2314 std::string name
= args
[argidx
].substr(2);
2315 if (args
[argidx
] == "-D") {
2316 if (++argidx
>= GetSize(args
))
2318 name
= args
[argidx
];
2320 size_t equal
= name
.find('=');
2321 if (equal
!= std::string::npos
) {
2322 string value
= name
.substr(equal
+1);
2323 name
= name
.substr(0, equal
);
2324 veri_file::DefineMacro(name
.c_str(), value
.c_str());
2326 veri_file::DefineMacro(name
.c_str());
2330 for (auto &dir
: verific_incdirs
)
2331 veri_file::AddIncludeDir(dir
.c_str());
2332 for (auto &dir
: verific_libdirs
)
2333 veri_file::AddYDir(dir
.c_str());
2335 while (argidx
< GetSize(args
))
2336 file_names
.Insert(args
[argidx
++].c_str());
2338 if (!veri_file::AnalyzeMultipleFiles(&file_names
, verilog_mode
, work
.c_str(), veri_file::MFCU
))
2339 log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
2341 verific_import_pending
= true;
2345 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl87") {
2346 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
2347 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2348 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_87
))
2349 log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args
[argidx
].c_str());
2350 verific_import_pending
= true;
2354 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl93") {
2355 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2356 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2357 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_93
))
2358 log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args
[argidx
].c_str());
2359 verific_import_pending
= true;
2363 if (GetSize(args
) > argidx
&& args
[argidx
] == "-vhdl2k") {
2364 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
2365 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2366 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2K
))
2367 log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args
[argidx
].c_str());
2368 verific_import_pending
= true;
2372 if (GetSize(args
) > argidx
&& (args
[argidx
] == "-vhdl2008" || args
[argidx
] == "-vhdl")) {
2373 vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
2374 for (argidx
++; argidx
< GetSize(args
); argidx
++)
2375 if (!vhdl_file::Analyze(args
[argidx
].c_str(), work
.c_str(), vhdl_file::VHDL_2008
))
2376 log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args
[argidx
].c_str());
2377 verific_import_pending
= true;
2381 if (GetSize(args
) > argidx
&& args
[argidx
] == "-import")
2383 std::set
<Netlist
*> nl_todo
, nl_done
;
2384 bool mode_all
= false, mode_gates
= false, mode_keep
= false;
2385 bool mode_nosva
= false, mode_names
= false, mode_verific
= false;
2386 bool mode_autocover
= false, mode_fullinit
= false;
2387 bool flatten
= false, extnets
= false;
2389 Map
parameters(STRING_HASH
);
2391 for (argidx
++; argidx
< GetSize(args
); argidx
++) {
2392 if (args
[argidx
] == "-all") {
2396 if (args
[argidx
] == "-gates") {
2400 if (args
[argidx
] == "-flatten") {
2404 if (args
[argidx
] == "-extnets") {
2408 if (args
[argidx
] == "-k") {
2412 if (args
[argidx
] == "-nosva") {
2416 if (args
[argidx
] == "-L" && argidx
+1 < GetSize(args
)) {
2417 verific_sva_fsm_limit
= atoi(args
[++argidx
].c_str());
2420 if (args
[argidx
] == "-n") {
2424 if (args
[argidx
] == "-autocover") {
2425 mode_autocover
= true;
2428 if (args
[argidx
] == "-fullinit") {
2429 mode_fullinit
= true;
2432 if (args
[argidx
] == "-chparam" && argidx
+2 < GetSize(args
)) {
2433 const std::string
&key
= args
[++argidx
];
2434 const std::string
&value
= args
[++argidx
];
2435 unsigned new_insertion
= parameters
.Insert(key
.c_str(), value
.c_str(),
2436 1 /* force_overwrite */);
2438 log_warning_noprefix("-chparam %s already specified: overwriting.\n", key
.c_str());
2441 if (args
[argidx
] == "-V") {
2442 mode_verific
= true;
2445 if (args
[argidx
] == "-v") {
2446 verific_verbose
= 1;
2449 if (args
[argidx
] == "-vv") {
2450 verific_verbose
= 2;
2453 if (args
[argidx
] == "-d" && argidx
+1 < GetSize(args
)) {
2454 dumpfile
= args
[++argidx
];
2460 if (argidx
> GetSize(args
) && args
[argidx
].compare(0, 1, "-") == 0)
2461 cmd_error(args
, argidx
, "unknown option");
2463 std::set
<std::string
> top_mod_names
;
2467 log("Running hier_tree::ElaborateAll().\n");
2469 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2470 VeriLibrary
*veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2472 Array veri_libs
, vhdl_libs
;
2473 if (vhdl_lib
) vhdl_libs
.InsertLast(vhdl_lib
);
2474 if (veri_lib
) veri_libs
.InsertLast(veri_lib
);
2476 Array
*netlists
= hier_tree::ElaborateAll(&veri_libs
, &vhdl_libs
, ¶meters
);
2480 FOREACH_ARRAY_ITEM(netlists
, i
, nl
)
2486 if (argidx
== GetSize(args
))
2487 cmd_error(args
, argidx
, "No top module specified.\n");
2489 Array veri_modules
, vhdl_units
;
2490 for (; argidx
< GetSize(args
); argidx
++)
2492 const char *name
= args
[argidx
].c_str();
2493 top_mod_names
.insert(name
);
2494 VeriLibrary
* veri_lib
= veri_file::GetLibrary(work
.c_str(), 1);
2497 VeriModule
*veri_module
= veri_lib
->GetModule(name
, 1);
2499 log("Adding Verilog module '%s' to elaboration queue.\n", name
);
2500 veri_modules
.InsertLast(veri_module
);
2504 // Also elaborate all root modules since they may contain bind statements
2506 FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib
, mi
, veri_module
) {
2507 if (!veri_module
->IsRootModule()) continue;
2508 veri_modules
.InsertLast(veri_module
);
2512 VhdlLibrary
*vhdl_lib
= vhdl_file::GetLibrary(work
.c_str(), 1);
2513 VhdlDesignUnit
*vhdl_unit
= vhdl_lib
->GetPrimUnit(name
);
2515 log("Adding VHDL unit '%s' to elaboration queue.\n", name
);
2516 vhdl_units
.InsertLast(vhdl_unit
);
2520 log_error("Can't find module/unit '%s'.\n", name
);
2523 log("Running hier_tree::Elaborate().\n");
2524 Array
*netlists
= hier_tree::Elaborate(&veri_modules
, &vhdl_units
, ¶meters
);
2528 FOREACH_ARRAY_ITEM(netlists
, i
, nl
) {
2529 nl
->AddAtt(new Att(" \\top", NULL
));
2535 if (!verific_error_msg
.empty())
2539 for (auto nl
: nl_todo
)
2544 VerificExtNets worker
;
2545 for (auto nl
: nl_todo
)
2549 for (auto nl
: nl_todo
)
2550 nl
->ChangePortBusStructures(1 /* hierarchical */);
2552 if (!dumpfile
.empty()) {
2553 VeriWrite veri_writer
;
2554 veri_writer
.WriteFile(dumpfile
.c_str(), Netlist::PresentDesign());
2557 while (!nl_todo
.empty()) {
2558 Netlist
*nl
= *nl_todo
.begin();
2559 if (nl_done
.count(nl
) == 0) {
2560 VerificImporter
importer(mode_gates
, mode_keep
, mode_nosva
,
2561 mode_names
, mode_verific
, mode_autocover
, mode_fullinit
);
2562 importer
.import_netlist(design
, nl
, nl_todo
, top_mod_names
.count(nl
->Owner()->Name()));
2571 verific_incdirs
.clear();
2572 verific_libdirs
.clear();
2573 verific_import_pending
= false;
2577 cmd_error(args
, argidx
, "Missing or unsupported mode parameter.\n");
2580 if (!verific_error_msg
.empty())
2581 log_error("%s\n", verific_error_msg
.c_str());
2584 #else /* YOSYS_ENABLE_VERIFIC */
2585 void execute(std::vector
<std::string
>, RTLIL::Design
*) YS_OVERRIDE
{
2586 log_cmd_error("This version of Yosys is built without Verific support.\n"
2588 "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n"
2589 "https://www.symbioticeda.com/seda-suite\n"
2591 "Contact office@symbioticeda.com for free evaluation\n"
2592 "binaries of Symbiotic EDA Suite.\n");
2597 struct ReadPass
: public Pass
{
2598 ReadPass() : Pass("read", "load HDL designs") { }
2599 void help() YS_OVERRIDE
2601 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
2603 log(" read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
2605 log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
2606 log("is only available via Verific.)\n");
2608 log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
2609 log("the language version (and before file names) to set additional verilog defines.\n");
2612 log(" read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
2614 log("Load the specified VHDL files. (Requires Verific.)\n");
2617 log(" read -define <macro>[=<value>]..\n");
2619 log("Set global Verilog/SystemVerilog defines.\n");
2622 log(" read -undef <macro>..\n");
2624 log("Unset global Verilog/SystemVerilog defines.\n");
2627 log(" read -incdir <directory>\n");
2629 log("Add directory to global Verilog/SystemVerilog include directories.\n");
2632 log(" read -verific\n");
2633 log(" read -noverific\n");
2635 log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
2636 log("with -verific will result in an error on Yosys binaries that are built without\n");
2637 log("Verific support. The default is to use Verific if it is available.\n");
2640 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
2642 #ifdef YOSYS_ENABLE_VERIFIC
2643 static bool verific_available
= !check_noverific_env();
2645 static bool verific_available
= false;
2647 static bool use_verific
= verific_available
;
2649 if (args
.size() < 2 || args
[1][0] != '-')
2650 cmd_error(args
, 1, "Missing mode parameter.\n");
2652 if (args
[1] == "-verific" || args
[1] == "-noverific") {
2653 if (args
.size() != 2)
2654 cmd_error(args
, 1, "Additional arguments to -verific/-noverific.\n");
2655 if (args
[1] == "-verific") {
2656 if (!verific_available
)
2657 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
2660 use_verific
= false;
2665 if (args
.size() < 3)
2666 cmd_error(args
, 3, "Missing file name parameter.\n");
2668 if (args
[1] == "-vlog95" || args
[1] == "-vlog2k") {
2670 args
[0] = "verific";
2672 args
[0] = "read_verilog";
2675 Pass::call(design
, args
);
2679 if (args
[1] == "-sv2005" || args
[1] == "-sv2009" || args
[1] == "-sv2012" || args
[1] == "-sv" || args
[1] == "-formal") {
2681 args
[0] = "verific";
2683 args
[0] = "read_verilog";
2684 if (args
[1] == "-formal")
2685 args
.insert(args
.begin()+1, std::string());
2687 args
.insert(args
.begin()+1, "-defer");
2689 Pass::call(design
, args
);
2693 if (args
[1] == "-vhdl87" || args
[1] == "-vhdl93" || args
[1] == "-vhdl2k" || args
[1] == "-vhdl2008" || args
[1] == "-vhdl") {
2695 args
[0] = "verific";
2696 Pass::call(design
, args
);
2698 cmd_error(args
, 1, "This version of Yosys is built without Verific support.\n");
2703 if (args
[1] == "-define") {
2705 args
[0] = "verific";
2706 args
[1] = "-vlog-define";
2707 Pass::call(design
, args
);
2709 args
[0] = "verilog_defines";
2710 args
.erase(args
.begin()+1, args
.begin()+2);
2711 for (int i
= 1; i
< GetSize(args
); i
++)
2712 args
[i
] = "-D" + args
[i
];
2713 Pass::call(design
, args
);
2717 if (args
[1] == "-undef") {
2719 args
[0] = "verific";
2720 args
[1] = "-vlog-undef";
2721 Pass::call(design
, args
);
2723 args
[0] = "verilog_defines";
2724 args
.erase(args
.begin()+1, args
.begin()+2);
2725 for (int i
= 1; i
< GetSize(args
); i
++)
2726 args
[i
] = "-U" + args
[i
];
2727 Pass::call(design
, args
);
2731 if (args
[1] == "-incdir") {
2733 args
[0] = "verific";
2734 args
[1] = "-vlog-incdir";
2735 Pass::call(design
, args
);
2737 args
[0] = "verilog_defaults";
2739 for (int i
= 2; i
< GetSize(args
); i
++)
2740 args
[i
] = "-I" + args
[i
];
2741 Pass::call(design
, args
);
2745 cmd_error(args
, 1, "Missing or unsupported mode parameter.\n");
2749 PRIVATE_NAMESPACE_END