Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
[yosys.git] / frontends / verilog / Makefile.inc
1
2 GENFILES += frontends/verilog/verilog_parser.tab.cc
3 GENFILES += frontends/verilog/verilog_parser.tab.hh
4 GENFILES += frontends/verilog/verilog_parser.output
5 GENFILES += frontends/verilog/verilog_lexer.cc
6
7 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
8 $(Q) mkdir -p $(dir $@)
9 $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
10
11 frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
12
13 frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
14 $(Q) mkdir -p $(dir $@)
15 $(P) flex -o frontends/verilog/verilog_lexer.cc $<
16
17 frontends/verilog/verilog_parser.tab.o: CXXFLAGS += -DYYMAXDEPTH=10000000
18
19 OBJS += frontends/verilog/verilog_parser.tab.o
20 OBJS += frontends/verilog/verilog_lexer.o
21 OBJS += frontends/verilog/preproc.o
22 OBJS += frontends/verilog/verilog_frontend.o
23 OBJS += frontends/verilog/const2ast.o
24