frontends/verilog/parser.y

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  *  ---
  19  *
  20  *  The Verilog frontend.
  21  *
  22  *  This frontend is using the AST frontend library (see frontends/ast/).
  23  *  Thus this frontend does not generate RTLIL code directly but creates an
  24  *  AST directly from the Verilog parse tree and then passes this AST to
  25  *  the AST frontend library.
  26  *
  27  *  ---
  28  *
  29  *  This is the actual bison parser for Verilog code. The AST ist created directly
  30  *  from the bison reduce functions here. Note that this code uses a few global
  31  *  variables to hold the state of the AST generator and therefore this parser is
  32  *  not reentrant.
  33  *
  34  */
  35
  36 %{
  37 #include <list>
  38 #include <assert.h>
  39 #include "verilog_frontend.h"
  40 #include "kernel/log.h"
  41
  42 using namespace AST;
  43 using namespace VERILOG_FRONTEND;
  44
  45 namespace VERILOG_FRONTEND {
  46         int port_counter;
  47         std::map<std::string, int> port_stubs;
  48         std::map<std::string, AstNode*> attr_list, default_attr_list;
  49         std::map<std::string, AstNode*> *albuf;
  50         std::vector<AstNode*> ast_stack;
  51         struct AstNode *astbuf1, *astbuf2, *astbuf3;
  52         struct AstNode *current_function_or_task;
  53         struct AstNode *current_ast, *current_ast_mod;
  54         int current_function_or_task_port_id;
  55         std::vector<char> case_type_stack;
  56 }
  57
  58 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)
  59 {
  60         for (auto &it : *al) {
  61                 if (ast->attributes.count(it.first) > 0)
  62                         delete ast->attributes[it.first];
  63                 ast->attributes[it.first] = it.second;
  64         }
  65         delete al;
  66 }
  67
  68 static void append_attr_clone(AstNode *ast, std::map<std::string, AstNode*> *al)
  69 {
  70         for (auto &it : *al) {
  71                 if (ast->attributes.count(it.first) > 0)
  72                         delete ast->attributes[it.first];
  73                 ast->attributes[it.first] = it.second->clone();
  74         }
  75 }
  76
  77 static void free_attr(std::map<std::string, AstNode*> *al)
  78 {
  79         for (auto &it : *al)
  80                 delete it.second;
  81         delete al;
  82 }
  83
  84 %}
  85
  86 %name-prefix="frontend_verilog_yy"
  87
  88 %union {
  89         std::string *string;
  90         struct AstNode *ast;
  91         std::map<std::string, AstNode*> *al;
  92         bool boolean;
  93 }
  94
  95 %token <string> TOK_STRING TOK_ID TOK_CONST TOK_PRIMITIVE
  96 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
  97 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
  98 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
  99 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 100 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR
 101 %token TOK_POSEDGE TOK_NEGEDGE TOK_OR
 102 %token TOK_CASE TOK_CASEX TOK_CASEZ TOK_ENDCASE TOK_DEFAULT
 103 %token TOK_FUNCTION TOK_ENDFUNCTION TOK_TASK TOK_ENDTASK
 104 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
 105 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 106 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
 107
 108 %type <ast> wire_type range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 109 %type <string> opt_label tok_prim_wrapper hierarchical_id
 110 %type <boolean> opt_signed
 111 %type <al> attr
 112
 113 // operator precedence from low to high
 114 %left OP_LOR
 115 %left OP_LAND
 116 %left '|' OP_NOR
 117 %left '^' OP_XNOR
 118 %left '&' OP_NAND
 119 %left OP_EQ OP_NE
 120 %left '<' OP_LE OP_GE '>'
 121 %left OP_SHL OP_SHR OP_SSHL OP_SSHR
 122 %left '+' '-'
 123 %left '*' '/' '%'
 124 %left OP_POW
 125 %right UNARY_OPS
 126
 127 %expect 2
 128 %debug
 129
 130 %%
 131
 132 input:
 133         module input |
 134         defattr input |
 135         /* empty */ {
 136                 for (auto &it : default_attr_list)
 137                         delete it.second;
 138                 default_attr_list.clear();
 139         };
 140
 141 attr:
 142         {
 143                 for (auto &it : attr_list)
 144                         delete it.second;
 145                 attr_list.clear();
 146                 for (auto &it : default_attr_list)
 147                         attr_list[it.first] = it.second->clone();
 148         } attr_opt {
 149                 std::map<std::string, AstNode*> *al = new std::map<std::string, AstNode*>;
 150                 al->swap(attr_list);
 151                 $$ = al;
 152         };
 153
 154 attr_opt:
 155         attr_opt ATTR_BEGIN opt_attr_list ATTR_END |
 156         /* empty */;
 157
 158 defattr:
 159         DEFATTR_BEGIN {
 160                 for (auto &it : default_attr_list)
 161                         delete it.second;
 162                 default_attr_list.clear();
 163                 for (auto &it : attr_list)
 164                         delete it.second;
 165                 attr_list.clear();
 166         } opt_attr_list {
 167                 default_attr_list = attr_list;
 168                 attr_list.clear();
 169         } DEFATTR_END;
 170
 171 opt_attr_list:
 172         attr_list | /* empty */;
 173
 174 attr_list:
 175         attr_assign |
 176         attr_list ',' attr_assign;
 177
 178 attr_assign:
 179         hierarchical_id {
 180                 if (attr_list.count(*$1) != 0)
 181                         delete attr_list[*$1];
 182                 attr_list[*$1] = AstNode::mkconst_int(1, false);
 183                 delete $1;
 184         } |
 185         hierarchical_id '=' expr {
 186                 if (attr_list.count(*$1) != 0)
 187                         delete attr_list[*$1];
 188                 attr_list[*$1] = $3;
 189                 delete $1;
 190         };
 191
 192 hierarchical_id:
 193         TOK_ID {
 194                 $$ = $1;
 195         } |
 196         hierarchical_id '.' TOK_ID {
 197                 if ($3->substr(0, 1) == "\\")
 198                         *$1 += "." + $3->substr(1);
 199                 else
 200                         *$1 += "." + *$3;
 201                 delete $3;
 202                 $$ = $1;
 203         };
 204
 205 module:
 206         attr TOK_MODULE TOK_ID {
 207                 AstNode *mod = new AstNode(AST_MODULE);
 208                 current_ast->children.push_back(mod);
 209                 current_ast_mod = mod;
 210                 ast_stack.push_back(mod);
 211                 port_stubs.clear();
 212                 port_counter = 0;
 213                 mod->str = *$3;
 214                 append_attr(mod, $1);
 215                 delete $3;
 216         } module_para_opt module_args_opt ';' module_body TOK_ENDMODULE {
 217                 if (port_stubs.size() != 0)
 218                         frontend_verilog_yyerror("Missing details for module port `%s'.",
 219                                         port_stubs.begin()->first.c_str());
 220                 ast_stack.pop_back();
 221                 assert(ast_stack.size() == 0);
 222         };
 223
 224 module_para_opt:
 225         '#' '(' module_para_list ')' | /* empty */;
 226
 227 module_para_list:
 228         single_module_para |
 229         single_module_para ',' module_para_list |
 230         /* empty */;
 231
 232 single_module_para:
 233         TOK_PARAMETER {
 234                 astbuf1 = new AstNode(AST_PARAMETER);
 235                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 236         } param_signed param_integer param_range single_param_decl {
 237                 delete astbuf1;
 238         };
 239
 240 module_args_opt:
 241         '(' ')' | /* empty */ | '(' module_args optional_comma ')';
 242
 243 module_args:
 244         module_arg | module_args ',' module_arg;
 245
 246 optional_comma:
 247         ',' | /* empty */;
 248
 249 module_arg_opt_assignment:
 250         '=' expr {
 251                 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
 252                         if (!ast_stack.back()->children.back()->is_reg) {
 253                                 AstNode *wire = new AstNode(AST_IDENTIFIER);
 254                                 wire->str = ast_stack.back()->children.back()->str;
 255                                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
 256                         } else
 257                                 ast_stack.back()->children.back()->attributes["\\init"] = $2;
 258                 } else
 259                         frontend_verilog_yyerror("Syntax error.");
 260         } |
 261         /* empty */;
 262
 263 module_arg:
 264         TOK_ID {
 265                 if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
 266                         AstNode *node = ast_stack.back()->children.back()->clone();
 267                         node->str = *$1;
 268                         node->port_id = ++port_counter;
 269                         ast_stack.back()->children.push_back(node);
 270                 } else {
 271                         if (port_stubs.count(*$1) != 0)
 272                                 frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
 273                         port_stubs[*$1] = ++port_counter;
 274                 }
 275                 delete $1;
 276         } module_arg_opt_assignment |
 277         attr wire_type range TOK_ID {
 278                 AstNode *node = $2;
 279                 node->str = *$4;
 280                 node->port_id = ++port_counter;
 281                 if ($3 != NULL)
 282                         node->children.push_back($3);
 283                 if (!node->is_input && !node->is_output)
 284                         frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str());
 285                 if (node->is_reg && node->is_input && !node->is_output)
 286                         frontend_verilog_yyerror("Input port `%s' is declared as register.", $4->c_str());
 287                 ast_stack.back()->children.push_back(node);
 288                 append_attr(node, $1);
 289                 delete $4;
 290         } module_arg_opt_assignment;
 291
 292 wire_type:
 293         {
 294                 astbuf3 = new AstNode(AST_WIRE);
 295         } wire_type_token_list {
 296                 $$ = astbuf3;
 297         };
 298
 299 wire_type_token_list:
 300         wire_type_token | wire_type_token_list wire_type_token;
 301
 302 wire_type_token:
 303         TOK_INPUT {
 304                 astbuf3->is_input = true;
 305         } |
 306         TOK_OUTPUT {
 307                 astbuf3->is_output = true;
 308         } |
 309         TOK_INOUT {
 310                 astbuf3->is_input = true;
 311                 astbuf3->is_output = true;
 312         } |
 313         TOK_WIRE {
 314         } |
 315         TOK_REG {
 316                 astbuf3->is_reg = true;
 317         } |
 318         TOK_INTEGER {
 319                 astbuf3->is_reg = true;
 320                 astbuf3->range_left = 31;
 321                 astbuf3->range_right = 0;
 322         } |
 323         TOK_GENVAR {
 324                 astbuf3->type = AST_GENVAR;
 325                 astbuf3->is_reg = true;
 326                 astbuf3->range_left = 31;
 327                 astbuf3->range_right = 0;
 328         } |
 329         TOK_SIGNED {
 330                 astbuf3->is_signed = true;
 331         };
 332
 333 range:
 334         '[' expr ':' expr ']' {
 335                 $$ = new AstNode(AST_RANGE);
 336                 $$->children.push_back($2);
 337                 $$->children.push_back($4);
 338         } |
 339         '[' expr ']' {
 340                 $$ = new AstNode(AST_RANGE);
 341                 $$->children.push_back($2);
 342         } |
 343         /* empty */ {
 344                 $$ = NULL;
 345         };
 346
 347 module_body:
 348         module_body module_body_stmt |
 349         /* empty */;
 350
 351 module_body_stmt:
 352         task_func_decl | param_decl | localparam_decl | defparam_decl | wire_decl | assign_stmt | cell_stmt |
 353         always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr;
 354
 355 task_func_decl:
 356         TOK_TASK TOK_ID ';' {
 357                 current_function_or_task = new AstNode(AST_TASK);
 358                 current_function_or_task->str = *$2;
 359                 ast_stack.back()->children.push_back(current_function_or_task);
 360                 ast_stack.push_back(current_function_or_task);
 361                 current_function_or_task_port_id = 1;
 362                 delete $2;
 363         } task_func_body TOK_ENDTASK {
 364                 current_function_or_task = NULL;
 365                 ast_stack.pop_back();
 366         } |
 367         TOK_FUNCTION opt_signed range TOK_ID ';' {
 368                 current_function_or_task = new AstNode(AST_FUNCTION);
 369                 current_function_or_task->str = *$4;
 370                 ast_stack.back()->children.push_back(current_function_or_task);
 371                 ast_stack.push_back(current_function_or_task);
 372                 AstNode *outreg = new AstNode(AST_WIRE);
 373                 if ($3 != NULL)
 374                         outreg->children.push_back($3);
 375                 outreg->str = *$4;
 376                 outreg->is_signed = $2;
 377                 current_function_or_task->children.push_back(outreg);
 378                 current_function_or_task_port_id = 1;
 379                 delete $4;
 380         } task_func_body TOK_ENDFUNCTION {
 381                 current_function_or_task = NULL;
 382                 ast_stack.pop_back();
 383         };
 384
 385 opt_signed:
 386         TOK_SIGNED {
 387                 $$ = true;
 388         } |
 389         /* empty */ {
 390                 $$ = false;
 391         };
 392
 393 task_func_body:
 394         task_func_body wire_decl |
 395         task_func_body behavioral_stmt |
 396         /* empty */;
 397
 398 param_signed:
 399         TOK_SIGNED {
 400                 astbuf1->is_signed = true;
 401         } | /* empty */;
 402
 403 param_integer:
 404         TOK_INTEGER {
 405                 if (astbuf1->children.size() != 1)
 406                         frontend_verilog_yyerror("Syntax error.");
 407                 astbuf1->children.push_back(new AstNode(AST_RANGE));
 408                 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
 409                 astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
 410         } | /* empty */;
 411
 412 param_range:
 413         range {
 414                 if ($1 != NULL) {
 415                         if (astbuf1->children.size() != 1)
 416                                 frontend_verilog_yyerror("Syntax error.");
 417                         astbuf1->children.push_back($1);
 418                 }
 419         };
 420
 421 param_decl:
 422         TOK_PARAMETER {
 423                 astbuf1 = new AstNode(AST_PARAMETER);
 424                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 425         } param_signed param_integer param_range param_decl_list ';' {
 426                 delete astbuf1;
 427         };
 428
 429 localparam_decl:
 430         TOK_LOCALPARAM {
 431                 astbuf1 = new AstNode(AST_LOCALPARAM);
 432                 astbuf1->children.push_back(AstNode::mkconst_int(0, true));
 433         } param_signed param_integer param_range param_decl_list ';' {
 434                 delete astbuf1;
 435         };
 436
 437 param_decl_list:
 438         single_param_decl | param_decl_list ',' single_param_decl;
 439
 440 single_param_decl:
 441         TOK_ID '=' expr {
 442                 AstNode *node = astbuf1->clone();
 443                 node->str = *$1;
 444                 delete node->children[0];
 445                 node->children[0] = $3;
 446                 ast_stack.back()->children.push_back(node);
 447                 delete $1;
 448         };
 449
 450 defparam_decl:
 451         TOK_DEFPARAM defparam_decl_list ';';
 452
 453 defparam_decl_list:
 454         single_defparam_decl | defparam_decl_list ',' single_defparam_decl;
 455
 456 single_defparam_decl:
 457         range hierarchical_id '=' expr {
 458                 AstNode *node = new AstNode(AST_DEFPARAM);
 459                 node->str = *$2;
 460                 node->children.push_back($4);
 461                 if ($1 != NULL)
 462                         node->children.push_back($1);
 463                 ast_stack.back()->children.push_back(node);
 464                 delete $2;
 465         };
 466
 467 wire_decl:
 468         attr wire_type range {
 469                 albuf = $1;
 470                 astbuf1 = $2;
 471                 astbuf2 = $3;
 472                 if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
 473                         if (astbuf2) {
 474                                 frontend_verilog_yyerror("Syntax error.");
 475                         } else {
 476                                 astbuf2 = new AstNode(AST_RANGE);
 477                                 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
 478                                 astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true));
 479                         }
 480                 }
 481                 if (astbuf2 && astbuf2->children.size() != 2)
 482                         frontend_verilog_yyerror("Syntax error.");
 483         } wire_name_list ';' {
 484                 delete astbuf1;
 485                 if (astbuf2 != NULL)
 486                         delete astbuf2;
 487                 free_attr(albuf);
 488         } |
 489         attr TOK_SUPPLY0 TOK_ID ';' {
 490                 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
 491                 ast_stack.back()->children.back()->str = *$3;
 492                 append_attr(ast_stack.back()->children.back(), $1);
 493                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)));
 494                 ast_stack.back()->children.back()->children[0]->str = *$3;
 495                 delete $3;
 496         } |
 497         attr TOK_SUPPLY1 TOK_ID ';' {
 498                 ast_stack.back()->children.push_back(new AstNode(AST_WIRE));
 499                 ast_stack.back()->children.back()->str = *$3;
 500                 append_attr(ast_stack.back()->children.back(), $1);
 501                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(1, false, 1)));
 502                 ast_stack.back()->children.back()->children[0]->str = *$3;
 503                 delete $3;
 504         };
 505
 506 wire_name_list:
 507         wire_name_and_opt_assign | wire_name_list ',' wire_name_and_opt_assign;
 508
 509 wire_name_and_opt_assign:
 510         wire_name |
 511         wire_name '=' expr {
 512                 if (!astbuf1->is_reg) {
 513                         AstNode *wire = new AstNode(AST_IDENTIFIER);
 514                         wire->str = ast_stack.back()->children.back()->str;
 515                         ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
 516                 } else
 517                         ast_stack.back()->children.back()->attributes["\\init"] = $3;
 518         };
 519
 520 wire_name:
 521         TOK_ID range {
 522                 AstNode *node = astbuf1->clone();
 523                 node->str = *$1;
 524                 append_attr_clone(node, albuf);
 525                 if (astbuf2 != NULL)
 526                         node->children.push_back(astbuf2->clone());
 527                 if ($2 != NULL) {
 528                         if (node->is_input || node->is_output)
 529                                 frontend_verilog_yyerror("Syntax error.");
 530                         if (!astbuf2) {
 531                                 AstNode *rng = new AstNode(AST_RANGE);
 532                                 rng->children.push_back(AstNode::mkconst_int(0, true));
 533                                 rng->children.push_back(AstNode::mkconst_int(0, true));
 534                                 node->children.push_back(rng);
 535                         }
 536                         node->type = AST_MEMORY;
 537                         node->children.push_back($2);
 538                 }
 539                 if (current_function_or_task == NULL) {
 540                         if (port_stubs.count(*$1) != 0) {
 541                                 if (!node->is_input && !node->is_output)
 542                                         frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $1->c_str());
 543                                 if (node->is_reg && node->is_input && !node->is_output)
 544                                         frontend_verilog_yyerror("Input port `%s' is declared as register.", $1->c_str());
 545                                 node->port_id = port_stubs[*$1];
 546                                 port_stubs.erase(*$1);
 547                         } else {
 548                                 if (node->is_input || node->is_output)
 549                                         frontend_verilog_yyerror("Module port `%s' is not declared in module header.", $1->c_str());
 550                         }
 551                         ast_stack.back()->children.push_back(node);
 552                 } else {
 553                         if (node->is_input || node->is_output)
 554                                 node->port_id = current_function_or_task_port_id++;
 555                         current_function_or_task->children.push_back(node);
 556                 }
 557                 delete $1;
 558         };
 559
 560 assign_stmt:
 561         TOK_ASSIGN assign_expr_list ';';
 562
 563 assign_expr_list:
 564         assign_expr | assign_expr_list ',' assign_expr;
 565
 566 assign_expr:
 567         expr '=' expr {
 568                 ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3));
 569         };
 570
 571 cell_stmt:
 572         attr TOK_ID {
 573                 astbuf1 = new AstNode(AST_CELL);
 574                 append_attr(astbuf1, $1);
 575                 astbuf1->children.push_back(new AstNode(AST_CELLTYPE));
 576                 astbuf1->children[0]->str = *$2;
 577                 delete $2;
 578         } cell_parameter_list_opt cell_list ';' {
 579                 delete astbuf1;
 580         } |
 581         attr tok_prim_wrapper {
 582                 astbuf1 = new AstNode(AST_PRIMITIVE);
 583                 astbuf1->str = *$2;
 584                 append_attr(astbuf1, $1);
 585                 delete $2;
 586         } prim_list ';' {
 587                 delete astbuf1;
 588         };
 589
 590 tok_prim_wrapper:
 591         TOK_PRIMITIVE {
 592                 $$ = $1;
 593         } |
 594         TOK_OR {
 595                 $$ = new std::string("or");
 596         };
 597
 598 cell_list:
 599         single_cell |
 600         cell_list ',' single_cell;
 601
 602 single_cell:
 603         TOK_ID {
 604                 astbuf2 = astbuf1->clone();
 605                 if (astbuf2->type != AST_PRIMITIVE)
 606                         astbuf2->str = *$1;
 607                 delete $1;
 608                 ast_stack.back()->children.push_back(astbuf2);
 609         } '(' cell_port_list ')';
 610
 611 prim_list:
 612         single_prim |
 613         prim_list ',' single_prim;
 614
 615 single_prim:
 616         single_cell |
 617         /* no name */ {
 618                 astbuf2 = astbuf1->clone();
 619                 ast_stack.back()->children.push_back(astbuf2);
 620         } '(' cell_port_list ')';
 621
 622 cell_parameter_list_opt:
 623         '#' '(' cell_parameter_list ')' | /* empty */;
 624
 625 cell_parameter_list:
 626         /* empty */ | cell_parameter |
 627         cell_parameter ',' cell_parameter_list;
 628
 629 cell_parameter:
 630         expr {
 631                 AstNode *node = new AstNode(AST_PARASET);
 632                 astbuf1->children.push_back(node);
 633                 node->children.push_back($1);
 634         } |
 635         '.' TOK_ID '(' expr ')' {
 636                 AstNode *node = new AstNode(AST_PARASET);
 637                 node->str = *$2;
 638                 astbuf1->children.push_back(node);
 639                 node->children.push_back($4);
 640                 delete $2;
 641         };
 642
 643 cell_port_list:
 644         /* empty */ | cell_port |
 645         cell_port ',' cell_port_list |
 646         /* empty */ ',' {
 647                 AstNode *node = new AstNode(AST_ARGUMENT);
 648                 astbuf2->children.push_back(node);
 649         } cell_port_list;
 650
 651 cell_port:
 652         expr {
 653                 AstNode *node = new AstNode(AST_ARGUMENT);
 654                 astbuf2->children.push_back(node);
 655                 node->children.push_back($1);
 656         } |
 657         '.' TOK_ID '(' expr ')' {
 658                 AstNode *node = new AstNode(AST_ARGUMENT);
 659                 node->str = *$2;
 660                 astbuf2->children.push_back(node);
 661                 node->children.push_back($4);
 662                 delete $2;
 663         } |
 664         '.' TOK_ID '(' ')' {
 665                 AstNode *node = new AstNode(AST_ARGUMENT);
 666                 node->str = *$2;
 667                 astbuf2->children.push_back(node);
 668                 delete $2;
 669         };
 670
 671 always_stmt:
 672         attr TOK_ALWAYS {
 673                 AstNode *node = new AstNode(AST_ALWAYS);
 674                 append_attr(node, $1);
 675                 ast_stack.back()->children.push_back(node);
 676                 ast_stack.push_back(node);
 677         } always_cond {
 678                 AstNode *block = new AstNode(AST_BLOCK);
 679                 ast_stack.back()->children.push_back(block);
 680                 ast_stack.push_back(block);
 681         } behavioral_stmt {
 682                 ast_stack.pop_back();
 683                 ast_stack.pop_back();
 684         } |
 685         attr TOK_INITIAL {
 686                 AstNode *node = new AstNode(AST_INITIAL);
 687                 append_attr(node, $1);
 688                 ast_stack.back()->children.push_back(node);
 689                 ast_stack.push_back(node);
 690                 AstNode *block = new AstNode(AST_BLOCK);
 691                 ast_stack.back()->children.push_back(block);
 692                 ast_stack.push_back(block);
 693         } behavioral_stmt {
 694                 ast_stack.pop_back();
 695                 ast_stack.pop_back();
 696         };
 697
 698 always_cond:
 699         '@' '(' always_events ')' |
 700         '@' '(' '*' ')' |
 701         '@' ATTR_BEGIN ')' |
 702         '@' '(' ATTR_END |
 703         '@' '*' |
 704         /* empty */;
 705
 706 always_events:
 707         always_event |
 708         always_events TOK_OR always_event |
 709         always_events ',' always_event;
 710
 711 always_event:
 712         TOK_POSEDGE expr {
 713                 AstNode *node = new AstNode(AST_POSEDGE);
 714                 ast_stack.back()->children.push_back(node);
 715                 node->children.push_back($2);
 716         } |
 717         TOK_NEGEDGE expr {
 718                 AstNode *node = new AstNode(AST_NEGEDGE);
 719                 ast_stack.back()->children.push_back(node);
 720                 node->children.push_back($2);
 721         } |
 722         expr {
 723                 AstNode *node = new AstNode(AST_EDGE);
 724                 ast_stack.back()->children.push_back(node);
 725                 node->children.push_back($1);
 726         };
 727
 728 opt_label:
 729         ':' TOK_ID {
 730                 $$ = $2;
 731         } |
 732         /* empty */ {
 733                 $$ = NULL;
 734         };
 735
 736 simple_behavioral_stmt:
 737         lvalue '=' expr {
 738                 AstNode *node = new AstNode(AST_ASSIGN_EQ, $1, $3);
 739                 ast_stack.back()->children.push_back(node);
 740         } |
 741         lvalue OP_LE expr {
 742                 AstNode *node = new AstNode(AST_ASSIGN_LE, $1, $3);
 743                 ast_stack.back()->children.push_back(node);
 744         };
 745
 746 // this production creates the obligatory if-else shift/reduce conflict
 747 behavioral_stmt:
 748         defattr |
 749         simple_behavioral_stmt ';' |
 750         hierarchical_id attr {
 751                 AstNode *node = new AstNode(AST_TCALL);
 752                 node->str = *$1;
 753                 delete $1;
 754                 ast_stack.back()->children.push_back(node);
 755                 ast_stack.push_back(node);
 756                 append_attr(node, $2);
 757         } opt_arg_list ';'{
 758                 ast_stack.pop_back();
 759         } |
 760         attr TOK_BEGIN opt_label {
 761                 AstNode *node = new AstNode(AST_BLOCK);
 762                 ast_stack.back()->children.push_back(node);
 763                 ast_stack.push_back(node);
 764                 append_attr(node, $1);
 765         } behavioral_stmt_list TOK_END opt_label {
 766                 if ($3 != NULL)
 767                         delete $3;
 768                 if ($7 != NULL)
 769                         delete $7;
 770                 ast_stack.pop_back();
 771         } |
 772         attr TOK_FOR '(' {
 773                 AstNode *node = new AstNode(AST_FOR);
 774                 ast_stack.back()->children.push_back(node);
 775                 ast_stack.push_back(node);
 776                 append_attr(node, $1);
 777         } simple_behavioral_stmt ';' expr {
 778                 ast_stack.back()->children.push_back($7);
 779         } ';' simple_behavioral_stmt ')' {
 780                 AstNode *block = new AstNode(AST_BLOCK);
 781                 ast_stack.back()->children.push_back(block);
 782                 ast_stack.push_back(block);
 783         } behavioral_stmt {
 784                 ast_stack.pop_back();
 785                 ast_stack.pop_back();
 786         } |
 787         attr TOK_IF '(' expr ')' {
 788                 AstNode *node = new AstNode(AST_CASE);
 789                 AstNode *block = new AstNode(AST_BLOCK);
 790                 AstNode *cond = new AstNode(AST_COND, AstNode::mkconst_int(1, false, 1), block);
 791                 ast_stack.back()->children.push_back(node);
 792                 node->children.push_back(new AstNode(AST_REDUCE_BOOL, $4));
 793                 node->children.push_back(cond);
 794                 ast_stack.push_back(node);
 795                 ast_stack.push_back(block);
 796                 append_attr(node, $1);
 797         } behavioral_stmt optional_else {
 798                 ast_stack.pop_back();
 799                 ast_stack.pop_back();
 800         } |
 801         attr case_type '(' expr ')' {
 802                 AstNode *node = new AstNode(AST_CASE, $4);
 803                 ast_stack.back()->children.push_back(node);
 804                 ast_stack.push_back(node);
 805                 append_attr(node, $1);
 806         } opt_synopsys_attr case_body TOK_ENDCASE {
 807                 case_type_stack.pop_back();
 808                 ast_stack.pop_back();
 809         };
 810
 811 case_type:
 812         TOK_CASE {
 813                 case_type_stack.push_back(0);
 814         } |
 815         TOK_CASEX {
 816                 case_type_stack.push_back('x');
 817         } |
 818         TOK_CASEZ {
 819                 case_type_stack.push_back('z');
 820         };
 821
 822 opt_synopsys_attr:
 823         opt_synopsys_attr TOK_SYNOPSYS_FULL_CASE {
 824                 if (ast_stack.back()->attributes.count("\\full_case") == 0)
 825                         ast_stack.back()->attributes["\\full_case"] = AstNode::mkconst_int(1, false);
 826         } |
 827         opt_synopsys_attr TOK_SYNOPSYS_PARALLEL_CASE {
 828                 if (ast_stack.back()->attributes.count("\\parallel_case") == 0)
 829                         ast_stack.back()->attributes["\\parallel_case"] = AstNode::mkconst_int(1, false);
 830         } |
 831         /* empty */;
 832
 833 behavioral_stmt_opt:
 834         behavioral_stmt |
 835         ';' ;
 836
 837 behavioral_stmt_list:
 838         behavioral_stmt_list behavioral_stmt |
 839         /* empty */;
 840
 841 optional_else:
 842         TOK_ELSE {
 843                 AstNode *block = new AstNode(AST_BLOCK);
 844                 AstNode *cond = new AstNode(AST_COND, new AstNode(AST_DEFAULT), block);
 845                 ast_stack.pop_back();
 846                 ast_stack.back()->children.push_back(cond);
 847                 ast_stack.push_back(block);
 848         } behavioral_stmt |
 849         /* empty */;
 850
 851 case_body:
 852         case_body case_item |
 853         /* empty */;
 854
 855 case_item:
 856         {
 857                 AstNode *node = new AstNode(AST_COND);
 858                 ast_stack.back()->children.push_back(node);
 859                 ast_stack.push_back(node);
 860         } case_select {
 861                 AstNode *block = new AstNode(AST_BLOCK);
 862                 ast_stack.back()->children.push_back(block);
 863                 ast_stack.push_back(block);
 864                 case_type_stack.push_back(0);
 865         } behavioral_stmt_opt {
 866                 case_type_stack.pop_back();
 867                 ast_stack.pop_back();
 868                 ast_stack.pop_back();
 869         };
 870
 871 case_select:
 872         case_expr_list ':' |
 873         TOK_DEFAULT;
 874
 875 case_expr_list:
 876         TOK_DEFAULT {
 877                 ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT));
 878         } |
 879         expr {
 880                 ast_stack.back()->children.push_back($1);
 881         } |
 882         case_expr_list ',' expr {
 883                 ast_stack.back()->children.push_back($3);
 884         };
 885
 886 rvalue:
 887         hierarchical_id '[' expr ']' '.' rvalue {
 888                 $$ = new AstNode(AST_PREFIX, $3, $6);
 889                 $$->str = *$1;
 890                 delete $1;
 891         } |
 892         hierarchical_id range {
 893                 $$ = new AstNode(AST_IDENTIFIER, $2);
 894                 $$->str = *$1;
 895                 delete $1;
 896         };
 897
 898 lvalue:
 899         rvalue {
 900                 $$ = $1;
 901         } |
 902         '{' lvalue_concat_list '}' {
 903                 $$ = $2;
 904         };
 905
 906 lvalue_concat_list:
 907         expr {
 908                 $$ = new AstNode(AST_CONCAT);
 909                 $$->children.push_back($1);
 910         } |
 911         expr ',' lvalue_concat_list {
 912                 $$ = $3;
 913                 $$->children.push_back($1);
 914         };
 915
 916 opt_arg_list:
 917         '(' arg_list optional_comma ')' |
 918         /* empty */;
 919
 920 arg_list:
 921         arg_list2 |
 922         /* empty */;
 923
 924 arg_list2:
 925         single_arg |
 926         arg_list ',' single_arg;
 927
 928 single_arg:
 929         expr {
 930                 ast_stack.back()->children.push_back($1);
 931         };
 932
 933 module_gen_body:
 934         module_gen_body gen_stmt |
 935         module_gen_body module_body_stmt |
 936         /* empty */;
 937
 938 // this production creates the obligatory if-else shift/reduce conflict
 939 gen_stmt:
 940         TOK_FOR '(' {
 941                 AstNode *node = new AstNode(AST_GENFOR);
 942                 ast_stack.back()->children.push_back(node);
 943                 ast_stack.push_back(node);
 944         } simple_behavioral_stmt ';' expr {
 945                 ast_stack.back()->children.push_back($6);
 946         } ';' simple_behavioral_stmt ')' gen_stmt {
 947                 ast_stack.pop_back();
 948         } |
 949         TOK_IF '(' expr ')' {
 950                 AstNode *node = new AstNode(AST_GENIF);
 951                 ast_stack.back()->children.push_back(node);
 952                 ast_stack.push_back(node);
 953                 ast_stack.back()->children.push_back($3);
 954         } gen_stmt opt_gen_else {
 955                 ast_stack.pop_back();
 956         } |
 957         TOK_BEGIN opt_label {
 958                 AstNode *node = new AstNode(AST_GENBLOCK);
 959                 node->str = $2 ? *$2 : std::string();
 960                 ast_stack.back()->children.push_back(node);
 961                 ast_stack.push_back(node);
 962         } module_gen_body TOK_END opt_label {
 963                 if ($2 != NULL)
 964                         delete $2;
 965                 if ($6 != NULL)
 966                         delete $6;
 967                 ast_stack.pop_back();
 968         };
 969
 970 opt_gen_else:
 971         TOK_ELSE gen_stmt | /* empty */;
 972
 973 expr:
 974         basic_expr {
 975                 $$ = $1;
 976         } |
 977         basic_expr '?' attr expr ':' expr {
 978                 $$ = new AstNode(AST_TERNARY);
 979                 $$->children.push_back($1);
 980                 $$->children.push_back($4);
 981                 $$->children.push_back($6);
 982                 append_attr($$, $3);
 983         };
 984
 985 basic_expr:
 986         rvalue {
 987                 $$ = $1;
 988         } |
 989         TOK_CONST {
 990                 $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back());
 991                 if ($$ == NULL)
 992                         log_error("Value conversion failed: `%s'\n", $1->c_str());
 993                 delete $1;
 994         } |
 995         TOK_STRING {
 996                 std::string str = *$1;
 997                 std::vector<RTLIL::State> data;
 998                 data.reserve(str.size() * 8);
 999                 for (size_t i = 0; i < str.size(); i++) {
1000                         unsigned char ch = str[str.size() - i - 1];
1001                         for (int j = 0; j < 8; j++) {
1002                                 data.push_back((ch & 1) ? RTLIL::S1 : RTLIL::S0);
1003                                 ch = ch >> 1;
1004                         }
1005                 }
1006                 $$ = AstNode::mkconst_bits(data, false);
1007                 $$->str = str;
1008                 delete $1;
1009         } |
1010         hierarchical_id attr {
1011                 AstNode *node = new AstNode(AST_FCALL);
1012                 node->str = *$1;
1013                 delete $1;
1014                 ast_stack.push_back(node);
1015                 append_attr(node, $2);
1016         } '(' arg_list optional_comma ')' {
1017                 $$ = ast_stack.back();
1018                 ast_stack.pop_back();
1019         } |
1020         TOK_TO_SIGNED attr '(' expr ')' {
1021                 $$ = new AstNode(AST_TO_SIGNED, $4);
1022                 append_attr($$, $2);
1023         } |
1024         TOK_TO_UNSIGNED attr '(' expr ')' {
1025                 $$ = new AstNode(AST_TO_UNSIGNED, $4);
1026                 append_attr($$, $2);
1027         } |
1028         '(' expr ')' {
1029                 $$ = $2;
1030         } |
1031         '{' concat_list '}' {
1032                 $$ = $2;
1033         } |
1034         '{' expr '{' expr '}' '}' {
1035                 $$ = new AstNode(AST_REPLICATE, $2, $4);
1036         } |
1037         '~' attr basic_expr %prec UNARY_OPS {
1038                 $$ = new AstNode(AST_BIT_NOT, $3);
1039                 append_attr($$, $2);
1040         } |
1041         basic_expr '&' attr basic_expr {
1042                 $$ = new AstNode(AST_BIT_AND, $1, $4);
1043                 append_attr($$, $3);
1044         } |
1045         basic_expr '|' attr basic_expr {
1046                 $$ = new AstNode(AST_BIT_OR, $1, $4);
1047                 append_attr($$, $3);
1048         } |
1049         basic_expr '^' attr basic_expr {
1050                 $$ = new AstNode(AST_BIT_XOR, $1, $4);
1051                 append_attr($$, $3);
1052         } |
1053         basic_expr OP_XNOR attr basic_expr {
1054                 $$ = new AstNode(AST_BIT_XNOR, $1, $4);
1055                 append_attr($$, $3);
1056         } |
1057         '&' attr basic_expr %prec UNARY_OPS {
1058                 $$ = new AstNode(AST_REDUCE_AND, $3);
1059                 append_attr($$, $2);
1060         } |
1061         OP_NAND attr basic_expr %prec UNARY_OPS {
1062                 $$ = new AstNode(AST_REDUCE_AND, $3);
1063                 append_attr($$, $2);
1064                 $$ = new AstNode(AST_LOGIC_NOT, $$);
1065         } |
1066         '|' attr basic_expr %prec UNARY_OPS {
1067                 $$ = new AstNode(AST_REDUCE_OR, $3);
1068                 append_attr($$, $2);
1069         } |
1070         OP_NOR attr basic_expr %prec UNARY_OPS {
1071                 $$ = new AstNode(AST_REDUCE_OR, $3);
1072                 append_attr($$, $2);
1073                 $$ = new AstNode(AST_LOGIC_NOT, $$);
1074         } |
1075         '^' attr basic_expr %prec UNARY_OPS {
1076                 $$ = new AstNode(AST_REDUCE_XOR, $3);
1077                 append_attr($$, $2);
1078         } |
1079         OP_XNOR attr basic_expr %prec UNARY_OPS {
1080                 $$ = new AstNode(AST_REDUCE_XNOR, $3);
1081                 append_attr($$, $2);
1082         } |
1083         basic_expr OP_SHL attr basic_expr {
1084                 $$ = new AstNode(AST_SHIFT_LEFT, $1, $4);
1085                 append_attr($$, $3);
1086         } |
1087         basic_expr OP_SHR attr basic_expr {
1088                 $$ = new AstNode(AST_SHIFT_RIGHT, $1, $4);
1089                 append_attr($$, $3);
1090         } |
1091         basic_expr OP_SSHL attr basic_expr {
1092                 $$ = new AstNode(AST_SHIFT_SLEFT, $1, $4);
1093                 append_attr($$, $3);
1094         } |
1095         basic_expr OP_SSHR attr basic_expr {
1096                 $$ = new AstNode(AST_SHIFT_SRIGHT, $1, $4);
1097                 append_attr($$, $3);
1098         } |
1099         basic_expr '<' attr basic_expr {
1100                 $$ = new AstNode(AST_LT, $1, $4);
1101                 append_attr($$, $3);
1102         } |
1103         basic_expr OP_LE attr basic_expr {
1104                 $$ = new AstNode(AST_LE, $1, $4);
1105                 append_attr($$, $3);
1106         } |
1107         basic_expr OP_EQ attr basic_expr {
1108                 $$ = new AstNode(AST_EQ, $1, $4);
1109                 append_attr($$, $3);
1110         } |
1111         basic_expr OP_NE attr basic_expr {
1112                 $$ = new AstNode(AST_NE, $1, $4);
1113                 append_attr($$, $3);
1114         } |
1115         basic_expr OP_GE attr basic_expr {
1116                 $$ = new AstNode(AST_GE, $1, $4);
1117                 append_attr($$, $3);
1118         } |
1119         basic_expr '>' attr basic_expr {
1120                 $$ = new AstNode(AST_GT, $1, $4);
1121                 append_attr($$, $3);
1122         } |
1123         basic_expr '+' attr basic_expr {
1124                 $$ = new AstNode(AST_ADD, $1, $4);
1125                 append_attr($$, $3);
1126         } |
1127         basic_expr '-' attr basic_expr {
1128                 $$ = new AstNode(AST_SUB, $1, $4);
1129                 append_attr($$, $3);
1130         } |
1131         basic_expr '*' attr basic_expr {
1132                 $$ = new AstNode(AST_MUL, $1, $4);
1133                 append_attr($$, $3);
1134         } |
1135         basic_expr '/' attr basic_expr {
1136                 $$ = new AstNode(AST_DIV, $1, $4);
1137                 append_attr($$, $3);
1138         } |
1139         basic_expr '%' attr basic_expr {
1140                 $$ = new AstNode(AST_MOD, $1, $4);
1141                 append_attr($$, $3);
1142         } |
1143         basic_expr OP_POW attr basic_expr {
1144                 $$ = new AstNode(AST_POW, $1, $4);
1145                 append_attr($$, $3);
1146         } |
1147         '+' attr basic_expr %prec UNARY_OPS {
1148                 $$ = new AstNode(AST_POS, $3);
1149                 append_attr($$, $2);
1150         } |
1151         '-' attr basic_expr %prec UNARY_OPS {
1152                 $$ = new AstNode(AST_NEG, $3);
1153                 append_attr($$, $2);
1154         } |
1155         basic_expr OP_LAND attr basic_expr {
1156                 $$ = new AstNode(AST_LOGIC_AND, $1, $4);
1157                 append_attr($$, $3);
1158         } |
1159         basic_expr OP_LOR attr basic_expr {
1160                 $$ = new AstNode(AST_LOGIC_OR, $1, $4);
1161                 append_attr($$, $3);
1162         } |
1163         '!' attr basic_expr %prec UNARY_OPS {
1164                 $$ = new AstNode(AST_LOGIC_NOT, $3);
1165                 append_attr($$, $2);
1166         };
1167
1168 concat_list:
1169         expr {
1170                 $$ = new AstNode(AST_CONCAT, $1);
1171         } |
1172         expr ',' concat_list {
1173                 $$ = $3;
1174                 $$->children.push_back($1);
1175         };
1176